JPH10161887A - Method and device for interruption signal synchronization - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the complexity of program operation by storing the values of respective counters when an interrupt signal is sent to an interrupt control part by referring to the value of a program counter and an instruction number counter. SOLUTION: By referring to the values held by the program counter and instruction number counter 122 by a comparator 13 of an interrupt synchronization part 12, the operation inputting an interrupt signal to an interrupt control apt 11 at time intervals corresponding to the priority of individual interrupts in timing to the execution of a program, and performing an interrupt process is added. Then the values of the program counter and instruction number counter 122 when the interrupt is reported to the interrupt control part 11 are saved in a history memory 121 and then used to reproduce the operation of the program. Consequently, the complexity of the program operation can be suppressed and the interrupt process can be prevented from being delayed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt signal synchronizing method, an interrupt signal synchronizing device, a data processing device, and a debugging method relating to an interrupt control technique in a CPU of a computer system.

[0002]

2. Description of the Related Art Conventionally, a computer system performs control by an interrupt signal in order to perform a process corresponding to an external event which occurs asynchronously with execution of a program. As shown in FIG. 5, a general CPU includes an arithmetic unit 51 including general-purpose registers and arithmetic circuits, and a program counter (P).
C) 52a and stack pointer register (SP) 52
b, and a control unit 52 including an interrupt control unit 52c.

[0003] Events occurring outside the computer system are denoted by C
To communicate to the PU 50, an interrupt signal is assigned to each event. When an external event targeted for interrupt processing occurs, the occurrence of the event is notified by an interrupt signal to the CP.
The interrupt control unit 52c is transmitted to the interrupt control unit 52c of U50.
“c” interrupts the program that has been executed up to that time, and starts an interrupt process corresponding to each external event.

By adopting such a method, it is possible to start and execute a processing program corresponding to various events whose timing and order cannot be predicted simply and efficiently.

[0005]

In the conventional interrupt processing method, the interrupt processing corresponding to the interrupt factor can be started quickly, but at an arbitrary point in time when the program is executed, except for the part where the interrupt is prohibited in the program. Interrupts can occur. For this reason, the position at which the execution of the program is interrupted changes due to the change in the timing at which the interrupt occurs, and the operation of the program is complicated.

In particular, in equipment control and the like, since many processings that occur asynchronously are often implemented with respective processing programs as interrupt processing, it is difficult to create programs and debug work is not easy.

This problem can be reduced to some extent by finely controlling interrupt prohibition / permission in a program. However, the overhead caused by inserting an instruction for interrupt control into the program and an error in interrupt control are increased. Another problem is that it is more likely that the program will not operate correctly.

[0008] The present invention has been made in view of the above circumstances,
By controlling the prohibition / permission of interrupts without relying on the user program, it is possible to greatly limit the points at which interrupts can be accepted without impairing the efficiency of interrupt processing, thereby enabling the program operation by interrupts. An object of the present invention is to provide an interrupt signal synchronizing method, an interrupt signal synchronizing device, a data processing device, and a debugging method that suppress complexity and facilitate creation and debugging of a program.

[0009]

According to the present invention, in an interrupt control device, an instruction number counter for counting the number of instructions executed by a processor is provided at a preceding stage of an interrupt control unit which receives an interrupt signal and starts an interrupt process. A comparator for transmitting an interrupt signal to an interrupt control unit at a time interval according to the priority of each interrupt in accordance with the execution of the program with reference to the values held by the program counter and the instruction number counter; and An interrupt synchronization unit comprising a history memory for storing the value of the program counter and the number of instructions when an interrupt is transmitted to the unit is provided.

Further, according to the present invention, in the above interrupt control apparatus, an instruction number counter is provided for each interrupt signal instead of a single instruction number counter, and an interrupt signal is generated in the instruction number counter. At that point, the maximum number of instructions that are allowed to be executed before the corresponding interrupt processing is activated is set. Each time one instruction is executed, the countdown is performed by one. If the value of the instruction number counter becomes zero before the execution, the acceptance of an interrupt is permitted.

Further, according to the present invention, there is provided the above-described interrupt control device, wherein the processor is configured to execute the interrupt prohibition instruction for disabling the processor from accepting the interrupt before actually disabling the processor for the interrupt. It is characterized in that a function of performing interrupt processing for all interrupt signals that have been generated but not transmitted to the interrupt control unit by the synchronization unit is added.

Further, according to the present invention, in the above interrupt control apparatus, a program counter when an interrupt signal is generated is stored in a history memory of an interrupt synchronizing unit, and the operation of the program is reproduced during debugging. The timing of generating an interrupt signal is determined from the program code and the value of the program counter stored in the history memory.

Further, according to the present invention, in the above interrupt control apparatus, the interrupt signal is generated before the processor is actually disabled in response to an interrupt disable command for disabling the processor from accepting the interrupt. However, the present invention is characterized in that a function of performing interrupt processing for all interrupt signals not transmitted to the interrupt control unit by the synchronization unit is added.

Further, according to the present invention, in a data processing device provided with the above interrupt control device, a program counter at the time of occurrence of an interrupt signal is stored in a history memory of the interrupt synchronization unit, and the operation of the program at the time of debugging is performed. Is reproduced, the timing for generating an interrupt signal is determined from the program code and the value of the program counter stored in the history memory.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, the interrupt control unit 11 includes:
A normal interrupt signal and an interrupt signal that has been synchronized by the interrupt synchronization unit 12 are input.

The interrupt synchronizer 12 transmits an interrupt signal to the interrupt controller 11 at regular intervals in accordance with the execution of the program. At this time, the interval at which the interrupt signal is transmitted to the interrupt control unit 11 is set short for interrupts with high priority and long for interrupts with low priority.

By performing this control, the number of points at which interrupt processing can be started in the program is greatly reduced. At this time, there is a time delay from the occurrence of the interrupt to the acceptance of the interrupt by the interrupt control unit 11, but since this is a very short time, it does not usually cause a problem.

As to the interrupt processing in which a slight delay causes a problem, an interrupt signal is directly input to the interrupt control unit 11 without passing through the interrupt synchronization unit 12 as in the conventional method, and no delay occurs. I can do it.

FIG. 2 shows the interrupt synchronizer 12 shown in FIG.
FIG. 3 is a diagram showing an example of the configuration of FIG. Interrupt synchronizer 12 shown in FIG.
Generates an interrupt permission signal based on whether or not some lower bits of the program counter (PC) are "0".
By allocating a permission signal having a small number of bits for checking “0” as a permission signal of a high-priority interrupt signal, a high-priority interrupt can be accepted more frequently.

For example, assuming that the instruction length is 4 bytes, in the example of FIG. 2, as shown in FIG.
(Interrupt 1) is executed every time two instructions are executed, and interrupt signal 2
In (interrupt 2), each time four instructions are executed, an interrupt is accepted (see ← in the figure). Therefore, the points at which interrupts are accepted in the program are ２ and 分 の, respectively, which is significantly reduced as compared with the normal method.

At this time, the time from the generation of the interrupt to the reception of the interrupt is the same as that of the interrupt signal 5.
This is only an execution time of 32 instructions at most, and does not cause a problem in normal processing.

When the program executes a small loop, if the loop portion enters between the points for accepting interrupts, if only the value of the program counter is used, unless the program exits the loop, the program is forever divided. May not be accepted.

The instruction counter 122 shown in FIG. 2 provided in the interrupt synchronization section 12 prevents this. The instruction counter 122 counts up by one each time the CPU 10 executes one instruction of the program. Comparator 1
By referring to this in step 3, an interrupt can be accepted even when the program is executing a small loop.

In a program, a section where interrupts are prohibited may be set. In this case, it may take a very long time from the occurrence of an interrupt to the start of interrupt processing.

Therefore, as a function of the interrupt prohibition instruction, C
Before the PU 10 is set to the interrupt disabled state, an operation for directly taking in all interrupt signals into the interrupt control unit 11 and performing an interrupt process is added.

The history memory 121 shown in FIG. 2 stores the values of the program counter and the instruction counter 122 at the time when the interrupt is accepted, and is used for reproducing the operation of the program at the time of debugging.

By performing the above-described control, the combination of the timing and the order in which the interrupt processing is started is greatly reduced, and the degree of the effect of the external operation on the operation of the program is reduced. Is reduced, and the work of developing and debugging the program is facilitated.

Also, in order to reproduce the operation of the program at the time of debugging, when an interrupt signal is input in accordance with the execution of the program, the timing of inputting the interrupt signal in instruction units in the conventional method must be planned. This is a very difficult task for a CPU that operates on a computer.

On the other hand, in the method according to the above-described embodiment of the present invention, since the acceptance period in the interrupt synchronization unit 12 may be set as a unit, the timing control of the interrupt signal input is greatly relaxed. Debugging is facilitated.

FIG. 4 is a diagram showing another example of the configuration of the interrupt synchronization section 12. As shown in FIG. In this configuration example, an independent instruction counter (IC1, IC2,...) Is provided for each interrupt signal. The width of each instruction number counter is equal to the number of bits of the program counter (PC) referred to by the comparator 41 in determining whether to accept an interrupt signal.

Each instruction counter is set to a maximum value as an initial value when an interrupt signal is generated, and is decremented every time one instruction is executed. Also, the comparator 4
When the bit range of the program counter referred to in each judgment condition in 1 becomes "0", the corresponding instruction number counter is cleared to zero.

In this case, as compared with the case where the number of instruction counters is one as shown in FIG. 2, there is an advantage that the timing of accepting an interrupt when the program is executing a small loop is determined. . The present invention is not limited to the above embodiment, but can be applied to all embedded control processors.

[0033]

As described above in detail, according to the present invention, the provision of the interrupt synchronization section at the preceding stage of the interrupt control section allows
The point at which interrupt processing can occur in a program can be reduced without significantly reducing the efficiency of interrupt processing, regardless of software, greatly simplifying program behavior in programs with many interrupt processing. This makes program development and debugging easier.

Further, according to the present invention, by allowing an allowable delay to be set for each interrupt signal, reception of an interrupt signal is reduced as compared with the case where a single instruction number counter is used. Is faster than necessary.

Further, according to the present invention, if the processor enters the interrupt disabled state in a state where the interrupt synchronizer has stopped accepting the interrupt signal, the delay time from the occurrence of the interrupt until the interrupt processing is performed. Since the interrupt prohibition instruction may have a function of detecting an interrupt signal and activating an interrupt process, a delay in interrupt processing can be prevented.

Further, according to the present invention, when trying to reproduce the behavior of a program in a debugging operation, it is particularly fast to input an externally applied signal such as an interrupt signal to the processor at an accurate timing. Although it becomes difficult with a simple microprocessor or the like, the interrupt control method of the present invention as described above makes it possible to reproduce an interrupt at an accurate timing even if an interrupt signal is input with a timing error over several instructions. By referring to the program counter value and the program code stored in the history memory, the timing at which an interrupt signal can be given can be determined within a certain allowable range, and the operation of the program can be reproduced in a debugging operation. Input the interrupt signal to the processor It can be input interrupt signal without being limited to the exact timing. As a result, the device for reproducing the interrupt signal can be simplified, and the debugging work is facilitated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an interrupt synchronization unit in the embodiment.

FIG. 3 is a conceptual diagram showing a relationship between an interrupt signal and instruction execution in the embodiment.

FIG. 4 is a block diagram showing the configuration of another interrupt synchronization unit in the embodiment.

FIG. 5 is a block diagram showing a conventional example.

[Explanation of symbols]

 10: CPU, 11: Interrupt control unit, 12: Interrupt synchronization unit, 13: Comparator, 121: History memory, 122: Instruction number counter.

Claims (7)

[Claims] An interrupt synchronization unit is provided at a stage preceding an interrupt control unit for activating an interrupt process, and the interrupt synchronization unit includes:
Interrupt signals transmitted to the interrupt control unit at time intervals according to the priority of individual interrupts in accordance with the execution of the program, thereby reducing points at which interrupt processing on the program can occur; Synchronization method. 2. An instruction control unit for receiving an interrupt signal and activating an interrupt process, comprising: an instruction number counter for counting the number of instructions executed by a processor; and a value held by the instruction number counter and a program counter. A comparator for transmitting an interrupt signal to an interrupt control unit at a time interval according to the priority of each interrupt in accordance with the execution of the program; and a program counter and an instruction number counter when the interrupt is transmitted to the interrupt control unit. An interrupt control device comprising an interrupt synchronization unit having a history memory for storing a value. 3. An instruction number counter is provided for each interrupt signal in place of a single instruction number counter, and the instruction number counter is provided in the instruction number counter when the corresponding interrupt processing is started when an interrupt signal is generated. The maximum number of instructions permitted to be set is set, and the instruction counter is sequentially counted down each time an instruction is executed, and the value of the instruction number counter is reduced before the interrupt acceptance is determined from the value of the program counter. 3. The interrupt control device according to claim 2, wherein when a predetermined value is reached, acceptance of an interrupt is permitted. 4. An interrupt signal is generated in response to an interrupt prohibition instruction for disabling the processor from accepting an interrupt before the processor is actually disabled, but the synchronization unit notifies the interrupt control unit of the interrupt signal. 4. The interrupt control device according to claim 2, wherein a function of performing an interrupt process for all interrupt signals not transmitted is added. 5. A program counter when an interrupt signal is generated is stored in a history memory of the interrupt synchronization unit,
4. The interrupt according to claim 2, wherein when reproducing the operation of the program at the time of debugging, the timing of generating an interrupt signal is determined from the code of the program and the value of the program counter stored in the history memory. Control device. 6. An instruction control unit for receiving an interrupt signal and activating an interrupt process, refers to an instruction number counter for counting the number of instructions executed by the processor and a value held by the instruction number counter and the program counter. A comparator for transmitting an interrupt signal to an interrupt control unit at a time interval according to the priority of each interrupt in accordance with the execution of the program; and a program counter and an instruction number counter when the interrupt is transmitted to the interrupt control unit. In a data processing device having an interrupt control device provided with an interrupt synchronizing unit having a history memory for storing a value, the processor is responsive to an interrupt prohibition instruction for disabling a processor from accepting an interrupt. Before the interrupt was actually disabled, the interrupt signal was generated but not transmitted to the interrupt control unit by the synchronization unit. The data processing apparatus characterized by having means for performing interrupt processing for all write signal. 7. An interrupt synchronizing unit, wherein an interrupt prohibition instruction for disabling a processor from accepting an interrupt is provided.
Before actually disabling the processor for interrupts, in a data processing apparatus having means for performing interrupt processing for all interrupt signals generated but not transmitted to the interrupt control unit by the synchronization unit, The program counter at the time of the occurrence of the interrupt signal is stored in the history memory of the synchronization unit, and when the operation of the program is reproduced during debugging, the program code and the value of the program counter stored in the history memory are stored. A debugging method characterized by determining a timing for generating an interrupt signal.