[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JPH10142271A - Measuring method for pattern electrostatic capacity of circuit board - Google Patents

Measuring method for pattern electrostatic capacity of circuit board

Info

Publication number
JPH10142271A
JPH10142271A JP8317090A JP31709096A JPH10142271A JP H10142271 A JPH10142271 A JP H10142271A JP 8317090 A JP8317090 A JP 8317090A JP 31709096 A JP31709096 A JP 31709096A JP H10142271 A JPH10142271 A JP H10142271A
Authority
JP
Japan
Prior art keywords
pattern
circuit board
capacitance
common electrode
measured
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8317090A
Other languages
Japanese (ja)
Other versions
JP3599929B2 (en
Inventor
Yoshinori Sato
義典 佐藤
Harumasa Tanabe
治正 田辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hioki EE Corp
Original Assignee
Hioki EE Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hioki EE Corp filed Critical Hioki EE Corp
Priority to JP31709096A priority Critical patent/JP3599929B2/en
Publication of JPH10142271A publication Critical patent/JPH10142271A/en
Application granted granted Critical
Publication of JP3599929B2 publication Critical patent/JP3599929B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Measurement Of Resistance Or Impedance (AREA)

Abstract

PROBLEM TO BE SOLVED: To facilitate the measurement of the electrostatic capacity of a surface pattern even in the case where a pattern provided on the surface of a detected circuit board and a mat pattern provided on its back are mutually conducted. SOLUTION: An electrode 10 being common to all surface patterns is arranged on the side of the back of a detected circuit board 24 provided with a plurality of patterns 28 on the surface, and an insulating layer 30 is insertedly set between the circuit board 24 and a common electrode 10, and a probe 16 is brought into contact with the surface pattern 28 being a measurement object, and low or high voltage is applied to them, and low or high voltage is applied to the common electrode, and a current flowing in the surface pattern 28 is measured to compute an electrostatic capacity between the surface pattern and the common electrode 10.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はX−Y方式インサー
キットテスタ、ベアボードテスタ等の回路基板検査装置
による回路基板のパターン静電容量測定方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for measuring a pattern capacitance of a circuit board using a circuit board inspection apparatus such as an XY type in-circuit tester, a bare board tester, or the like.

【0002】[0002]

【従来の技術】従来、実装基板即ち多数の電子部品等を
半田付けしたプリント基板はインサーキットテスタを用
いて、その基板の必要な測定点に適宜プローブの先端を
接触させ、それ等の各部品の有無を電気的に検出し、或
いは各部品の特性値を電気的に測定する等して基板の良
否の判定を行っている。特に、X−Y方式インサーキッ
トテスタでは被検査回路基板を乗せて固定する測定台上
にX−Yユニットを設置し、そのX軸方向に可動するア
ームの上にY軸方向に可動するZ軸ユニットを備え、そ
のZ軸ユニットでプローブをZ軸方向に可動可能に支持
している。そして、検査時にはX−Yユニットを制御し
て、プローブを基板の上方からX軸、Y軸、Z軸方向に
それぞれ適宜移動し、予め設定した各測定点に順次接触
する。それ故、X−Y方式インサーキットテスタは多品
種少量生産の回路基板の検査に適する。
2. Description of the Related Art Conventionally, a mounting substrate, that is, a printed circuit board on which a large number of electronic components are soldered, uses an in-circuit tester to appropriately contact the tip of a probe to a required measurement point on the substrate, and to connect each of those components. The quality of the board is determined by electrically detecting the presence or absence of the component or by electrically measuring the characteristic value of each component. In particular, in an XY-system in-circuit tester, an XY unit is installed on a measuring table on which a circuit board to be inspected is mounted and fixed, and a Z-axis movable in the Y-axis direction on an arm movable in the X-axis direction. A unit is provided, and the probe is movably supported in the Z-axis direction by the Z-axis unit. At the time of inspection, the XY unit is controlled, the probe is appropriately moved in the X-axis, Y-axis, and Z-axis directions from above the substrate, and sequentially comes in contact with preset measurement points. Therefore, the XY type in-circuit tester is suitable for inspection of a circuit board of a large variety of small production.

【0003】このようなX−Y方式インサーキットテス
タを用いて、プリント基板に設けた配線パターンの静電
容量の測定を行なうと、パターンの断線、ショート等を
検査することができる。その際、図9に示すような板体
を共通電極10にし、その上に複数のパターン12(1
2a、……12f)を設けた表面を上にして検査の対象
となるプリント基板14を乗せる。そして、測定の対象
としたパターン12aにプローブ16を接触し、そのプ
ローブ16に計測部18に備えた交流電圧源20から高
位又は低位の電圧を加え、共通電極10に低位又は高位
の電圧を加えると、そのパターン12aに流れる電流を
交流電流計22により測定し、それ等の電圧値と電流値
とからパターン12aと共通電極10の間の静電容量を
算出できる。なお、静電容量Cは電圧の実効値をE、電
流の実効値をI、周波数をfとすると、C=I/2πf
Eの式より算出できる。
When the capacitance of a wiring pattern provided on a printed circuit board is measured using such an XY type in-circuit tester, disconnection or short-circuit of the pattern can be inspected. At this time, a plate as shown in FIG. 9 is used as the common electrode 10 and a plurality of patterns 12 (1
The printed circuit board 14 to be inspected is placed with the surface provided with 2a,... 12f) facing up. Then, the probe 16 is brought into contact with the pattern 12 a to be measured, and a high or low voltage is applied to the probe 16 from the AC voltage source 20 provided in the measuring unit 18, and a low or high voltage is applied to the common electrode 10. Then, the current flowing through the pattern 12a is measured by the AC ammeter 22, and the capacitance between the pattern 12a and the common electrode 10 can be calculated from the voltage value and the current value. Here, assuming that the effective value of the voltage is E, the effective value of the current is I, and the frequency is f, the capacitance C is C = I / 2πf
It can be calculated from E.

【0004】このようにしてパターン12aの静電容量
を算出した後、先に良基板により求めておいた基準値と
比較することにより、パターン12aの静電容量が小さ
い時には断線、大きい時にはショートと判定する。な
お、共通電極10は全てのパターン12に共通な電極で
あるため、他の各パターン12b、……12fについて
も同様の判定を行なえる。
After the capacitance of the pattern 12a is calculated in this way, it is compared with a reference value previously obtained from a good substrate. judge. Since the common electrode 10 is an electrode common to all the patterns 12, the same determination can be made for the other patterns 12b,..., 12f.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、このよ
うな共通電極10を用いても、図10に示すようにプリ
ント基板24の裏面にベタパターン26が設けられてお
り、表面の例えばパターン28aとベタパターン26と
が導通していると、そのベタパターン26にレジストが
施されていない場合、パターン28aと共通電極10も
導通するため、パターン28aの静電容量を測定するこ
とができない。それ故、パターン28aの断線、ショー
ト等を検査できい。なお、ベタパターン26にレジスト
が施されていても、スルホールがあるとその部分が絶縁
されていないためやはり問題がある。
However, even when such a common electrode 10 is used, the solid pattern 26 is provided on the back surface of the printed circuit board 24 as shown in FIG. When the pattern 26 is conductive, if the resist is not applied to the solid pattern 26, the pattern 28a and the common electrode 10 are also conductive, so that the capacitance of the pattern 28a cannot be measured. Therefore, it is not possible to inspect the pattern 28a for disconnection, short circuit and the like. Even if a resist is applied to the solid pattern 26, if there is a through hole, that part is not insulated, so that there is still a problem.

【0006】本発明はこのような従来の問題点に着目し
てなされたものであり、第1に被検査回路基板の表面に
設けたパターンと裏面に設けたベタパターンが導通して
いる場合にも、その表面パターンの静電容量の測定を行
なえる回路基板のパターン静電容量測定方法を提供する
ことを目的とする。
The present invention has been made in view of such conventional problems. First, the present invention relates to a case where a pattern provided on the front surface of a circuit board to be inspected and a solid pattern provided on the back surface are conductive. It is another object of the present invention to provide a method of measuring the capacitance of a circuit board, which can measure the capacitance of the surface pattern.

【0007】又、第2に被検査回路基板の表面に設けた
パターンと裏面に設けたベタパターンが導通している場
合にも、その表面パターンの静電容量の測定を行なえる
ばかりでなく、検査スピードを高速化できる回路基板の
パターン静電容量測定方法を提供することを目的とす
る。
Second, even when the pattern provided on the front surface of the circuit board to be inspected and the solid pattern provided on the back surface are conducting, not only can the capacitance of the surface pattern be measured, It is an object of the present invention to provide a method for measuring the capacitance of a circuit board pattern that can increase the inspection speed.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するため
に、本発明による第1目的対応の回路基板のパターン静
電容量測定方法では表面に複数のパターンを設けた被検
査回路基板の裏面側に、それ等の全ての表面パターンに
共通な電極を配置し、その測定の対象とした表面パター
ンにプローブを接触して高位又は低位の電圧を加え、共
通電極に低位又は高位の電圧を加えて、その表面パター
ンに流れる電流を測定し、その表面パターンと共通電極
間の静電容量を算出するという手順を踏む。そして、回
路基板と共通電極間に絶縁層を介在することを特徴とす
る。
In order to achieve the above object, in the method for measuring the capacitance of a circuit board according to the first object of the present invention, the back side of a circuit board to be inspected having a plurality of patterns provided on the front side. In addition, an electrode common to all of these surface patterns is arranged, a probe is brought into contact with the surface pattern to be measured, and a high or low voltage is applied, and a low or high voltage is applied to the common electrode. , The current flowing through the surface pattern is measured, and the capacitance between the surface pattern and the common electrode is calculated. Further, an insulating layer is interposed between the circuit board and the common electrode.

【0009】又、第2目的対応の回路基板のパターン静
電容量測定方法では表面に複数のパターンを設けた被検
査回路基板の裏面側に、それ等の全ての表面パターンに
共通な電極を配置し、複数本の各プローブを同時に全表
面パターンから選んだ対応する各表面パターンにそれぞ
れ接触して、その共通電極に高位又は低位の電圧を加
え、測定の対象とした表面パターンに低位又は高位の電
圧を加えて、その表面パターンに流れる電流を測定し、
その表面パターンと共通電極間の静電容量を算出すると
いう手順を踏む。そして、その回路基板と共通電極間に
絶縁層を介在し、プローブが接触した測定しない各表面
パターンに共通電極と同一電位電圧を印加することを特
徴とする。
In the method for measuring the pattern capacitance of a circuit board corresponding to the second object, an electrode common to all the surface patterns is arranged on the back side of a circuit board to be inspected having a plurality of patterns provided on the front side. Then, a plurality of probes are simultaneously brought into contact with the corresponding surface patterns selected from all the surface patterns respectively, and a high or low voltage is applied to the common electrode, and a low or high voltage is applied to the surface pattern to be measured. Apply a voltage and measure the current flowing through the surface pattern,
The procedure is to calculate the capacitance between the surface pattern and the common electrode. An insulating layer is interposed between the circuit board and the common electrode, and the same potential voltage as that of the common electrode is applied to each of the unmeasured surface patterns contacted by the probe.

【0010】[0010]

【発明の実施の形態】以下、添付図面に基づいて、本発
明の実施の形態を説明する。図1は本発明を適用した1
プローブ移動型のX−Y方式インサーキットテスタによ
る被検査回路基板のパターン静電容量測定時の回路図で
ある。本発明による回路基板のパターン静電容量測定方
法では共通電極10の上面全域にプラスチック製等の絶
縁シート30を付着して使用する。それ故、図10で示
す従来のものと異なり、共通電極10の上に被検査回路
基板24を乗せても、絶縁シート30が絶縁層となっ
て、被検査回路基板24と共通電極10との間に介在す
る。そして、被検査回路基板24の表面にある例えばパ
ターン28aと裏面にあるパターン26とが導通してい
ても、ベタパターン26と共通電極10とは導通しなく
なる。
Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a diagram 1 showing the application of the invention.
FIG. 4 is a circuit diagram when a pattern capacitance of a circuit board to be inspected is measured by a probe moving type XY in-circuit tester. In the method for measuring the pattern capacitance of a circuit board according to the present invention, an insulating sheet 30 made of plastic or the like is attached to the entire upper surface of the common electrode 10 for use. Therefore, unlike the conventional device shown in FIG. 10, even if the circuit board 24 to be inspected is placed on the common electrode 10, the insulating sheet 30 becomes an insulating layer, and the circuit board 24 and the common electrode 10 Intervene in between. Then, even if the pattern 28a on the front surface of the circuit board 24 to be inspected and the pattern 26 on the rear surface are conductive, the solid pattern 26 and the common electrode 10 are not conductive.

【0011】そこで、従来と同様にして測定の対象とし
た表面の1箇所のパターン28に1本のプローブ16を
接触し、そのパターン28に計測部18に備えた交流電
圧源20から高位電圧を加え、共通電極10に低位電圧
を加えると、そのパターン28に流れる電流を交流電流
計22により測定し、それ等の電圧値と電流値とからパ
ターン28と共通電極10の間の静電容量Cを算出でき
る。その際、パターン28aの静電容量Caはパターン
28aとベタパターン26とが導通しているため、図2
示すようにベタパターン26と共通電極10との間の静
電容量C2 と等しくなる。
Therefore, as in the prior art, one probe 16 is brought into contact with one pattern 28 on the surface to be measured, and a high voltage is applied to the pattern 28 from the AC voltage source 20 provided in the measuring unit 18. In addition, when a low voltage is applied to the common electrode 10, the current flowing through the pattern 28 is measured by the AC ammeter 22, and the capacitance C between the pattern 28 and the common electrode 10 is measured based on the voltage value and the current value. Can be calculated. At this time, since the pattern 28a and the solid pattern 26 are conducting, the capacitance Ca of the pattern 28a
As shown, the capacitance becomes equal to the capacitance C2 between the solid pattern 26 and the common electrode 10.

【0012】又、他の各パターン28(28b、……2
8f)の静電容量C(Cb、……Cf)は各パターン2
8(28b、……28f)とベタパターン26との間の
静電容量をC1 (C1b、……C1f)とし、ベタパター
ン26と共通電極10との間の静電容量をC2 とする
と、各パターン28につき図3に示すように両静電容量
C1 とC2 は直列接続になるため、各パターン28の静
電容量CはC=C1 ・C2 /(C1 +C2 )となる。し
かも、裏面のパターンがベタパターン26であると、C
1 ≪C2 であるため、C≒C1 となる。それ故、各パタ
ーン28b、……28fの静電容量Cb、……Cfはそ
れぞれCb≒C1b、……Cf≒C1f となる。この結果、
パターン28aとベタパターン26とが導通していて
も、全ての各パターン28につき静電容量Cをそれぞれ
算出できることになり、各パターン28の断線、ショー
ト等の判定を行なえる。なお、各パターン28に低位電
圧を加え、共通電極10に高位電圧を加えてもよい。
Each of the other patterns 28 (28b,..., 2)
8f) of the capacitance C (Cb,... Cf)
8 (28b,..., 28f) and the solid pattern 26 are represented by C1 (C1b,... C1f), and the capacitance between the solid pattern 26 and the common electrode 10 is represented by C2. Since the capacitances C1 and C2 are connected in series as shown in FIG. 3 for the pattern 28, the capacitance C of each pattern 28 is C = C1.C2 / (C1 + C2). Moreover, if the pattern on the back side is the solid pattern 26, C
Since 1≪C2, C ≒ C1. Therefore, the capacitances Cb,..., Cf of the respective patterns 28b,..., 28f are Cb ≒ C1b,. As a result,
Even when the pattern 28a and the solid pattern 26 are electrically connected, the capacitance C can be calculated for each of the patterns 28, and it is possible to determine whether each pattern 28 is disconnected or short-circuited. Note that a low voltage may be applied to each pattern 28 and a high voltage may be applied to the common electrode 10.

【0013】しかしながら、このような測定方法では各
パターン28の静電容量Cを測定する毎に、プローブ1
6を1本Z軸方向に上げ下げする等して移動しなければ
ならないため、パターンの数が多いと測定時間がかなり
必要となり、検査をスピード化することができない。そ
こで、複数本のプローブを同時に上げ下げする等して移
動することが考えられる。例えば、図4に示すように3
本のプローブ16(16a、16b、16c)を同時に
下げて対応する各パターン28(28a、28b、28
c)にそれぞれ接触する。その際、本出願人が先に提示
した特願平6−172136号等に示す多ピンプローブ
ユニットを用いるとよい。なお、32は測定の対象とす
るパターン28を選ぶスキャナである。
However, in such a measuring method, each time the capacitance C of each pattern 28 is measured, the probe 1
6 must be moved up and down in the Z-axis direction or the like. Therefore, if the number of patterns is large, the measurement time is considerably required, and the inspection cannot be speeded up. Therefore, it is conceivable to move a plurality of probes by simultaneously raising and lowering them. For example, as shown in FIG.
The probe 16 (16a, 16b, 16c) is simultaneously lowered and the corresponding pattern 28 (28a, 28b, 28
c) respectively. At this time, it is preferable to use a multi-pin probe unit disclosed in Japanese Patent Application No. 6-172136 previously presented by the present applicant. A scanner 32 selects a pattern 28 to be measured.

【0014】しかし、例えばパターン28bの静電容量
Cbを測定しようとして、図5に示すように共通電極1
0に高位電圧Hを加え、パターン28bに低位電圧Lを
加えると、バス線のように各パターンが至近距離で隣接
している場合や内層にベタパターンを含む場合等にはプ
ローブ28a、b間に浮遊の静電容量C01が存在し、プ
ローブ16b、c間に浮遊の静電容量C02が存在するた
め、静電容量Cb として誤ってC01+C1b+C02・C1c
/(C02+C1c)を測定してしまい、C1bを測定できな
い。又、図6に示すように測定しないプローブ16a、
cの電位電圧をガード(アース)にすると、ガード効果
でベタパターン26と導通しているパターン28aに電
流が流れて、パターン28bに電流が流れなくなるた
め、C1bを測定できない。
However, in order to measure the capacitance Cb of the pattern 28b, for example, as shown in FIG.
When a high voltage H is applied to 0 and a low voltage L is applied to the pattern 28b, when the patterns are adjacent to each other at a close distance like a bus line or when a solid pattern is included in the inner layer, etc. , A floating capacitance C01 exists between the probes 16b and 16c, and a floating capacitance C02 exists between the probes 16b and c. Therefore, the capacitance Cb is erroneously determined as C01 + C1b + C02.C1c.
/ (C02 + C1c) is measured and C1b cannot be measured. In addition, as shown in FIG.
If the potential voltage of c is set to guard (earth), a current flows through the pattern 28a that is in conduction with the solid pattern 26 due to the guard effect, and no current flows through the pattern 28b, so that C1b cannot be measured.

【0015】そこで、パターン28aの静電容量Caを
測定する場合には、図7に示すように共通電極10に高
位電圧Hを加え、パターン28aに低位電圧Lを加え、
更に測定しない各パターン28b、cに共通電極10と
同一の高位電圧Hをそれぞれ加える。すると、各パター
ン28b、cと浮遊の静電容量C02にはいずれも電流が
流れないため、静電容量C1b、C1c、C02の影響がなく
なって測定値CはC=C01+C2 となる。そこで、測定
物たる被検査回路基板24のない状態で浮遊の静電容量
C01を測定して測定値Cより差し引くとC−C01=C2
となり、パターン28aの静電容量Caを測定できる。
To measure the capacitance Ca of the pattern 28a, a high voltage H is applied to the common electrode 10 and a low voltage L is applied to the pattern 28a as shown in FIG.
Further, the same high voltage H as that of the common electrode 10 is applied to each of the patterns 28b and c that are not measured. Then, no current flows through each of the patterns 28b and c and the floating capacitance C02, so that the influence of the capacitances C1b, C1c and C02 disappears, and the measured value C becomes C = C01 + C2. Therefore, when the floating capacitance C01 is measured without the circuit board 24 to be inspected and is subtracted from the measured value C, C-C01 = C2.
Thus, the capacitance Ca of the pattern 28a can be measured.

【0016】又、パターン28bの静電容量Cbを測定
する場合には、図8に示すように共通電極10に高位電
圧Hを加え、パターン28bに低位電圧Lを加え、更に
測定しない各パターン28a、cに共通電極10と同一
の高位電圧Hをそれぞれ加える。すると、パターン28
cには電流が流れないため、静電容量C1cの影響がなく
なって測定値CはC=C01+C02+C1bとなる。但し、
C≪C2 である。そこで、被検査回路基板24のない状
態でC01、C02を測定してCより差し引くとC−C01−
C02=C1bとなり、パターン28bの静電容量Cbを測
定できる。又、パターン28cの静電容量Ccについて
も同様にして静電容量Cc をCc =C1cと測定できる。
又、残りの各パターン28d、e、fについても3本の
プローブ16を同時に上げ下げする等して移動し、同様
にして静電容量Cd、Ce、Cfをそれぞれ測定でき
る。なお、測定の対象としたパターン28に高位電圧を
加え、プローブ60が接触した測定しない各パターン2
8と共通電極10に低位電圧を加えてもよい。
When measuring the capacitance Cb of the pattern 28b, a high voltage H is applied to the common electrode 10 and a low voltage L is applied to the pattern 28b as shown in FIG. , C, the same high voltage H as that of the common electrode 10 is applied. Then, the pattern 28
Since no current flows through c, the influence of the capacitance C1c disappears, and the measured value C becomes C = C01 + C02 + C1b. However,
C≪C2. Therefore, when C01 and C02 are measured without the circuit board 24 to be inspected and subtracted from C, C-C01-
C02 = C1b, and the capacitance Cb of the pattern 28b can be measured. Similarly, the capacitance Cc of the pattern 28c can be measured as Cc = C1c.
The remaining probes 28d, e, and f can also be moved by raising and lowering the three probes 16 at the same time, and the capacitances Cd, Ce, and Cf can be measured in the same manner. A high voltage is applied to the pattern 28 to be measured, and each of the unmeasured patterns 2
A lower voltage may be applied to the common electrode 8 and the common electrode 10.

【0017】[0017]

【発明の効果】以上説明した本発明によれば、請求項1
記載の発明では被検査回路基板の表面に設けたパターン
と裏面に設けたベタパターンとが導通状態になっている
場合にも、その回路基板と共通電極との間に絶縁層を介
在することにより、その表面パターンの静電容量を測定
することができる。
According to the present invention described above, claim 1
In the described invention, even when the pattern provided on the front surface of the circuit board to be inspected and the solid pattern provided on the back surface are in a conductive state, an insulating layer is interposed between the circuit board and the common electrode. The capacitance of the surface pattern can be measured.

【0018】又、請求項2記載の発明では被検査回路基
板と共通電極間に絶縁層を介在し、複数本の各プローブ
を同時に全表面パターンから選んだ対応する各表面パタ
ーンにそれぞれ接触して、プローブが接触した測定しな
い各表面パターンに共通電極と同一の高位又は低位の電
圧を印加するため、プローブが接触した測定しない各パ
ターンの影響をなくし、表面パターンと裏面のベタパタ
ーンとが導通状態になっている場合にも、その表面パタ
ーンの静電容量を測定することができる。そして、検査
スピードを高速化できる。
In the invention according to claim 2, an insulating layer is interposed between the circuit board to be inspected and the common electrode, and a plurality of probes are simultaneously brought into contact with corresponding surface patterns selected from all the surface patterns, respectively. The same high or low voltage as the common electrode is applied to each non-measurement surface pattern contacted by the probe, eliminating the influence of each non-measurement pattern contacted by the probe. Also, the capacitance of the surface pattern can be measured. And the inspection speed can be increased.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明を適用した1プローブ移動型のX−Y方
式インサーキットテスタによる被検査回路基板のパター
ン静電容量測定時の回路図である。
FIG. 1 is a circuit diagram when a pattern capacitance of a circuit board to be inspected is measured by an XY type in-circuit tester of a one-probe moving type to which the present invention is applied.

【図2】同1プローブ移動型のX−Y方式インサーキッ
トテスタによる裏面のベタパターンと導通する表面パタ
ーンの静電容量測定等価回路を示す図である。
FIG. 2 is a diagram showing an equivalent circuit for measuring a capacitance of a front surface pattern that is conductive to a solid back surface pattern by the XY type in-circuit tester of the same probe moving type.

【図3】同1プローブ移動型のX−Y方式インサーキッ
トテスタによる裏面のベタパターンと導通しない表面パ
ターンの静電容量測定等価回路を示す図である。
FIG. 3 is a diagram showing a capacitance measurement equivalent circuit of a front surface pattern that does not conduct with a solid back surface pattern by the XY type in-circuit tester of the same probe moving type.

【図4】本発明を適用した3プローブ同時移動型のX−
Y方式インサーキットテスタによる被検査回路基板のパ
ターン静電容量測定時の回路図である。
FIG. 4 shows a three-probe simultaneous movement type X- to which the present invention is applied.
FIG. 4 is a circuit diagram when a pattern capacitance of a circuit board to be inspected is measured by a Y-system in-circuit tester.

【図5】同3プローブ同時移動型のX−Y方式インサー
キットテスタによるプローブが接触した測定しない各表
面パターンの浮遊静電容量結合を示す裏面のベタパター
ンと導通しない表面パターンの静電容量測定等価回路図
である。
FIG. 5 shows the measurement of the capacitance of a surface pattern that does not conduct with the solid pattern on the back surface showing the stray capacitance coupling of each surface pattern that is not measured by the probe and that is not measured by the XY type in-circuit tester of the three-probe simultaneous movement type. It is an equivalent circuit diagram.

【図6】同3プローブ同時移動型のX−Y方式インサー
キットテスタによるプローブが接触した測定しない各表
面パターンのガード効果を示す裏面のベタパターンと導
通しない表面パターンの静電容量測定等価回路図であ
る。
FIG. 6 is an equivalent circuit diagram of capacitance measurement of a surface pattern that does not conduct with a solid pattern on the back surface showing a guard effect of each surface pattern that is not measured by a probe and that is in contact with the XY type in-circuit tester of the three-probe simultaneous movement type. It is.

【図7】同3プローブ同時移動型のX−Y方式インサー
キットテスタによるプローブが接触した測定しない各表
面パターンの影響をなくした裏面のベタパターンと導通
する表面パターンの静電容量測定等価回路を示す図であ
る。
FIG. 7 is a diagram showing an equivalent circuit for measuring capacitance of a surface pattern which is conducted to a solid pattern on the back surface of the XY type in-circuit tester of the three-probe simultaneous movement type, which eliminates the influence of each surface pattern which is not measured and which is in contact with the probe. FIG.

【図8】同3プローブ同時移動型のX−Y方式インサー
キットテスタによるプローブが接触した測定しない各表
面パターンの影響をなくした裏面のベタパターンと導通
しない表面パターンの静電容量測定等価回路を示す図で
ある。
FIG. 8 shows an equivalent circuit for capacitance measurement of a surface pattern that does not conduct with a solid pattern on the back side by eliminating the influence of each surface pattern that is not measured by the probe and the XY type in-circuit tester of the three-probe simultaneous movement type. FIG.

【図9】従来の1プローブ移動型のX−Y方式インサー
キットテスタによる被検査回路基板のパターン静電容量
測定時の回路図である。
FIG. 9 is a circuit diagram when a pattern capacitance of a circuit board to be inspected is measured by a conventional one probe moving type XY in-circuit tester.

【図10】同1プローブ移動型のX−Y方式インサーキ
ットテスタによる裏面のベタパターンと導通する表面パ
ターンの静電容量測定不能状態を示す回路図である。
FIG. 10 is a circuit diagram showing a state in which the capacitance of a front surface pattern that is electrically connected to a solid back surface pattern cannot be measured by the XY type in-circuit tester of the same probe moving type.

【符号の説明】[Explanation of symbols]

10…共通電極 16…プローブ 18…計測部 20
…交流電圧源 22…交流電流計 24…被検査回路基
板 26…ベタパターン 28…表面パターン30…絶
縁シート
10 Common electrode 16 Probe 18 Measurement unit 20
... AC voltage source 22 ... AC ammeter 24 ... circuit board to be inspected 26 ... solid pattern 28 ... surface pattern 30 ... insulating sheet

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 表面に複数のパターンを設けた被検査回
路基板の裏面側に、それ等の全ての表面パターンに共通
な電極を配置し、その測定の対象とした表面パターンに
プローブを接触して高位又は低位の電圧を加え、共通電
極に低位又は高位の電圧を加えて、その表面パターンに
流れる電流を測定し、その表面パターンと共通電極間の
静電容量を算出する回路基板のパターン静電容量測定方
法において、上記回路基板と共通電極間に絶縁層を介在
することを特徴とする回路基板のパターン静電容量測定
方法。
An electrode common to all the surface patterns is arranged on the back side of a circuit board to be inspected having a plurality of patterns on the surface, and a probe is brought into contact with the surface pattern to be measured. A high or low voltage is applied to the common electrode, a low or high voltage is applied to the common electrode, a current flowing through the surface pattern is measured, and a capacitance between the surface pattern and the common electrode is calculated. In the capacitance measuring method, an insulating layer is interposed between the circuit board and the common electrode, wherein the pattern capacitance of the circuit board is measured.
【請求項2】 表面に複数のパターンを設けた被検査回
路基板の裏面側に、それ等の全ての表面パターンに共通
な電極を配置し、複数本の各プローブを同時に全表面パ
ターンから選んだ対応する各表面パターンにそれぞれ接
触して、その共通電極に高位又は低位の電圧を加え、測
定の対象とした表面パターンに低位又は高位の電圧を加
えて、その表面パターンに流れる電流を測定し、その表
面パターンと共通電極間の静電容量を算出する回路基板
のパターン静電容量測定方法において、上記回路基板と
共通電極間に絶縁層を介在し、プローブが接触した測定
しない各表面パターンに共通電極と同一電位電圧を印加
することを特徴とする回路基板のパターン静電容量測定
方法。
2. An electrode common to all the surface patterns is arranged on the back surface side of a circuit board to be inspected having a plurality of patterns on the surface, and a plurality of probes are simultaneously selected from all the surface patterns. Contact each corresponding surface pattern, apply a high or low voltage to the common electrode, apply a low or high voltage to the surface pattern to be measured, measure the current flowing in the surface pattern, In the method for measuring the capacitance of a circuit board, which calculates the capacitance between the surface pattern and the common electrode, an insulating layer is interposed between the circuit board and the common electrode, and is common to each unmeasured surface pattern contacted by a probe. A method for measuring the capacitance of a pattern on a circuit board, comprising applying the same potential voltage as an electrode.
JP31709096A 1996-11-12 1996-11-12 Circuit board pattern capacitance measurement method Expired - Fee Related JP3599929B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31709096A JP3599929B2 (en) 1996-11-12 1996-11-12 Circuit board pattern capacitance measurement method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31709096A JP3599929B2 (en) 1996-11-12 1996-11-12 Circuit board pattern capacitance measurement method

Publications (2)

Publication Number Publication Date
JPH10142271A true JPH10142271A (en) 1998-05-29
JP3599929B2 JP3599929B2 (en) 2004-12-08

Family

ID=18084329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31709096A Expired - Fee Related JP3599929B2 (en) 1996-11-12 1996-11-12 Circuit board pattern capacitance measurement method

Country Status (1)

Country Link
JP (1) JP3599929B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003207535A (en) * 2002-01-17 2003-07-25 Nec Corp Printed circuit board inspection method and printed circuit board inspection device
JP2010156650A (en) * 2009-01-05 2010-07-15 Hioki Ee Corp Board inspecting apparatus and board inspecting method
JP2010216827A (en) * 2009-03-13 2010-09-30 Hioki Ee Corp Method for performing pass/fail determination of circuit board
JP2011106972A (en) * 2009-11-18 2011-06-02 Hioki Ee Corp Device and method for inspecting circuit board
KR101182649B1 (en) 2010-12-30 2012-09-14 주식회사 유라코퍼레이션 A Movement Device for Examination Of Circuit
JP2014528232A (en) * 2011-09-13 2014-10-23 ルノー エス.ア.エス. Battery charger capacitive filter monitoring method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003207535A (en) * 2002-01-17 2003-07-25 Nec Corp Printed circuit board inspection method and printed circuit board inspection device
JP2010156650A (en) * 2009-01-05 2010-07-15 Hioki Ee Corp Board inspecting apparatus and board inspecting method
JP2010216827A (en) * 2009-03-13 2010-09-30 Hioki Ee Corp Method for performing pass/fail determination of circuit board
JP2011106972A (en) * 2009-11-18 2011-06-02 Hioki Ee Corp Device and method for inspecting circuit board
KR101182649B1 (en) 2010-12-30 2012-09-14 주식회사 유라코퍼레이션 A Movement Device for Examination Of Circuit
JP2014528232A (en) * 2011-09-13 2014-10-23 ルノー エス.ア.エス. Battery charger capacitive filter monitoring method

Also Published As

Publication number Publication date
JP3599929B2 (en) 2004-12-08

Similar Documents

Publication Publication Date Title
JP2994259B2 (en) Substrate inspection method and substrate inspection device
US5517110A (en) Contactless test method and system for testing printed circuit boards
JP3228982B2 (en) In-circuit test equipment
JP3285215B2 (en) Conductor device inspection method and device
JP2625623B2 (en) Circuit test apparatus and method
CN101799507B (en) Printed circuit board testing device and testing method
JPH09152457A (en) Electric wiring inspection method and apparatus
JPH06160457A (en) Testing apparatus of circuit board
US6452410B1 (en) Apparatus and method for electrolytic bare board testing
JP3599929B2 (en) Circuit board pattern capacitance measurement method
JP5420277B2 (en) Circuit board inspection apparatus and circuit board inspection method
JP4277398B2 (en) Wiring board inspection equipment
JPH04503105A (en) Electrical circuit testing
TW200537112A (en) Circuit pattern testing apparatus and circuit pattern testing method
KR20070083501A (en) Inspecting apparatus, inspecting method and sensor for inspecting apparatus
JP2005315775A (en) Four-terminal inspection method and four-terminal inspection jig using single-sided transfer probe
JP2000171500A (en) Resistance-measuring device of printed wiring board and resistance measurement method using it
JP2000232141A (en) Method for testing conduction of substrate for semiconductor package
JP3788129B2 (en) Wiring board inspection apparatus and inspection method
JP2006200973A (en) Circuit board inspection method and its device
JP4467027B2 (en) Electrical circuit disconnection inspection method
JP3281164B2 (en) Foot Lift Detection Method Using IC In-Circuit Tester
JP2002131365A (en) Method and device for inspection
US8704545B2 (en) Determination of properties of an electrical device
JP4369002B2 (en) Circuit board inspection equipment

Legal Events

Date Code Title Description
TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20040914

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20040915

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20070924

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090924

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110924

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130924

Year of fee payment: 9

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees