JPH10135648A - Multilayer printed wiring board - Google Patents
Multilayer printed wiring boardInfo
- Publication number
- JPH10135648A JPH10135648A JP28662096A JP28662096A JPH10135648A JP H10135648 A JPH10135648 A JP H10135648A JP 28662096 A JP28662096 A JP 28662096A JP 28662096 A JP28662096 A JP 28662096A JP H10135648 A JPH10135648 A JP H10135648A
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- multilayer printed
- conductor
- conductor foil
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、多層プリント配線
板の構造に係り、特に、情報通信システムに用いるブッ
クシェルフ実装用多層プリント配線板の構造に関するも
のである。The present invention relates to a structure of a multilayer printed wiring board, and more particularly to a structure of a multilayer printed wiring board for bookshelf mounting used in an information communication system.
【0002】[0002]
【従来の技術】一般的に、従来この種の多層プリント配
線板は、配線可能領域を外形寸より、ガイドレール+導
体箔間隙分内側(約5mm)として、設計および製造さ
れていた。2. Description of the Related Art In general, a multilayer printed wiring board of this type has conventionally been designed and manufactured so that the area where the wiring is possible is set to the inside (about 5 mm) of the gap between the guide rail and the conductor foil from the external dimensions.
【0003】[0003]
【発明が解決しようとする課題】しかしながら、上記し
た従来の多層プリント配線板の場合、プリント配線板の
サイズが大きくなると、組み立て時のリフローソルダリ
ング工程において、プリント板が部品及び自重で大きく
反り、元に戻らない状態となる。また、フローソルダリ
ング工程では、はんだ付け面のみが240℃前後のはん
だ温度に数秒曝されることによる熱膨張及び冷却工程に
おける収縮が生じる。プリント配線板の導体密度分布及
び部品実装分布が異なることにより、温度分布により熱
膨張後の収縮度合いが異なり、反り、ねじれが発生し、
実用上以下に述べる問題があった。However, in the case of the above-mentioned conventional multilayer printed wiring board, when the size of the printed wiring board is increased, the printed board is largely warped by parts and its own weight in a reflow soldering process at the time of assembly. It will not return to its original state. In the flow soldering step, thermal expansion and contraction in the cooling step occur when only the soldering surface is exposed to a solder temperature of about 240 ° C. for several seconds. Due to the difference in the conductor density distribution and the component mounting distribution of the printed wiring board, the degree of shrinkage after thermal expansion differs due to the temperature distribution, causing warpage and twisting.
There are practically the following problems.
【0004】(1)両面実装のプリント配線板におい
て、片面実装後反転し、反対面への部品実装を行う際
に、部品の自動搭載機の高さ方向の制御位置が異なるた
め、部品の搭載位置が大きくずれる等の問題が発生す
る。 (2)ブックシェルフ実装時、プリント配線板がガイド
レールから外れる。最悪の場合、隣接プリント配線板間
で短絡事故が引き起こされる。(1) On a double-sided printed wiring board, when mounting is performed on one side after reversing and mounting on the other side, the control position of the automatic mounting machine in the height direction is different. Problems such as a large displacement occur. (2) When the bookshelf is mounted, the printed wiring board comes off the guide rail. In the worst case, a short circuit accident occurs between adjacent printed wiring boards.
【0005】(3)ブックシェルフ実装時、プリント配
線板の挿入・抜去時に隣接プリント配線板の部品にぶつ
かり、面部品の欠落等、部品へダメージを与える。 本発明は、上記問題点を除去し、厚みを均一化し、組み
立て時の熱による反り、ねじれを防止することができる
多層プリント配線板を提供することを目的とする。(3) At the time of bookshelf mounting, when the printed wiring board is inserted or removed, the printed wiring board collides with a component of an adjacent printed wiring board, and a component such as a missing surface component is damaged. SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer printed wiring board which can eliminate the above problems, make the thickness uniform, and prevent warpage and twisting due to heat during assembly.
【0006】[0006]
【課題を解決するための手段】本発明は、上記目的を達
成するために、 (1)多層プリント配線板において、配線領域と製品外
形の間に、任意の幅、任意の長さ、任意の間隙を有する
導体箔を偶数層、奇数層で導体箔のない部分がジグザグ
になるように配置し、且つ、前記導体箔をスルーホール
で接続するようにしたものである。According to the present invention, there is provided a multi-layer printed wiring board having an arbitrary width, an arbitrary length, an arbitrary length between a wiring region and a product outer shape. The conductor foils having gaps are arranged so that the even-numbered layers and the odd-numbered layers have no zigzag portions without the conductor foils, and the conductor foils are connected by through holes.
【0007】したがって、多層プリント配線板の周囲に
導体箔を配置することにより、導体箔のない部分の樹脂
量が、導体箔の厚さ分多くなり、その部分の寸法変化量
が大きくなることを避けることが可能となり、組み立て
時の熱による反り、ねじれをスルーホール部のめっきを
ザグルことにより矯正することができる。 (2)配線領域と製品外形の間の配線不可領域に、任意
の幅、長さ、間隙を有する導体箔を設け、導体箔のない
部分が、偶数層と奇数層でジグザグになるように配置す
るようにしたものである。Therefore, by arranging the conductor foil around the multilayer printed wiring board, the amount of resin in the portion without the conductor foil increases by the thickness of the conductor foil, and the dimensional change in that portion increases. It is possible to avoid warpage and torsion caused by heat at the time of assembling. (2) A conductive foil having an arbitrary width, length, and gap is provided in a non-wiring area between the wiring area and the outer shape of the product, and a portion without the conductive foil is arranged in a zigzag manner between an even layer and an odd layer. It is something to do.
【0008】したがって、多層プリント配線板の周囲に
導体箔を配置することにより、導体箔のない部分の樹脂
量が、導体箔の厚さ分多くなり、その部分の寸法変化量
が大きくなることを避けることが可能となり、回路形成
時のエッチング液の流出制御並びに多層積層時の溶融接
着剤の流出制御を円滑に行うことができる。Therefore, by arranging the conductor foil around the multilayer printed wiring board, the amount of resin in the portion without the conductor foil increases by the thickness of the conductor foil, and the dimensional change in that portion increases. This makes it possible to smoothly control the outflow of the etchant during circuit formation and the outflow of the molten adhesive during multilayer lamination.
【0009】[0009]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照しながら詳細に説明する。図1は本発明の
第1実施例を示す多層プリント配線板の概略断面図、図
2はその多層プリント配線板の奇数層の概略の平面図、
図3はその多層プリント配線板の偶数層の概略の平面図
である。Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic sectional view of a multilayer printed wiring board showing a first embodiment of the present invention, FIG. 2 is a schematic plan view of an odd layer of the multilayer printed wiring board,
FIG. 3 is a schematic plan view of an even layer of the multilayer printed wiring board.
【0010】これらの図に示すように、この多層プリン
ト配線板の各層は、配線領域101、配線不可領域10
2に分割される。この実施例では、配線不可領域102
に、反り制御用の導体箔(銅箔)103を配線領域10
1の導体と有る間隙を設け、且つ、製品外形より0.3
mm以上確保した領域に、任意の幅、任意の長さを有す
る導体箔103を奇数層、偶数層ごとにその導体箔のな
い部分がジグザグになるように構成し、且つ、その導体
箔103間が接続されるようにスルーホール104を形
成した。[0010] As shown in these figures, each layer of the multilayer printed wiring board includes a wiring area 101 and a non-wiring area 10.
Divided into two. In this embodiment, the non-wiring area 102
Then, a conductor foil (copper foil) 103 for controlling warpage is connected to the wiring region 10.
Provide a certain gap with one conductor and 0.3
mm or more, a conductor foil 103 having an arbitrary width and an arbitrary length is formed in an odd-numbered layer and an even-numbered layer so that a portion without the conductor foil becomes zigzag. Are formed so as to be connected.
【0011】ここで、導体箔103を製品外形より0.
3mm以上確保した位置に配置したのは、多層板とした
場合、層間の位置ずれが発生し、外形加工時にルータビ
ットが導体箔103に当たって、折損することを避ける
ためである。さらに、任意の長さを有する導体箔103
としたのは、多層積層時の接着剤(プリプレグ)が溶融
した場合に発生する気泡を、樹脂の流出と一緒に製品外
へ逃がすためである。Here, the conductor foil 103 is placed at a distance of 0.1 mm from the outer shape of the product.
The reason why they are arranged at a position where 3 mm or more is secured is to prevent a router bit from hitting the conductive foil 103 during external processing and being broken when a multilayer board is used. Further, the conductor foil 103 having an arbitrary length
The reason for this is to allow bubbles generated when the adhesive (prepreg) is melted during multilayer lamination to escape to the outside of the product together with the outflow of the resin.
【0012】また、偶数層と奇数層で導体箔103の位
置がジグザグになるように配置したのは、同一箇所で行
った場合、導体箔のない部分の樹脂量が、導体の厚さ分
多くなり、その部分の寸法変化量が大きくなることを避
けるためである。さらに、スルーホール104を設ける
ようにしたのは、その部分相互の膨張・圧縮を抑えるた
めである。また、その穴を、中途まで、あるいは貫通
し、スルーホールめっき部をザグルことにより、膨張・
収縮を解放してやり、反り、ねじれを矯正するためであ
る。Also, the reason why the conductor foil 103 is arranged in a zigzag position in the even-numbered layer and the odd-numbered layer is that the resin amount in the portion without the conductor foil increases by the thickness of the conductor when the same location is used. This is to avoid an increase in the dimensional change of that portion. Furthermore, the reason why the through holes 104 are provided is to suppress expansion and compression between the portions. In addition, the hole is extended halfway or through, and the through-hole plated part is swollen and expanded.
This is to release the contraction and correct the warpage and twist.
【0013】このように、第1実施例によれば、多層プ
リント配線板において、製品の配線領域外、且つ、製品
外形から0.3mm内側に、任意の幅、任意の長さを有
する導体箔103を偶数層、奇数層で、導体箔のない部
分がジグザグになるように設け、且つ、その導体箔10
3間を接続するスルーホールを設け、組み立ての熱によ
る反り、ねじれが発生する場合、反り、ねじれの大きい
部分のスルーホール104を板厚さの1/2、または、
全部を貫通することにより、基材の熱膨張差によって生
じた歪みを解放してやることにより、反り、ねじれを矯
正することが可能となり、大型基板の反り、ねじれを大
幅に制御することができる。As described above, according to the first embodiment, in the multilayer printed wiring board, the conductor foil having an arbitrary width and an arbitrary length outside the wiring area of the product and inside 0.3 mm from the outer shape of the product. 103 is an even-numbered layer, an odd-numbered layer, and a portion having no conductive foil is provided in a zigzag manner.
In the case where warping or torsion occurs due to the heat of assembly, a through hole 104 having a large warp or torsion is formed to a half of the plate thickness, or
By penetrating the entire substrate, the strain caused by the difference in thermal expansion of the base material is released, so that the warpage and the twist can be corrected, and the warpage and the twist of the large-sized substrate can be largely controlled.
【0014】また、各信号層の配線密度が異なることに
よる、接着基材(プリプレグ)を使用した層間の厚さば
らつきが小さくなるように抑えられ、特性インピーダン
ス制御を必要とする多層プリント配線板にも使用するこ
とができる。次に、本発明の第2実施例について説明す
る。図4は本発明の第2実施例を示す多層プリント配線
板の奇数層の概略の平面図、図5はその多層プリント配
線板の偶数層の概略の平面図である。なお、断面図は図
1と同様であるので、ここでは省略する。[0014] Further, thickness variations between layers using an adhesive base material (prepreg) due to different wiring densities of the respective signal layers are suppressed so as to be small, so that a multilayer printed wiring board requiring characteristic impedance control is required. Can also be used. Next, a second embodiment of the present invention will be described. FIG. 4 is a schematic plan view of an odd-numbered layer of a multilayer printed wiring board showing a second embodiment of the present invention, and FIG. 5 is a schematic plan view of an even-numbered layer of the multilayer printed wiring board. The cross-sectional view is the same as that of FIG.
【0015】これらの図に示すように、多層プリント配
線板の各層では、配線領域201、配線不可領域202
に分割される。この実施例では、配線不可領域202
に、エッチング液流出制御及び、多層積層時の溶融接着
剤の流出制御用の導体箔203を配線領域201の導体
と任意の間隙を設け、且つ、製品外形より0.3mm以
上確保した領域に、任意の幅、長さ、間隙を有する導体
箔を奇数層、偶数層ごとに導体箔の内部分がジグザグに
なるように構成した。As shown in these figures, in each layer of the multilayer printed wiring board, a wiring area 201 and a non-wiring area 202
Is divided into In this embodiment, the non-wiring area 202
The conductor foil 203 for controlling the outflow of the etchant and controlling the outflow of the molten adhesive at the time of multilayer lamination is provided with an arbitrary gap from the conductor in the wiring area 201, and in an area where the outer diameter is secured by 0.3 mm or more from the outer shape of the product. The conductor foil having an arbitrary width, length, and gap was configured so that the inner portion of the conductor foil became zigzag for each of the odd-numbered and even-numbered layers.
【0016】ここで、導体箔を製品外形より0.3mm
以上確保した位置に配置したのは、多層板とした場合、
層間の位置ずれが発生し、外形加工時にルータビットが
導体箔に当たって、折損することを避けるためである。
さらに、任意の長さ、間隙を有する導体箔としたのは、
パターンをエッチング液にて形成するとき、エッチング
液の流出速度をプリント配線板の中央部と端部を同等と
するため。また、多層積層時の接着剤(プリプレグ)が
溶融した場合に発生する気泡を樹脂の流出と一緒に製品
外へ逃がすこと及びプリント配線板の中央部と端部の仕
上がり板厚さを均一にするためである。Here, the conductor foil is 0.3 mm from the outer shape of the product.
Placed in the position secured above is a multilayer board,
This is to prevent the router bit from hitting the conductor foil during the outer shape processing and causing breakage due to misalignment between layers.
Furthermore, the conductor foil having an arbitrary length and gap is
When the pattern is formed with an etching solution, the outflow speed of the etching solution is made equal between the central portion and the end portion of the printed wiring board. In addition, air bubbles generated when the adhesive (prepreg) at the time of multilayer lamination is melted are allowed to escape to the outside of the product together with the outflow of the resin, and the finished board thickness at the center and the end of the printed wiring board is made uniform. That's why.
【0017】また、導体箔を偶数層と奇数層間ジグザグ
になるようにしたのは、同一箇所で行った場合、銅箔の
ない部分の樹脂量が、銅箔の厚さ分だけ、厚くなり、そ
の部分の寸法変化量が大きくなることを避けるためであ
る。このように、第2実施例によれば、多層プリント配
線板において、製品の配線領域外、且つ、製品外形から
0.3mm内側に、任意の幅、長さ、間隙を有する導体
箔を偶数層、奇数層で、銅箔のない部分がジグザグにな
るように設けたことにより、パターン形成時の中央部と
端部の導体幅が均一となる。また、積層後の層間厚さ
が、中央部と端部で均一となる。Further, the reason why the conductor foil is formed into a zigzag between the even-numbered layer and the odd-numbered layer is that, when performed at the same location, the resin amount in the portion without copper foil becomes thicker by the thickness of the copper foil. This is for avoiding an increase in the dimensional change of that portion. As described above, according to the second embodiment, in the multilayer printed wiring board, the conductor foil having an arbitrary width, length, and gap is formed in an even number of layers outside the wiring region of the product and inside 0.3 mm from the outer shape of the product. By providing the odd-numbered layers so that the portions without the copper foil form a zigzag pattern, the conductor width at the center portion and at the end portion during pattern formation becomes uniform. Further, the interlayer thickness after lamination becomes uniform at the center and the end.
【0018】したがって、特性インピーダンスのばらつ
きを非常に少なくすることができる。また、プリント配
線板に部品を実装する組み立て工程においても、プリン
ト配線板の部品重さ、自重、はんだ付けの熱による反り
を小さく抑えることができる。Therefore, variation in characteristic impedance can be extremely reduced. Also, in the assembly process of mounting components on the printed wiring board, warpage due to component weight, own weight, and heat of soldering of the printed wiring board can be suppressed.
【0019】なお、上記実施例では、ブックシェルフ実
装用多層プリント配線板について説明したが、回路形成
をエッチングにて行い、且つ、積層プレスを用いた多層
プリント配線板、全てに適用できる。例えば、サブトラ
クティブ法を用いた多層プリント配線板等全てに適用で
きる。また、本発明は上記実施例に限定されるものでは
なく、本発明の趣旨に基づいて種々の変形が可能であ
り、これらを本発明の範囲から排除するものではない。In the above embodiment, a multilayer printed wiring board for bookshelf mounting has been described. However, the present invention can be applied to all multilayer printed wiring boards using a lamination press in which a circuit is formed by etching. For example, the present invention can be applied to all types of multilayer printed wiring boards using a subtractive method. Further, the present invention is not limited to the above-described embodiments, and various modifications are possible based on the gist of the present invention, and these are not excluded from the scope of the present invention.
【0020】[0020]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、以下のような効果を奏することができる。 (1)請求項1記載の発明によれば、多層プリント配線
板の周囲に導体箔を配置することにより、導体箔のない
部分の樹脂量が、導体箔の厚さ分多くなり、その部分の
寸法変化量が大きくなることを避けることが可能とな
り、組み立て時の熱による反り、ねじれをスルーホール
部のめっきをザグルことにより矯正することができる。As described above, according to the present invention, the following effects can be obtained. (1) According to the first aspect of the present invention, by arranging the conductor foil around the multilayer printed wiring board, the amount of resin in the portion without the conductor foil is increased by the thickness of the conductor foil, and the amount of resin in that portion is increased. It is possible to avoid an increase in the dimensional change, and it is possible to correct warpage and torsion due to heat during assembly by zagging the plating of the through-hole portion.
【0021】(2)請求項2記載の発明によれば、多層
プリント配線板の周囲に導体箔を配置することにより、
導体箔のない部分の樹脂量が、導体箔の厚さ分多くな
り、その部分の寸法変化量が大きくなることを避けるこ
とが可能となり、回路形成時のエッチング液の流出制御
並びに多層積層時の溶融接着剤の流出制御を円滑に行う
ことができる。(2) According to the second aspect of the invention, by disposing the conductive foil around the multilayer printed wiring board,
The amount of resin in the portion without the conductor foil is increased by the thickness of the conductor foil, making it possible to avoid an increase in dimensional change in that portion. Outflow control of the molten adhesive can be performed smoothly.
【図1】本発明の第1実施例を示す多層プリント配線板
の概略断面図である。FIG. 1 is a schematic sectional view of a multilayer printed wiring board according to a first embodiment of the present invention.
【図2】本発明の第1実施例を示す多層プリント配線板
の奇数層の概略の平面図である。FIG. 2 is a schematic plan view of an odd-numbered layer of the multilayer printed wiring board according to the first embodiment of the present invention.
【図3】本発明の第1実施例を示す多層プリント配線板
の偶数層の概略の平面図である。FIG. 3 is a schematic plan view of an even-numbered layer of the multilayer printed wiring board according to the first embodiment of the present invention.
【図4】本発明の第2実施例を示す多層プリント配線板
の奇数層の概略の平面図である。FIG. 4 is a schematic plan view of an odd-numbered layer of a multilayer printed wiring board according to a second embodiment of the present invention.
【図5】本発明の第2実施例を示す多層プリント配線板
の偶数層の概略の平面図である。FIG. 5 is a schematic plan view of an even-numbered layer of a multilayer printed wiring board according to a second embodiment of the present invention.
101,201 配線領域 102,202 配線不可領域 103,203 導体箔(銅箔) 104 スルーホール 101, 201 Wiring area 102, 202 Non-wiring area 103, 203 Conductor foil (copper foil) 104 Through hole
Claims (2)
任意の長さ、任意の間隙を有する導体箔を偶数層、奇数
層で導体箔のない部分がジグザグになるように配置し、
且つ、前記導体箔をスルーホールで接続することを特徴
とする多層プリント配線板。1. An arbitrary width between a wiring area and a product outer shape.
Arrange the conductor foil with any length and any gap so that even-layer, odd-layer with no conductor foil is zigzag,
A multilayer printed wiring board, wherein the conductor foils are connected by through holes.
に、任意の幅、長さ、間隙を有する導体箔を設け、導体
箔のない部分が、偶数層と奇数層でジグザグになるよう
に配置することを特徴とする多層プリント配線板。2. A conductive foil having an arbitrary width, length, and gap is provided in a non-wiring area between a wiring area and a product outer shape, and a portion without a conductive foil is zigzag between even and odd layers. A multilayer printed wiring board characterized by being arranged on a printed circuit board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28662096A JPH10135648A (en) | 1996-10-29 | 1996-10-29 | Multilayer printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28662096A JPH10135648A (en) | 1996-10-29 | 1996-10-29 | Multilayer printed wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH10135648A true JPH10135648A (en) | 1998-05-22 |
Family
ID=17706772
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28662096A Withdrawn JPH10135648A (en) | 1996-10-29 | 1996-10-29 | Multilayer printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH10135648A (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001053394A (en) * | 1999-08-16 | 2001-02-23 | Ibiden Co Ltd | Wiring board and manufacture thereof |
JP2002076530A (en) * | 2000-09-05 | 2002-03-15 | Matsushita Electric Ind Co Ltd | Printed circuit board and method of manufacturing printed circuit board |
JP2005167141A (en) * | 2003-12-05 | 2005-06-23 | Ibiden Co Ltd | Method of manufacturing printed wiring board and multilayer printed wiring board |
JP2009212417A (en) * | 2008-03-06 | 2009-09-17 | Denso Corp | Method of manufacturing multilayer wiring board |
EP2066160A3 (en) * | 2007-11-29 | 2009-11-25 | Shinko Electric Industries Co., Ltd. | Wiring board and electronic component device |
US8024857B2 (en) | 2008-11-07 | 2011-09-27 | Hynix Semiconductor Inc. | Substrate for semiconductor package having a reinforcing member that prevents distortions and method for fabricating the same |
JP2012038911A (en) * | 2010-08-06 | 2012-02-23 | Jtekt Corp | Multilayer circuit board |
JP2013089847A (en) * | 2011-10-20 | 2013-05-13 | Hitachi Automotive Systems Ltd | Printed circuit board and electronic apparatus using the same |
KR101431911B1 (en) * | 2012-12-06 | 2014-08-26 | 삼성전기주식회사 | Printed circuit board and manufacturing method thereof |
-
1996
- 1996-10-29 JP JP28662096A patent/JPH10135648A/en not_active Withdrawn
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001053394A (en) * | 1999-08-16 | 2001-02-23 | Ibiden Co Ltd | Wiring board and manufacture thereof |
JP2002076530A (en) * | 2000-09-05 | 2002-03-15 | Matsushita Electric Ind Co Ltd | Printed circuit board and method of manufacturing printed circuit board |
JP2005167141A (en) * | 2003-12-05 | 2005-06-23 | Ibiden Co Ltd | Method of manufacturing printed wiring board and multilayer printed wiring board |
EP2066160A3 (en) * | 2007-11-29 | 2009-11-25 | Shinko Electric Industries Co., Ltd. | Wiring board and electronic component device |
JP2009212417A (en) * | 2008-03-06 | 2009-09-17 | Denso Corp | Method of manufacturing multilayer wiring board |
US8024857B2 (en) | 2008-11-07 | 2011-09-27 | Hynix Semiconductor Inc. | Substrate for semiconductor package having a reinforcing member that prevents distortions and method for fabricating the same |
JP2012038911A (en) * | 2010-08-06 | 2012-02-23 | Jtekt Corp | Multilayer circuit board |
JP2013089847A (en) * | 2011-10-20 | 2013-05-13 | Hitachi Automotive Systems Ltd | Printed circuit board and electronic apparatus using the same |
KR101431911B1 (en) * | 2012-12-06 | 2014-08-26 | 삼성전기주식회사 | Printed circuit board and manufacturing method thereof |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20040106 |