JPH10124010A - Liquid crystal panel and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce degradation in picture quality by reducing a frequency of a reference voltage applied to a common electrode and preventing concentration of a current to the common electrode without increasing flicker. SOLUTION: In a liquid crystal panel 101 in which pixel sections 104 having thin film transistors is formed, opposing electrodes 112 opposing to pixel electrodes 106 of liquid crystal 107 constituting the pixel sections and additional capacitors 108 are made common for each pixel section, connection between gate lines 102 and pixel sections 104 or connection between corresponding electrodes 112 of each pixel section and opposing electrode lines 109, 110 are performed so that a current is not concentrated to one side only. Also, a period of AC voltage applied to the opposing electrode lines 109, 110 can be reduced to a frame period to prevent occurrence of flicker by performing its connection so that voltage of positive polarity and voltage of negative polarity are applied uniformly to a whole screen.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device having an active matrix driving type liquid crystal panel, and more particularly to a structure and a driving method of the liquid crystal panel.

[0002]

2. Description of the Related Art In a liquid crystal panel of a liquid crystal display device, a TFT (Thin Film Transistor) is provided on a transparent substrate in which liquid crystal is sealed.
r) There is an active matrix driving type liquid crystal panel (TFT liquid crystal panel) in which pixel portions formed by pixel electrodes and the like are arranged in a matrix. JP-A-63-2370
No. 95 discloses that a gradation voltage corresponding to display data is TF
A liquid crystal display device that performs color display by applying a voltage to a T liquid crystal panel is shown.

A conventional liquid crystal display device using a TFT liquid crystal panel will be described below.

FIG. 15 shows an equivalent circuit diagram of a TFT liquid crystal panel. In FIG. 15, a TFT liquid crystal panel 201 is
Four gate lines 20 each drawn in the horizontal and vertical directions
2. a drain line 203, a pixel unit 204 connected to each one of the drain lines 203 and the gate line 202 arranged in a matrix and corresponding to an arrangement position, and all the pixel units 2
04 has a common electrode (Com) 209 and a common electrode (Strg) 210 provided in common. Each pixel section 204
Represents a thin film transistor (TFT) 205 and a pixel electrode 20
6, a liquid crystal 208, and an additional capacitor 207. Here, the liquid crystal 208 includes a pixel electrode 206 and a common electrode (Co
m) and the additional capacitor 207 is sandwiched between the pixel electrode 20
6 and a common electrode (Strg) 210. In addition, each pixel unit 204 in the same row is driven by the same voltage of one gate line 202, and each pixel unit 2 in the same column is driven.
04 is also driven by the same voltage of one drain line 203.

FIG. 16 shows an overall configuration diagram of a liquid crystal display device. In FIG. 16, in the liquid crystal display device, a pixel portion is formed by m rows and n rows.
The above-mentioned liquid crystal panels 201 arranged in columns, a liquid crystal controller 302 for outputting display data and various synchronization signals, a drain driver 306 for applying a data voltage corresponding to the display data to the drain line 203, and a scanning voltage for the gate line 202 A gate driver 307 for applying the
4 includes AC voltage generating circuits 309, 310, and 313 for converting the voltage applied to AC into AC, and a dividing resistor 311.

The liquid crystal controller 302 sequentially latches display data in accordance with the data synchronization signal 402 and transfers it to the drain driver 306 by the circuit shown in FIG. The circuit shown in FIG. 18 generates an AC signal 304 for designating the polarity of the reference voltage from the vertical synchronizing signal 501 and the horizontal synchronizing signal 502, and generates AC voltage generating circuits 309 and 31.
0,313. The alternating signal 304 changes so that the polarity of the voltage applied to each pixel unit 204 is inverted for each cycle of the horizontal synchronization signal.

In the gate driver 307, in the configuration shown in FIG. 19, the shift register 603 internally shifts the synchronizing signal 601 for enabling the selection of the first line according to the synchronizing signal 602 having the same frequency as the horizontal synchronizing signal. The level shifter 605 and the voltage selection circuit 607 change the gate voltages G (1), G
(2), G (3)... Are generated and applied to the gate line 202. As a result, G (1), G
A selection voltage for turning on the TFT 205 is applied in the order of (2), G (3),.

In the drain driver 306, in the configuration shown in FIG. 20, a latch circuit 707 sequentially takes in display data and stores it for one line in accordance with a sampling clock 706 generated by a shift register 705. The stored display data for one line is simultaneously taken into the latch circuit 709 by the synchronization signal 704 having the same frequency as the horizontal synchronization signal, and is converted into the drain voltage Vd corresponding to the reference voltage 312 by the gradation voltage generation circuit 711. And the drain line 203
Is applied to

Note that each pixel section 204 of the liquid crystal panel 201
If the polarity of the voltage applied to the liquid crystal 208 is the same in one frame period, the screen flickers. In order to reduce this flicker, in the present liquid crystal display device, the polarity of the voltage applied to each pixel unit 204 is inverted every line period by the AC voltage generation circuits 309, 310, 313 and the like.

Next, the operation of the above-described liquid crystal display device will be described with reference to FIG.
1 will be described.

In parallel with the gate driver 307 setting the voltage VG (2) of the gate line 202 of the second horizontal line (second row) to the selection voltage Vgon, the drain driver 306
Applies the grayscale voltage Vd based on the display data of the second row and the AC signal to each drain line 203. As a result, in each pixel unit 204 in the second row, the TFT 205 is turned on, the gradation voltage Vd is applied to the pixel electrode 206, and the reference voltage according to the AC signal is applied to the common electrodes (Com, Strg) 209 and 210. Is applied. The potential difference between the gradation voltage and the reference voltage controls the transmittance of the liquid crystal 208, and the voltage VG (2) becomes the non-selection voltage Vgoff, and the TFT 205
Is held off by the liquid crystal 208 and the additional capacitor 207 even after the switch is turned off.

When the gate driver 305 sets the voltage VG (2) to the non-selection voltage Vgoff and sets the voltage VG (3) of the gate line 202 in the third row to the selection voltage Vgon, the drain driver 306 sets the display data in the third row. And a gradation voltage Vd based on the polarity signal. As a result, the same driving as described above is performed on each pixel unit 204 in the third row.

In the above operation, the common electrodes (Com,
(Strg) When the level of the reference voltage applied to 209 and 210 is the positive level VcomP, the negative gradation voltage Vd is applied to the pixel electrode 206 of the pixel unit 204 in the driving target row. The potential difference at the additional capacitance 207 has a negative polarity with respect to the reference voltage. Conversely, when the common electrodes (Com, Strg) 209 and 210 are at the negative polarity level VcomN, the potential difference between the liquid crystal 208 and the additional capacitance 207 becomes positive.

[0014]

In the above prior art,
The additional capacitors 207 of all the pixel units 204 are connected to the common electrode Str.
Connect to g210 in common. The additional capacitance 207 of each pixel unit 204 has a larger capacitance than the liquid crystal 208,
Those corresponding to the same row hold the potential difference of the same polarity.
Therefore, when voltages having different polarities are applied to the additional capacitance 207 during driving of the pixel unit 204, a current flows intensively between the additional capacitance 207 of the pixel unit 204 and the common electrode strg 210 which are driven at the same time. Distortion occurs in the voltage of the common electrode due to the influence of the wiring resistance and the load capacitance. In the related art, there is a problem that the level of the voltage applied to the liquid crystal 208 changes due to the distortion and the image quality deteriorates.

Further, in the above-mentioned conventional technique, in order to prevent the occurrence of flicker, the reference voltage applied to the common electrode is converted into an alternating current and the polarity is inverted every time one row is driven. That is, the voltage applied to the common electrode is 30 kHz to 60 kHz.
It is necessary to change the frequency at a high frequency of about Hz, which causes a problem that power consumption increases.

Accordingly, an object of the present invention is to reduce the frequency of the voltage applied to the common electrode without increasing flicker. It is another object of the present invention to eliminate the concentration of current in the common electrode and reduce the deterioration of image quality.

[0017]

In order to achieve the above-mentioned object, a liquid crystal panel of the present invention is provided with a liquid crystal panel arranged opposite to each other.
A liquid crystal panel having one substrate and a liquid crystal filled between the two substrates, the liquid crystal panel being formed on the substrate.
M × N pixel units corresponding to the pixels in M rows and N columns, a plurality of drain lines, a plurality of gate lines, and two counter electrode lines are provided. A thin film transistor having a gate electrode connected to the gate line, and a drain electrode and a source electrode connected to any one of the drain lines; a pixel electrode connected to a source electrode of the thin film transistor; And an opposite electrode for applying an electric field to the liquid crystal to change the transmittance of the liquid crystal for a corresponding pixel, wherein the opposite electrode is divided into two groups, and the two opposite electrodes are provided for each group. It is characterized in that it is connected to each of the electrode wires. In this liquid crystal panel, reference voltages having different polarities can be applied to two groups of counter electrodes via two counter electrode lines. When a reference voltage having a different polarity is applied, the liquid crystal of each pixel of the liquid crystal panel is divided into a liquid crystal to which a positive reference voltage is applied and a liquid crystal to which a negative reference voltage is applied. Even when the polarity is not changed, the effect of AC conversion is produced, and flicker can be sufficiently suppressed even when the polarity of the reference voltage is changed at a lower frequency than in the related art.

Further, in the liquid crystal panel according to the present invention, in the liquid crystal panel according to the present invention, the counter electrode is paired with the pixel electrode to form a capacitor for maintaining the electric field, and is connected to the one gate line. Among the connected thin film transistors, the number of the thin film transistors connected to the pair of pixel electrodes and the counter electrode connected to the same counter electrode line is approximately N / 2.
It is characterized by being individual. In this liquid crystal panel, for example, when N thin film transistors are driven at the same time, the current flowing from the liquid crystal and the capacitor is substantially equally distributed to the two counter electrode lines, so that the current does not concentrate on one of the counter electrode lines. In addition, the deterioration of image quality due to the current of the counter electrode line is reduced as compared with the related art.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is an equivalent circuit diagram of a liquid crystal panel according to the first embodiment of the present invention. Here, an example in which four pixel units are arranged in each of the horizontal and vertical directions will be described.

The liquid crystal panel 101 shown in FIG. 1 has five gate lines 102 drawn in the horizontal direction, four drain lines 103 drawn in the vertical direction, and one each arranged in four rows and four columns.
The pixel unit 104 connected to the drain line 203 and the gate line 202 and the pixel unit 104 in an odd row (1, 3 rows)
A common electrode (Strg0) 109 provided in common to
A common electrode (Strg1) 110 is provided in common to the pixel units 104 in the even rows (2 and 4 rows). Note that when the pixel portion 104 is arranged in m rows and n columns, the gate line 10
2 and (m + 1) lines and n drain lines 103 may be drawn. In the case of performing color display, R (red), G
(Green) and B (blue) are displayed.

Each pixel section 104 includes a thin film transistor (T
FT) 105, pixel electrodes 106, liquid crystals 107 and 11
1, an additional capacitor 108, a counter electrode 112, and a color filter (not shown) of a color corresponding to the arrangement position. The liquid crystals 107 and 111 and the additional capacitance 107 are sandwiched between the pixel electrode 206 and the counter electrode 112. The odd-numbered counter electrodes 112 are connected to the common electrode (Strg0) 109, and are connected to the even-numbered row common electrodes (Strg1) 110. Note that the liquid crystal 111 is an auxiliary liquid crystal for the liquid crystal 107 and does not necessarily need to be provided. In the first row, the pixel units 104 in odd-numbered columns (first and third columns) apply the voltage G of the gate line 102.
The pixel section 104 of the first row is driven by the voltage G (2), and the pixel sections 104 of the first row, even columns (2, 4 columns) and the second row, odd columns are driven. Then, the pixel unit 104 in the even-numbered column in the fourth row, which is the last row, is driven by the voltage G (5). Each pixel portion 204 in the same column is also driven by the same voltage of one drain line 203. That is, when the pixel units 104 are arranged in m rows and n columns, the pixel units 104 in the (a-1) -th row and the even-numbered columns
Then, the pixel portion 104 in the a-th row and the odd-numbered column is driven by the voltage G (a) (where 1 <a <m). The pixel portion 104 in the b-th column is driven by the voltage D (b).

FIG. 2 is a configuration diagram of the liquid crystal display device according to the first embodiment of the present invention.

In the liquid crystal display device shown in FIG.
The above-mentioned liquid crystal panel 101 arranged in the row n column and the liquid crystal controller 9 for generating and outputting display data and various synchronization signals
02 and a data voltage corresponding to the display data to the drain line 1
03 and the gate line 1
02, a gate driver 908 that applies a scanning voltage to the pixel electrodes 02, AC voltage generation circuits 910 and 911 that apply a reference voltage to the counter electrode 112 of each pixel unit 104 via a common electrode, and a gray scale Divided resistors 912 and 913 for applying a voltage are provided.

FIG. 3 is a block diagram of a circuit unit for generating display data by the liquid crystal controller 302, and FIG. 4 is a block diagram of a circuit unit for generating AC signals 904 and 905 by the liquid crystal controller 302.

As shown in FIG. 3, a circuit for generating display data includes a data delay circuit 1003 and a selection circuit 100.
5. The data delay circuit 1003 is supplied with display data 1001 included in a bus signal 901 supplied from a system (not shown) and a synchronization signal 1002 indicating a transmission timing of the display data. The supplied display data 1001 is delayed by a predetermined period of the synchronization signal 1002 in the data delay circuit 1003, and is output as display data 1004. The selection circuit 1005
According to the method shown in the timing chart of FIG.
001 and new display data 1006 are generated from the delayed display data 1004 and output to the drain driver 907. For example, the display data (R1-0, G1-
0, B1-0), (R1-1, G1-1, B1-1),
..., display data of the second row (R2-0, G2-0, B
2-0), (R2-1, G2-1, B2-1).
0, G1-0, B2-0), (R1-1, G2-1, B
1-1)... At the same time, a synchronization signal enabling display of the display data 1006 is output to the drain driver 907 and the gate driver 908.

As shown in FIG. 4, a circuit section for generating an AC signal includes an FF (flip-flop) circuit 1103,
1105, 1111 and 1112, exclusive OR circuit 11
07, and an inverting circuit 1109. Bus signal 9
01 included in the FF circuit 11
03, the signal is divided by 2 to become a signal 1104, and the FF circuit 11
11 is supplied. The FF circuit 1111 takes in the supplied signal 1104 with a signal 1110 obtained by inverting the horizontal synchronization signal 1102 of the bus signal 901, and outputs it as an AC signal 905 to the AC voltage generation circuits 910 and 911. This alternating signal 905 is a signal whose polarity is inverted every frame period. On the other hand, the horizontal synchronizing signal 1102 included in the bus signal 901 is frequency-divided by 2 in the FF circuit 1105, and then the exclusive OR with the signal 1104 is calculated in the arithmetic circuit 1107. The calculation result is output to the FF circuit 11
At 12, the signal is captured by the signal 1110 and output to the drain driver 907 as an alternating signal 904. This alternating signal 905 is a signal whose polarity is inverted every line period.

FIG. 6 is a block diagram of the gate driver 908.

Referring to FIG. 6, a gate driver 908 comprises:
m + 1 stage shift register 1303, level shifter 13
05, a voltage selection circuit 1307. The synchronization signal 906 supplied from the liquid crystal controller 302 to the gate driver 908 includes a synchronization signal 1301 for enabling the selection of the first line and a synchronization signal 1302 for instructing switching of the selected line. Shift register 13
03 is the output signal 13 when the synchronization signal 1301 is input.
The output signal 1304 to be made high is sequentially shifted in accordance with the synchronization signal 1302 with the first signal of 04 being high.
The level shifter 1305 and the voltage selection circuit 1307 provide a TFT to the gate line 102 corresponding to the high output signal 1304.
A selection voltage for turning on 205 is applied, and another gate line 1 is turned on.
02 is applied with a non-selection voltage for turning off the TFT 205. As a result, the gate line 102 to which the selection voltage is applied
Changes in the order of voltages G (1), G (2),..., G (m + 1).

FIG. 7 is a block diagram of the drain driver 907.

In FIG. 7, the drain driver 907
Is a shift register 1405 for generating display data capture timing, line latch circuits 1407 and 1409 for capturing and holding one line of display data, and a positive polarity grayscale voltage for generating a positive polarity grayscale voltage according to the display data. A generation circuit 1411; a negative gradation voltage generation circuit 1413 that generates a negative gradation voltage according to display data; and a voltage selector 1415 that selects and outputs one of a positive gradation voltage and a negative gradation voltage. And

The shift register 1405 stores the display data 1401 contained in the bus signal 903 in the latch circuit 1407 sequentially for one horizontal line based on the synchronization signals 1402 and 1403 contained in the bus signal 903 supplied from the liquid crystal controller 902. A timing signal 1406 to be taken in is generated and output to the latch circuit 1407. The display data for one horizontal line captured and held by the latch circuit 1407 is the synchronization signal 1 of the bus signal 903.
At 404, they are simultaneously taken into the latch circuit 1409,
Positive polarity gradation voltage generation circuit 1 via data bus 1410
411, supplied to the negative polarity gradation voltage generation circuit 1412. Each of the grayscale voltage generation circuits 1411 and 1412 generates a positive drain voltage Vd + 1412 and a negative drain voltage Vd-1414 according to the supplied display data for one horizontal line, respectively.
Output to The voltage selection circuit 1415 calculates the supplied drain voltage Vd + 1412 and the drain voltage Vd-1414.
Is selected according to the AC conversion signal 904 supplied from the liquid crystal controller 902 and applied to the drain line 103. At this time, the applied drain voltage V is applied between the odd-numbered column drain line 103 and the even-numbered column drain line 103.
The polarity of d is different. Each drain line 103 has 1
A positive drain voltage and a negative drain voltage are alternately applied for each line period.

Next, the operation of the liquid crystal display of this embodiment will be described with reference to FIG.

The liquid crystal controller 902 controls the display data (R2-0, G1-0, B2-
0), (R1-1, G2-1, B1-1)... To the drain driver 907. Gate driver 908
As a result, the voltage G (2) of the gate line 102 becomes the selection voltage Vgon.
Then, the TFT 105 of each pixel portion 104 in the even-numbered column of the first row and the odd-numbered column of the second row is turned on. In parallel with this, the display data (R2-0, G1-0, B2-0, R1-A1) of each pixel in the even-numbered column of the first row and the odd-numbered column of the second row are output from the drain driver 907. 1,
G2-1, B2-1 ...) and the reference voltage 904 are output to the drain line 130. This gradation voltage is applied to the pixel electrode 106 of each pixel unit 104 in the ON state. The common electrode (Strg0, Strg
g1) An AC reference voltage is applied via 109 or 110, and the transmittance of the liquid crystal 107 is controlled by a potential difference between the voltage applied to the liquid crystal 107 and the additional capacitor 108, whereby gradation display is performed. This potential difference is held by the liquid crystal 107 and the additional capacitor 108 even after the voltage G (2) of the gate line 102 becomes the non-selection voltage Vgoff.

After one line period, when the voltage G (2) becomes the non-selection voltage Vgoff and the voltage G (3) becomes the selection voltage Vgon, each pixel in the even-numbered column of the second row and the odd-numbered column of the third row The TFT 105 of the portion 104 is turned on, and in parallel with this, the drain line 130 has a level based on the display data of each pixel in the even-numbered column of the second row and the odd-numbered column of the third row and the AC reference voltage 904. An adjustment voltage is output. Thus, 1
The same operation is repeated every line period, and all the pixel units 104 are driven in one frame period.

For example, in the period in which the voltage G (2) is equal to the selection voltage Vgon, as shown in FIG. 8, the reference voltage Vstrg0 of the common electrode (Strg0) 109 is in the pixel section 104 of the first row and the even-numbered column. A negative potential VstrgN causes a positive potential difference. At this time, the common electrode (Strg1) 110 is provided in the pixel portion 104 in the second row and the odd-numbered column.
Becomes the positive voltage VstrgP, thereby generating a negative potential difference. That is, the polarity of the potential difference generated in each pixel portion 104 is alternately inverted for each row.

As described above, in the liquid crystal display device of the present embodiment, the current generated by the change in the reference voltage in the n pixel units 104 driven at the same time uses the common electrode (Str).
(g0, Strg1) 109 and 110, which are split into two and flow into. Since the current does not intensively flow into one of the common electrodes, the deterioration of the image quality due to the fluctuation of the applied voltage to the common electrode can be reduced as compared with the conventional example.

In the liquid crystal display device of the present embodiment, even when the polarity of the voltage applied to each of the common electrodes (Strg0, Strg1) 109 and 110 is fixed in one frame period, the liquid crystal of each pixel of the liquid crystal panel is Since a positive polarity voltage and a negative polarity voltage are applied equally to each other, an effect of preventing flicker can be obtained. For this reason, the common electrodes (Strg0, Strg1) 109 and 11 are maintained while maintaining the effect of preventing flicker.
The frequency of the reference voltage applied to 0 can be reduced, thereby reducing power consumption.

Next, a second embodiment of the present invention will be described with reference to FIGS.
11 will be described.

FIG. 9 is an equivalent circuit diagram of a liquid crystal panel according to the second embodiment of the present invention.

The liquid crystal panel 1601 shown in FIG. 9 has four gate lines 1602, four drain lines 1603,
A pixel portion 1604 arranged in four rows and four columns and a common electrode (St)
rg0) 1609 and the common electrode (Strg1) 1610
And Each pixel portion 1604 is a liquid crystal panel 1 shown in FIG.
01, TFT 1605, liquid crystal 1607, 161
1, additional capacitance 1608, pixel electrode 1606, counter electrode 1
612. In the liquid crystal panel 1601, each pixel portion 1604 has a gate line 1 corresponding to the arranged row.
602 and a drain line 1603 corresponding to the arranged column
Connected to. That is, the pixel portion 160 on the a-th row and the b-th column
4 is driven by the voltages G (a) and D (b). In the odd-numbered row pixel portion 1604, the odd-numbered column counter electrode 1612 is commonly connected to the common electrode (Strg1) 1610, and the even-numbered column counter electrode 1612 is commonly connected to the common electrode (Strg0) 1609. ing. Conversely, in the pixel portion 1604 in the even-numbered row, the opposing electrode 1612 in the odd-numbered column is a common electrode (Strg0) 1609, and the opposing electrode 1612 in the even-numbered column is a common electrode (Strg1) 161.
0. A plurality of wirings between the counter electrodes 1612 are drawn obliquely in an area forming the pixel portion 1604, and connect the pixel portions 1604 in the oblique direction.

FIG. 10 is a configuration diagram of the liquid crystal display device according to the present embodiment.

In the liquid crystal display device shown in FIG.
The liquid crystal panel 1601, the liquid crystal controller 1701, the drain driver 907, the gate driver 307, the AC voltage generating circuits 910 and 911, and the dividing resistors 912 and 913 are arranged in columns. In the liquid crystal panel 1601,
Since the pixel portion 1604 is driven for each row, the liquid crystal controller 1701 transfers display data to the drain driver 907 by the conventional circuit of FIG. Further, the conventional circuit of FIG. 19 can also be used for the gate driver 307. The AC conversion operation is the same as that of the liquid crystal display device of FIG. 2, and uses the AC voltage generation circuits 910 and 911 and the division resistors 912 and 913 of FIG. 2, and uses the same circuit as that of FIG. . A circuit similar to that shown in FIG. 4 is used for a circuit for generating an alternating signal in the liquid crystal controller 1701.

Next, the operation of the liquid crystal display of this embodiment will be described with reference to FIG.

The gate driver 307 is connected to the gate line 1602
In parallel with setting the voltage G (2) of the second row to the selection voltage (Vgon), the drain driver 907 outputs the display data (R2-0, G2-0, B2-0, R2-1, G2-
, B2-1...) And the AC signal 904, the drain voltages Vd + and Vd-
Output to As a result, the drain voltage Vd + or Vd− and the reference voltage are applied to each pixel portion 1604 in the second row. The transmittance of the liquid crystal 1607 is controlled by the potential difference between the voltage applied to the liquid crystal 1607 and the voltage applied to the additional capacitor 1608, and gradation display is performed. Then, this potential difference is held by the liquid crystal 1607 and the additional capacitor 1608 even after the voltage G (2) of the gate line 1602 becomes the non-selection voltage Vgoff.

After one line period, when the voltage G (2) becomes the non-selection voltage Vgoff and the voltage G (3) becomes the selection voltage Vgon, the TFT 1605 of each pixel portion 104 in the third row is turned on, and Then, a gray scale voltage based on the display data of the third row and the reference voltage 904 is output to the drain line 1603. Thus, the same operation is repeated every one line period, and all the pixel units 104 are driven in one frame period.

For example, during the period in which the voltage G (2) becomes the selection voltage Vgon, the common electrode (Strg0) 16 in the pixel portion 1604 in the second row and the odd-numbered column as shown in FIG.
When the reference voltage Vstrg0 of 09 becomes negative VstrgN, a positive potential difference is generated. At this time, in the pixel portion 1604 in the second row and the even column, the common electrode (Strg
1) The reference voltage Vstrg1 of 110 is a positive voltage Vs
By becoming trgP, a negative potential difference is generated. That is, the polarity of the potential difference generated in the pixel portion 104 in each row is inverted for each column. In addition, each common electrode (Strg
0, Strg1) The current flowing into 1609 and 1610 flows through individual wiring for each pixel current in the area forming the pixel portion 1604, and flows into n / 2 pixels in a wiring region other than the area forming the pixel portion 1604. Current. In a wiring region other than the area where the pixel portion 1604 is formed, it is possible to reduce the resistance by making the wiring thicker, whereas it is difficult to reduce the resistance in the area where the pixel portion 1604 is formed. Therefore, the fact that only one pixel's worth of current flows through each wiring in the area constituting the pixel portion 1604 greatly contributes to lower distortion of the liquid crystal applied voltage.

As described above, also in the liquid crystal display device of this embodiment, the current generated by the change in the voltage in the n pixel units 1604 of each row driven simultaneously has the common electrode (Strg).
0, Strg1) 1609 and 1610 do not intensively flow into one of them, so that the deterioration of the image quality due to the fluctuation of the voltage of the common electrode can be reduced as compared with the conventional example. Further, even when the polarity of the reference voltage applied to each of the common electrodes (Strg0, Strg1) 109 and 110 is fixed in one frame period, a positive voltage and a negative voltage are applied to the liquid crystal of each pixel of the liquid crystal panel. Since the voltage is applied evenly, the effect of preventing flicker can be obtained even when the frequency of the reference voltage is reduced, and the power consumption can be reduced as compared with the conventional example.

Next, a third embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIGS.

FIG. 12 is an equivalent circuit diagram of a liquid crystal panel according to the third embodiment of the present invention. The liquid crystal panel 1 of FIG.
901 differs from the liquid crystal panel 1601 in FIG. 9 only in the connection state between each pixel portion and the common electrode. That is, in the liquid crystal panel 1901 of this embodiment, a plurality of wirings between the counter electrodes 1612 are drawn in the vertical direction in the area forming the pixel portion 1604, and connect every other pixel portion 1604 in the vertical direction. As a result, the pixel portion 1 in the odd-numbered row and the odd-numbered column
904 and a pixel portion 1904 in an even-numbered row and an even-numbered column are connected to a common electrode (Strg0) 1909, and all other pixel portions 1904 are connected to a common electrode (Strg1) 1910.

FIG. 13 is a configuration diagram of a liquid crystal display device according to the third embodiment of the present invention. The liquid crystal display device in FIG. 13 has the same configuration as the liquid crystal display device in FIG. 10 except that the above-described liquid crystal panel 1901 is used as a liquid crystal panel.

The operation of the liquid crystal display device of this embodiment will be described with reference to FIG.
4 will be described.

In the liquid crystal display device of this embodiment, similarly to the second embodiment, the drain line 19 is set in parallel with the voltage G (2) of the gate line 1902 becoming the selection voltage (Vgon).
03, the display data of the pixels in the second row and the AC signal 90
4 are output. As a result, the drain voltage Vd + or Vd− and the reference voltage are applied to each pixel portion 1904 in the second row. After one line period, the voltage G (2) becomes the non-selection voltage Vgof.
f, and when the voltage G (3) becomes the selection voltage Vgon, 3
The TFT 105 of each pixel portion 1904 in the row is turned on, and in parallel with this, display data of each pixel in the third row and a gradation voltage based on the reference voltage 904 are output to the drain line 1903. In this manner, the same operation is repeated every one line period, and all the pixel portions 1904 are provided in one frame period.
Is driven.

For example, during the period in which the voltage G (2) is equal to the selection voltage Vgon, a positive potential difference is generated in the odd-numbered pixel section 1904 in the second row as shown in FIG. In the pixel portion 1904 in the column, a negative potential difference is generated. That is, the polarity of the potential difference generated in the pixel portion 1904 in each row is inverted for each column. Further, the current flowing into each of the common electrodes (Strg0, Strg1) 1909 and 1910 flows through individual wiring for each pixel in the area forming the pixel portion 1904, and the wiring region other than the area forming the pixel portion 1904 And the current for n / 2 pixels. For this reason, similarly to the second embodiment, the liquid crystal applied voltage can be stabilized.

As described above, even in the liquid crystal display device of the present embodiment, the deterioration of the image quality due to the fluctuation of the voltage of the common electrode can be reduced as compared with the conventional example, and the flicker can be prevented even when the frequency of the reference voltage is reduced. Since the effect is obtained, the power consumption can be reduced as compared with the conventional example.

[0056]

According to the present invention, the frequency of the voltage applied to the common electrode can be reduced without increasing flicker. Further, it is possible to eliminate the concentration of the current in the common electrode and reduce the deterioration of the image quality.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a liquid crystal panel according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a liquid crystal display device according to the first embodiment.

FIG. 3 is a block diagram of a data processing unit of the liquid crystal controller.

FIG. 4 is a block diagram of an AC signal generation unit of the liquid crystal controller.

FIG. 5 is a timing chart illustrating processing of a data processing unit.

FIG. 6 is a block diagram of a gate driver.

FIG. 7 is a block diagram of a drain driver.

FIG. 8 is a waveform chart showing the operation of the liquid crystal display device of the first embodiment.

FIG. 9 is an equivalent circuit diagram of a liquid crystal panel according to a second embodiment of the present invention.

FIG. 10 is a configuration diagram of a liquid crystal display device according to a second embodiment.

FIG. 11 is a waveform chart showing the operation of the liquid crystal display device of the second embodiment.

FIG. 12 is an equivalent circuit diagram of a liquid crystal panel according to a third embodiment of the present invention.

FIG. 13 is a configuration diagram of a liquid crystal display device according to a third embodiment.

FIG. 14 is a waveform chart illustrating the operation of the liquid crystal display device according to the third embodiment.

FIG. 15 is an equivalent circuit diagram of a conventional liquid crystal panel.

FIG. 16 is a configuration diagram of a conventional liquid crystal display device.

FIG. 17 is a block diagram of a data processing unit of a conventional liquid crystal controller.

FIG. 18 is a block diagram of an AC signal generator of a conventional liquid crystal controller.

FIG. 19 is a lock diagram of a conventional gate drive.

FIG. 20 is a block diagram of a conventional drain driver.

FIG. 21 is a waveform chart showing the operation of a conventional liquid crystal display device.

[Explanation of symbols]

[FIG. 1] 101: liquid crystal panel, 102: gate line bus, 103: drain line bus, 104: pixel portion, 10
5: thin film transistor (TFT), 106: pixel electrode,
107, 111: liquid crystal, 108: additional capacitance, 109: common electrode (Strg0), 110: common electrode (Strg0)
1), 112: counter electrode. [FIG. 2] 901: signal bus, 902: liquid crystal controller, 903: signal bus, 904, 905: AC signal,
906: signal bus, 907: drain driver, 90
8: Gate driver, 910: AC voltage generation circuit, 91
1: AC voltage generation circuit, 912: division resistance, 913: division resistance, 914: gradation voltage signal, 915: gradation voltage signal. [FIG. 3] 1001: display data, 1002: synchronization signal, 1003: data delay circuit, 1004: display data, 1005: selection circuit. [FIG. 4] 1101: vertical synchronization signal, 1102: horizontal synchronization signal, 1103: flip-flop, 1104: frequency-divided signal, 1105: flip-flop, 1106: frequency-divided signal, 1107: exclusive logic circuit, 1108: output signal,
1109: Inverting circuit, 1110: Output signal, 1111:
Flip-flop, 1112: flip-flop. [FIG. 6] 1301: first line valid timing signal,
1302: synchronization signal, 1303: shift register, 13
04: output signal, 1305: level shifter, 1306:
Output signal, 1307: voltage selection circuit. [FIG. 7] 1401: signal bus, 1402: enable signal, 1403: clock, 1404: clock, 14
05: shift register, 1406: sampling clock, 1407: line latch circuit, 1408: data bus, 1409: line latch circuit, 1410: data bus, 1411: positive gradation voltage generation circuit, 1412: voltage bus, 1413: negative electrode Gray scale voltage generation circuit, 141
4: voltage bus, 1415: voltage selector. [FIG. 9] 1601: liquid crystal panel, 1602: gate line bus, 1603: drain line bus, 1604: pixel portion,
1605: thin film transistor (TFT), 1606: pixel electrode, 1607, 1600: liquid crystal, 1608: additional capacitance, 1609: common electrode (Strg0), 1610: common electrode (Strg1). [FIG. 10] 1701: a liquid crystal controller. [FIG. 12] 1901: liquid crystal panel, 1902: gate line, 1903: drain line, 1904: pixel portion, 190
5: thin film transistor (TFT), 1906: pixel electrode, 1907, 1911: liquid crystal, 1908: additional capacitance,
1909: common electrode (Strg0), 1910: common electrode (Strg1), 1912: counter electrode. [FIG. 15] 201: liquid crystal panel, 202: gate line,
203: drain line, 204: pixel portion, 205: thin film transistor (TFT), 206: pixel electrode, 208: liquid crystal, 207: additional capacitance, 209: common electrode (Com),
210: common electrode (Strg). [FIG. 16] 301: signal bus, 302: liquid crystal controller, 303: signal bus, 304: AC signal, 30
5: signal bus, 306: drain driver, 307: gate driver, 309: AC voltage generation circuit, 310: AC voltage generation circuit, 311: division resistance, 312: gradation voltage signal, 313: AC voltage generation circuit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshio Futami 3300 Hayano, Mobara-shi, Chiba Electronic Device Division, Hitachi, Ltd.

Claims (9)

[Claims] 1. A liquid crystal panel comprising two substrates disposed opposite to each other and a liquid crystal filled between the two substrates, wherein M rows and N columns of pixels are formed on the substrates. M corresponding to
× N pixel units, a plurality of drain lines, a plurality of gate lines, and two counter electrode lines, wherein each of the pixel units includes a gate electrode connected to any one of the gate lines. A thin film transistor comprising: a drain electrode connected to any one of the drain lines; and a source electrode; a pixel electrode connected to a source electrode of the thin film transistor; and a pair of the pixel electrode and the liquid crystal. An opposing electrode for applying an electric field to change the transmittance of the liquid crystal for a corresponding pixel, wherein the opposing electrode is divided into two groups and each group is connected to the two opposing electrode lines. A liquid crystal panel characterized by the above-mentioned. 2. The liquid crystal panel according to claim 1, wherein the counter electrode is paired with the pixel electrode to form a capacitor for maintaining the electric field, and is connected to each one of the gate lines. A liquid crystal panel characterized in that the number of thin film transistors connected to a pair of pixel electrodes and a counter electrode connected to the same counter electrode line among the thin film transistors is approximately N / 2. 3. The liquid crystal panel according to claim 1, wherein each one of the drain lines is connected to a drain electrode of a thin film transistor corresponding to each one of the columns. One counter electrode line is connected to a counter electrode corresponding to the odd-numbered row of thin film transistors, and the other counter electrode line is connected to a counter electrode corresponding to the even-numbered row of thin film transistors; Are connected to thin film transistors in even or odd columns in each row, or connected to thin film transistors in odd or even columns in one row adjacent to each row together with the thin film transistors. A liquid crystal panel. 4. The liquid crystal panel according to claim 1, wherein each one drain line is connected to a drain electrode of a thin film transistor corresponding to each one column, and each one gate line is One counter electrode line is connected to a thin film transistor in one row, and one counter electrode line corresponds to a thin film transistor in an odd-numbered row or an odd-numbered or even-numbered column, and an even-numbered row corresponding to an even-numbered or odd-numbered column. The other counter electrode line is commonly connected to the counter electrodes corresponding to the even-numbered or odd-numbered columns in the odd-numbered rows and the thin-film transistors in the odd-numbered or even-numbered columns in the even-numbered rows. A liquid crystal panel, which is connected. 5. The liquid crystal panel according to claim 3, wherein the two opposing electrode lines are formed of a plurality of wirings drawn in parallel in a vertical or oblique direction on the substrate. A liquid crystal panel, wherein, among thin film transistors connected to one gate line, the number of thin film transistors corresponding to a counter electrode connected to the same wiring is one. 6. A liquid crystal display according to claim 1, wherein display data and a synchronization signal are captured, and an image represented by the display data can be displayed on the liquid crystal panel based on the captured display data and synchronization signal. A liquid crystal controller that generates data and a liquid crystal synchronization signal; scanning voltage generation means that applies a selection voltage or a non-selection voltage to the gate line according to the liquid crystal synchronization signal; Reference voltage generating means for applying reference voltages of predetermined levels having different polarities from each other, and inverting the polarities of the two reference voltages at a predetermined cycle; and the liquid crystal display data and the reference voltage according to the liquid crystal synchronization signal. And a grayscale voltage generating means for generating a grayscale voltage based on the grayscale voltage and applying the grayscale voltage to the drain line. Liquid crystal display device. 7. A liquid crystal display according to claim 2, wherein display data and a synchronization signal are taken in, and an image represented by the display data can be displayed on the liquid crystal panel based on the taken in display data and the synchronization signal. A liquid crystal controller that generates data and a liquid crystal synchronization signal; scanning voltage generation means that applies a selection voltage or a non-selection voltage to the gate line according to the liquid crystal synchronization signal; A reference voltage generating means for applying a reference voltage; and a gradation voltage generating means for generating a gradation voltage based on the liquid crystal display data and the reference voltage in accordance with the liquid crystal synchronization signal, and applying the gradation voltage to the drain line. A liquid crystal display device comprising: 8. The liquid crystal display device according to claim 6, wherein the reference voltage generation means inverts the polarity of the reference voltage every display period of one frame of the liquid crystal display data, A liquid crystal display device, wherein the generation means generates the gradation voltage based on a reference voltage having a different polarity for each display period of one line of the liquid crystal display data. 9. The liquid crystal display device according to claim 6, wherein the liquid crystal controller stores the acquired display data in accordance with a connection state between the thin film transistor, a gate line, and a drain line in the liquid crystal panel. A liquid crystal display device, wherein the liquid crystal display data is generated by performing rearrangement.