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JPH10111723A - Voltage stabilization circuit - Google Patents

Voltage stabilization circuit

Info

Publication number
JPH10111723A
JPH10111723A JP8264954A JP26495496A JPH10111723A JP H10111723 A JPH10111723 A JP H10111723A JP 8264954 A JP8264954 A JP 8264954A JP 26495496 A JP26495496 A JP 26495496A JP H10111723 A JPH10111723 A JP H10111723A
Authority
JP
Japan
Prior art keywords
voltage
transistor
circuit
terminal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8264954A
Other languages
Japanese (ja)
Other versions
JP3543509B2 (en
Inventor
Atsushi Yamada
敦史 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP26495496A priority Critical patent/JP3543509B2/en
Publication of JPH10111723A publication Critical patent/JPH10111723A/en
Application granted granted Critical
Publication of JP3543509B2 publication Critical patent/JP3543509B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/30Reactive power compensation

Landscapes

  • Supply And Distribution Of Alternating Current (AREA)
  • Control Of Electrical Variables (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Amplifiers (AREA)

Abstract

(57)【要約】 (修正有) 【課題】電圧変換回路の出力電圧を入力電圧とするMO
S構造の電圧安定化回路に関する。 【解決手段】電圧安定化回路40の入力電圧印加端子7
と安定化出力電圧端子8との間に、入力電圧印加端子7
にドレイン電極を接続したMOSトランジスタ11のソ
ース電極と、安定化出力電圧出力端子8にドレイン電極
を接続したMOSトランジスタ9のソース電極とを共通
にして直列接続し、かつ、安定化出力電圧出力端子8と
GND端子間にMOSトランジスタ12を直列挿入す
る。 【効果】電圧変換回路5や電圧安定化回路40の回路動
作停止時に、出力容量10に蓄積された電荷の負荷以外
への放電経路がなくなるため、特に液晶パネルのような
容量性負荷を接続して使用する場合には、電圧変換回路
や電圧安定化回路を間欠動作させることが可能となり、
消費電流の低減、電圧変換効率の向上が図れる。
(57) [Abstract] (with correction) [PROBLEMS] MO that uses output voltage of voltage conversion circuit as input voltage
The present invention relates to an S-structure voltage stabilizing circuit. An input voltage applying terminal of a voltage stabilizing circuit is provided.
Between the input voltage applying terminal 7 and the stabilized output voltage terminal 8.
A source electrode of a MOS transistor 11 having a drain electrode connected to the source electrode and a source electrode of a MOS transistor 9 having a drain electrode connected to a stabilized output voltage output terminal 8 are connected in common and connected in series. The MOS transistor 12 is inserted in series between the terminal 8 and the GND terminal. When the circuit operation of the voltage conversion circuit 5 and the voltage stabilization circuit 40 is stopped, there is no discharge path to the load other than the load of the charge accumulated in the output capacitor 10, so that a capacitive load such as a liquid crystal panel is connected. In the case of using it, the voltage conversion circuit and the voltage stabilization circuit can be operated intermittently,
The current consumption can be reduced and the voltage conversion efficiency can be improved.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電圧変換回路の出
力電圧を入力電圧とするMOS構造の電圧安定化回路に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage stabilizing circuit having a MOS structure using an output voltage of a voltage conversion circuit as an input voltage.

【0002】[0002]

【従来の技術】従来、1.5Vの電池を電源として例え
ば液晶駆動用に安定化された定電圧出力を得るには、図
2に示すように電源電圧入力端子6に1.5Vの電池電
圧を入力して電圧変換回路5にて昇圧してその昇圧され
た出力電圧を電圧安定化回路4の入力電圧として電圧安
定化回路入力電圧印加端子7に入力して電圧安定化回路
4にて安定化された定電圧出力たとえば3V程度の定電
圧出力を安定化電圧出力端子8に発生させる回路構成に
て実現していた。電圧変換回路5の出力電圧を入力電圧
とするMOS構造の電圧安定化回路4は、図2に示すよ
うに基準電圧発生回路1とオペアンプ差動段回路2とオ
ペアンプ出力段回路3により構成されていた。
2. Description of the Related Art Conventionally, in order to obtain a stabilized constant voltage output for driving a liquid crystal, for example, using a 1.5 V battery as a power source, a 1.5 V battery voltage is applied to a power voltage input terminal 6 as shown in FIG. Is input to the voltage stabilization circuit 4, and the boosted output voltage is input to the voltage stabilization circuit input voltage application terminal 7 as an input voltage of the voltage stabilization circuit 4 and is stabilized by the voltage stabilization circuit 4. A stabilized constant voltage output, for example, a constant voltage output of about 3 V is generated at the stabilized voltage output terminal 8 by a circuit configuration. A voltage stabilizing circuit 4 having a MOS structure using the output voltage of the voltage converting circuit 5 as an input voltage includes a reference voltage generating circuit 1, an operational amplifier differential stage circuit 2, and an operational amplifier output stage circuit 3, as shown in FIG. Was.

【0003】[0003]

【発明が解決しようとする課題】しかし、従来の電圧安
定化回路4の回路構成では、安定化された定電圧を安定
化電圧出力端子8に得るには、電圧変換回路5の回路動
作を停止して電圧安定化回路4に入力される電圧が電源
電圧1.5Vまで低下すると電圧安定化回路4の駆動用
MOSトランジスタ9の寄生ダイオード35により安定
化電圧出力端子8に接続された出力安定化用コンデンサ
10に蓄積された電荷が放電されて電圧が低下してしま
う。これをさけるために、電圧変換回路5は常時動作さ
せて電圧安定化回路4の入力電圧印加端子7には常に安
定化電圧出力端子8の定電圧値より高い電圧を印加した
状態にする必要があった。即ち、安定化電圧出力端子8
に接続される負荷の大小、負荷の種類に関係なく常に回
路全体を動作させる必要があった。従って、電池を使用
した携帯機器において液晶パネルのような容量性負荷を
駆動する場合、出力安定化用コンデンサ10に3Vとい
う所望の電圧を発生させたあとで出力安定化用コンデン
サ10から負荷へ流れたわずかな電荷分を出力電圧の許
容される電圧範囲内で補充できるように、上記の電圧変
換回路5と電圧安定化回路4を間欠動作させ、電圧変換
回路5や電圧安定化回路4での無効電流を減らして低消
費電流化、電源の変換効率を向上させる、という課題が
達成できなかった。また、間欠動作をさせようとする
と、動作停止時に電圧安定化回路4の駆動用MOSトラ
ンジスタ9の寄生ダイオード構造により安定化電圧出力
端子8の電圧が入力される電源まで低下するため、動作
開始する毎に出力安定化コンデンサ10に電荷が蓄積さ
れ所望の安定化された定電圧を得るまでに待機時間が必
要であった。そのため、従来の電源安定化回路を用いる
と回路の動作スピードを向上できないという欠点があっ
た。
However, in the circuit configuration of the conventional voltage stabilizing circuit 4, in order to obtain a stabilized constant voltage at the stabilized voltage output terminal 8, the circuit operation of the voltage converting circuit 5 is stopped. Then, when the voltage input to the voltage stabilizing circuit 4 drops to the power supply voltage 1.5 V, the output stabilization connected to the stabilizing voltage output terminal 8 by the parasitic diode 35 of the driving MOS transistor 9 of the voltage stabilizing circuit 4 The electric charge stored in the capacitor 10 is discharged and the voltage drops. In order to avoid this, it is necessary to always operate the voltage conversion circuit 5 so that a voltage higher than the constant voltage value of the stabilized voltage output terminal 8 is always applied to the input voltage application terminal 7 of the voltage stabilization circuit 4. there were. That is, the stabilized voltage output terminal 8
It is necessary to always operate the entire circuit irrespective of the size of the load connected to the circuit and the type of load. Therefore, when driving a capacitive load such as a liquid crystal panel in a portable device using a battery, the output stabilizing capacitor 10 generates a desired voltage of 3 V and then flows from the output stabilizing capacitor 10 to the load. The voltage conversion circuit 5 and the voltage stabilization circuit 4 are operated intermittently so that the small amount of charge can be replenished within the allowable voltage range of the output voltage. The problem of reducing the reactive current and reducing the current consumption and improving the conversion efficiency of the power supply could not be achieved. When the intermittent operation is to be performed, the operation starts because the voltage of the stabilized voltage output terminal 8 drops to the power supply to which the voltage of the stabilized voltage output terminal 8 is input due to the parasitic diode structure of the driving MOS transistor 9 of the voltage stabilizing circuit 4 when the operation is stopped. Each time, the electric charge is accumulated in the output stabilizing capacitor 10 and a waiting time is required until a desired stabilized constant voltage is obtained. Therefore, there is a disadvantage that the operation speed of the circuit cannot be improved when the conventional power supply stabilizing circuit is used.

【0004】そこで、本発明ではこのような課題を解決
するもので、その目的とするところは電池を電源として
使用した携帯機器において液晶パネルのような容量性負
荷を駆動するのに適した定電圧を得る回路構成にして無
効電流を減らして消費電流の低減と電源変換効率を向上
させる電圧安定化回路を提供するところにある。
In view of the above, the present invention solves such a problem, and an object thereof is to provide a constant voltage suitable for driving a capacitive load such as a liquid crystal panel in a portable device using a battery as a power supply. It is another object of the present invention to provide a voltage stabilizing circuit that reduces the reactive current by reducing the reactive current and improves the power supply conversion efficiency.

【0005】[0005]

【課題を解決するための手段】請求項1記載の電圧安定
化回路は、第1の電源端子に印加される電圧を安定化し
て出力端子に出力する電圧安定化回路において、前記第
1の電源端子と前記出力端子との間に、放電防止手段と
駆動用トランジスタとを直列接続してなり、前記放電防
止手段は前記第1の電源端子に印加される電圧が前記出
力端子の電圧よりも低いときに、該出力端子から該第1
の電源端子への電荷の放電を防止してなることを特徴と
する。
A voltage stabilizing circuit according to claim 1, wherein said voltage stabilizing circuit stabilizes a voltage applied to a first power supply terminal and outputs the voltage to an output terminal. A discharge prevention unit and a driving transistor connected in series between the output terminal and the output terminal, wherein the discharge prevention unit is configured such that a voltage applied to the first power supply terminal is lower than a voltage of the output terminal. Sometimes, the first terminal is connected to the output terminal.
In which the discharge of electric charge to the power supply terminal is prevented.

【0006】請求項2記載の電圧安定化回路は、請求項
1記載の電圧安定化回路において、前記放電防止手段
は、第1のトランジスタを有し、該第1のトランジスタ
のドレインには前記第1の電源端子に印加される電圧が
供給され、該第1のトランジスタのソースが前記駆動用
トランジスタのソースに接続され、該第1のトランジス
タのゲートには該第1のトランジスタのソースの電位と
略同一の電位が供給されてなることを特徴とする。
A voltage stabilizing circuit according to a second aspect of the present invention is the voltage stabilizing circuit according to the first aspect, wherein the discharge preventing means has a first transistor, and a drain of the first transistor has a drain connected to the first transistor. A voltage applied to the first power supply terminal is supplied, a source of the first transistor is connected to a source of the driving transistor, and a gate of the first transistor is connected to a source potential of the first transistor. It is characterized in that substantially the same potential is supplied.

【0007】請求項3記載の電圧安定化回路は、請求項
2記載の電圧安定化回路において、前記第1のトランジ
スタのゲートとソースとの間に第2のトランジスタを有
し、該第2のトランジスタのゲートとソースは前記第1
のトランジスタのソースに接続され、該第2のトランジ
スタのドレインは前記第1のトランジスタのゲートに接
続されてなることを特徴とする。
According to a third aspect of the present invention, in the voltage stabilizing circuit according to the second aspect, a second transistor is provided between a gate and a source of the first transistor. The gate and source of the transistor are the first
And the drain of the second transistor is connected to the gate of the first transistor.

【0008】請求項4記載の電圧安定化回路は、基準電
圧発生回路と、安定化電圧出力端子と接地端子間に接続
された分圧回路と、基準電圧発生回路の出力と分圧回路
の分圧出力を入力とする差動入力オペアンプ回路と、ゲ
ート電極が差動入力オペアンプ回路の出力に接続されド
レインが安定化電圧出力端子に接続された駆動用トラン
ジスタとを有する電圧安定化回路であって、電圧安定化
回路の入力電圧印加端子にドレインを接続し前記駆動用
トランジスタのソースにソースを接続した第3のトラン
ジスタと、安定化電圧出力端子と接地端子との間に前記
分圧回路と直列に接続された第4のトランジスタと、該
第4のトランジスタが非導通状態のときに、前記第3の
トランジスタが非導通となるような電圧を該第3のトラ
ンジスタのゲートに供給してなる手段とを具備すること
を特徴とする。
According to a fourth aspect of the present invention, there is provided a voltage stabilizing circuit, comprising: a reference voltage generating circuit; a voltage dividing circuit connected between a stabilized voltage output terminal and a ground terminal; And a driving transistor having a gate electrode connected to the output of the differential input operational amplifier circuit and a drain connected to the stabilized voltage output terminal. A third transistor having a drain connected to the input voltage application terminal of the voltage stabilizing circuit and a source connected to the source of the driving transistor, and a series connected to the voltage dividing circuit between the stabilized voltage output terminal and the ground terminal. And a voltage that causes the third transistor to be non-conductive when the fourth transistor is non-conductive, to the gate of the third transistor. Characterized by comprising a means formed by supply.

【0009】本発明の請求項1ないし3記載の発明によ
れば、前記第1の電源端子と前記出力端子との間に、放
電防止手段と駆動用トランジスタとを直列接続してな
り、前記放電防止手段は前記第1の電源端子に印加され
る電圧が前記出力端子の電圧よりも低いときに、該出力
端子から該第1の電源端子への電荷の放電を防止してな
るため、出力端子8に接続された負荷以外への放電経路
が無くなり、液晶パネルのような容量性負荷の場合に
は、電圧安定化回路の間欠動作が可能となり無効電流を
減らして低消費電流化や電源変換効率の向上を実現する
ことが可能となる。
According to the first to third aspects of the present invention, the discharge preventing means and the driving transistor are connected in series between the first power supply terminal and the output terminal. When the voltage applied to the first power supply terminal is lower than the voltage at the output terminal, the prevention means prevents discharge of electric charge from the output terminal to the first power supply terminal. In the case of a capacitive load such as a liquid crystal panel, intermittent operation of the voltage stabilizing circuit is enabled, the reactive current is reduced, the current consumption is reduced, and the power conversion efficiency is reduced. Can be improved.

【0010】また、本発明の請求項4記載の発明によれ
ば、電圧安定化回路40の入力電圧印加端子7と安定化
電圧出力端子8との間に接続されたトランジスタ11
と、安定化電圧出力端子8とGND端子との間に接続さ
れたトランジスタ12とにより、電圧変換回路5と電圧
安定化回路40を動作停止状態にしても出力電圧安定化
用コンデンサ10に蓄積された電荷が、安定化電源出力
端子8から入力電圧印加端子へ放電されて電流が逆流す
ることを阻止するため、安定化電圧出力端子8に接続さ
れた負荷以外への放電経路が無くなり、液晶パネルのよ
うな容量性負荷の場合には、電圧変換回路と電圧安定化
回路の間欠動作が可能となり無効電流を減らして低消費
電流化や電源変換効率の向上を実現することが可能とな
る。
According to a fourth aspect of the present invention, the transistor 11 connected between the input voltage application terminal 7 and the stabilized voltage output terminal 8 of the voltage stabilizing circuit 40 is provided.
And the transistor 12 connected between the stabilized voltage output terminal 8 and the GND terminal, the voltage is stored in the output voltage stabilizing capacitor 10 even when the voltage conversion circuit 5 and the voltage stabilization circuit 40 are in an operation stop state. In order to prevent the discharged electric charge from being discharged from the stabilized power supply output terminal 8 to the input voltage application terminal and causing the current to flow backward, there is no discharge path to a portion other than the load connected to the stabilized voltage output terminal 8, and the liquid crystal panel In the case of such a capacitive load, an intermittent operation of the voltage conversion circuit and the voltage stabilization circuit becomes possible, so that the reactive current can be reduced, thereby reducing the current consumption and improving the power supply conversion efficiency.

【0011】[0011]

【発明の実施の形態】以下、本発明について実施の形態
に基づいて詳細に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail based on embodiments.

【0012】図1は、本発明の電圧安定化回路を使用し
た一実施の形態である。1は、基準電圧発生回路、2
は、オペアンプ差動段回路、3は、オペアンプ出力段回
路、40は、電圧安定化回路である。5は、電圧変換回
路で、通常コンデンサを使用したチャージポンプ回路方
式で構成する。6は、電池等の電源を接続する電源電圧
入力端子、7は、電圧安定化回路入力電圧印加端子、8
は、安定化電圧出力端子であり、図示しない液晶パネル
等の負荷に接続される。9は、駆動用MOSトランジス
タ、10は、出力電圧安定化用コンデンサ、11と12
が放電防止用MOSトランジスタ、14は、オンオフ動
作制御信号入力端子、15は、オンオフ動作制御用デプ
レション型PチャネルMOSトランジスタ、16は、オ
ンオフ動作制御用エンハンスメント型NチャネルMOS
トランジスタ、20は、オペアンプ位相補償用コンデン
サ、21は、オンオフ動作制御用エンハンスメント型P
チャネルMOSトランジスタ、22・23は、Pチャネ
ルMOSトランジスタ、24・25は、NチャネルMO
Sトランジスタ、27は、オンオフ動作制御用エンハン
スメント型NチャネルMOSトランジスタ、26は、定
電流用デプレッション型NチャネルMOSトランジス
タ、33は、接地端子である。また、34は放電防止用
MOSトランジスタ11の寄生ダイオート゛、35は駆動
用用MOSトランジスタ9の寄生ダイオート゛を図示した
ものである。
FIG. 1 shows an embodiment using the voltage stabilizing circuit of the present invention. 1 is a reference voltage generating circuit, 2
Is an operational amplifier differential stage circuit, 3 is an operational amplifier output stage circuit, and 40 is a voltage stabilizing circuit. Reference numeral 5 denotes a voltage conversion circuit, which is usually configured by a charge pump circuit system using a capacitor. 6 is a power supply voltage input terminal for connecting a power supply such as a battery, 7 is a voltage stabilization circuit input voltage application terminal, 8
Is a stabilized voltage output terminal, which is connected to a load such as a liquid crystal panel (not shown). 9 is a driving MOS transistor, 10 is an output voltage stabilizing capacitor, and 11 and 12
Is a discharge prevention MOS transistor, 14 is an on / off operation control signal input terminal, 15 is an on / off operation control depletion type P-channel MOS transistor, and 16 is an on / off operation control enhancement N-channel MOS transistor.
A transistor 20 is an operational amplifier phase compensation capacitor, and 21 is an on / off operation control enhancement type P
Channel MOS transistors, 22 and 23 are P channel MOS transistors, and 24 and 25 are N channel MO transistors.
The S transistor 27 is an enhancement type N-channel MOS transistor for ON / OFF operation control, 26 is a depletion type N-channel MOS transistor for constant current, and 33 is a ground terminal. Numeral 34 denotes a parasitic diode of the MOS transistor 11 for preventing discharge, and numeral 35 denotes a parasitic diode of the MOS transistor 9 for driving.

【0013】次に、図1の実施の形態における動作を説
明する。電池等の1.5Vの電圧から安定化電圧出力端
子8に、液晶パネルを駆動するのに必要な例えば3Vの
出力電圧を得るには、電源電圧入力端子6に印加された
入力電圧を通常はコンデンサを使用したチャージポンプ
方式で構成される電圧変換回路5で昇圧し3V以上の昇
圧電圧を得、該昇圧電圧を電圧安定化回路40の入力電
圧印加端子7に入力して安定化電圧出力端子8に所望の
3Vの定電圧出力を得る。電圧安定化回路40は、オペ
アンプ差動段回路2とオペアンプ出力段回路3により構
成されており、オペアンプ出力段回路3の抵抗R14と
抵抗R13で分圧された節点(ノード)30の電圧をオ
ペアンプ差動段回路2に電圧帰還をかけてIC内部で生
成する基準電圧28と比較して、オペアンプ出力段回路
3の出力駆動用トランジスタ9のゲート電極に接続され
ている節点29の電圧を制御することにより安定化電圧
出力端子8に安定化された定電圧を得る回路である。安
定化電圧出力端子8に出力される定電圧値Voutは、オ
ペアンプ出力段回路3に接続された抵抗R13、R14
と基準電圧発生回路1が出力する基準電圧値Vrefによ
り決定され下記の式により表される。
Next, the operation of the embodiment shown in FIG. 1 will be described. In order to obtain an output voltage of, for example, 3 V necessary for driving the liquid crystal panel from a voltage of 1.5 V of a battery or the like to the stabilized voltage output terminal 8, the input voltage applied to the power supply voltage input terminal 6 is usually changed. The voltage is boosted by a voltage conversion circuit 5 configured by a charge pump method using a capacitor to obtain a boosted voltage of 3 V or more, and the boosted voltage is input to an input voltage application terminal 7 of a voltage stabilization circuit 40 and a stabilized voltage output terminal At 8, a desired constant voltage output of 3 V is obtained. The voltage stabilizing circuit 40 includes an operational amplifier differential stage circuit 2 and an operational amplifier output stage circuit 3. The voltage stabilizing circuit 40 converts the voltage of the node 30 divided by the resistors R14 and R13 of the operational amplifier output stage circuit 3 into an operational amplifier. The voltage at the node 29 connected to the gate electrode of the output driving transistor 9 of the operational amplifier output stage circuit 3 is controlled by comparing the reference voltage 28 generated inside the IC by applying voltage feedback to the differential stage circuit 2. This is a circuit for obtaining a stabilized constant voltage at the stabilized voltage output terminal 8. The constant voltage value Vout output to the stabilized voltage output terminal 8 is determined by the resistances R13 and R14 connected to the operational amplifier output stage circuit 3.
And the reference voltage value Vref output from the reference voltage generation circuit 1 and is represented by the following equation.

【0014】 Vout=Vref×(R13+R14)/R13 この回路構成で、オンオフ動作制御信号入力端子14に
Lレベルを入力して、電圧変換回路5や電圧安定化回路
40の回路動作を停止させると、電圧安定化回路40の
入力電圧印加端子7と安定化電圧出力端子8の間に直列
に接続されている駆動用MOSトランジスタ9は、オン
オフ動作制御用トランジスタ21が導通状態になるので
節点29に接続されている駆動用MOSトランジスタの
ゲート電極にはHレベルが供給され非導通状態になる。
また、放電防止用トランジスタ11のゲート電極に接続
されている節点31は、オンオフ動作制御用エンハンス
メント型NチャネルMOSトランジスタ16が非導通状
態になり、常に導通状態となるオンオフ動作制御用デプ
レッション型PチャネルMOSトランンジスタ15によ
りソース電極に接続されている節点32と同一電位にな
るので、放電防止用トランジスタ11も非導通状態にな
る。従って、電圧変換回路5や電圧安定化回路40を動
作停止状態にして電圧安定化回路入力電圧印加端子7に
入力される電圧が安定化電圧出力端子8の電圧より低下
しても出力安定化用コンデンサ10に蓄積された電荷の
入力電圧側へのMOSトランジスタ9及びMOSトラン
ジスタの寄生ダイオード35による放電経路又は逆流経
路はなくなる。また、回路動作停止時には安定化電圧出
力端子8と接地端子間に接続されたMOSトランジスタ
12も非導通状態になるため接地端子側への放電経路も
なくなる。従って、電圧変換回路5や電圧安定化回路4
0を動作制御信号14により停止させても出力安定化用
コンデンサ10に蓄えられた電荷は、出力に接続された
負荷に電荷が流れない限り電荷が保持される回路構成に
なる。出力安定化用コンデンサ10のリーク電流は負荷
に比べて無視できる程度に小さい値で実現できる。ま
た、かかる放電又は逆流の防止にMOSトランジスタ1
1を用いているため、電圧降下が小さくなり、電圧変換
効率の低下もなくなる。
Vout = Vref × (R13 + R14) / R13 With this circuit configuration, when an L level is input to the on / off operation control signal input terminal 14 to stop the circuit operations of the voltage conversion circuit 5 and the voltage stabilization circuit 40, The drive MOS transistor 9 connected in series between the input voltage application terminal 7 and the stabilized voltage output terminal 8 of the voltage stabilization circuit 40 is connected to the node 29 because the on / off operation control transistor 21 is turned on. The H level is supplied to the gate electrode of the driving MOS transistor, which is turned off.
A node 31 connected to the gate electrode of the discharge prevention transistor 11 is a depletion-type P-channel for ON / OFF operation control in which the ON / OFF operation control enhancement N-channel MOS transistor 16 is in a non-conductive state and is always in a conductive state. Since the MOS transistor 15 has the same potential as the node 32 connected to the source electrode, the discharge preventing transistor 11 is also turned off. Therefore, even if the voltage input to the voltage stabilization circuit input voltage application terminal 7 becomes lower than the voltage of the stabilization voltage output terminal 8 when the voltage conversion circuit 5 and the voltage stabilization circuit 40 are in the operation stop state, the output stabilization circuit is used. There is no discharge path or reverse path due to the MOS transistor 9 and the parasitic diode 35 of the MOS transistor to the input voltage side of the charge accumulated in the capacitor 10. Further, when the circuit operation is stopped, the MOS transistor 12 connected between the stabilized voltage output terminal 8 and the ground terminal is also turned off, so that there is no discharge path to the ground terminal. Therefore, the voltage conversion circuit 5 and the voltage stabilization circuit 4
Even if 0 is stopped by the operation control signal 14, the electric charge stored in the output stabilizing capacitor 10 has a circuit configuration in which the electric charge is held unless the electric charge flows to the load connected to the output. The leak current of the output stabilizing capacitor 10 can be realized with a value negligibly small as compared with the load. In order to prevent such discharge or backflow, a MOS transistor 1
Since 1 is used, the voltage drop is small and the voltage conversion efficiency is not reduced.

【0015】なお、本実施の形態の変形例として、放電
防止用トランジスタ11をダイオードに置き換えた構成
をとることも可能である。この構成は、回路動作時のダ
イオード順方向電圧降下が小さく、電圧変換効率が低下
しないような状況で使用すれば、上記の構成の場合と同
様に出力安定化用コンデンサ10に蓄積された電荷の入
力電圧側への放電経路をなくすことが可能となる。
As a modification of the present embodiment, it is possible to adopt a configuration in which the discharge preventing transistor 11 is replaced with a diode. If this configuration is used in a situation where the diode forward voltage drop during circuit operation is small and the voltage conversion efficiency does not decrease, the charge stored in the output stabilizing capacitor 10 can be reduced in the same manner as in the above configuration. It is possible to eliminate a discharge path to the input voltage side.

【0016】また、本実施の形態の他の変形例として、
トランジスタ15に換えて高抵抗の抵抗素子を使用して
もよい。抵抗値はトランジスタ16が導通したときのG
NDへ流れる電流の仕様に応じて決めることができる。
As another modified example of the present embodiment,
A high resistance element may be used instead of the transistor 15. The resistance value is G when the transistor 16 is turned on.
It can be determined according to the specification of the current flowing to the ND.

【0017】次に、この回路構成での、オンオフ動作制
御信号入力端子14にHレベルを入力したときの動作を
説明する。オンオフ動作制御信号入力端子14にHレベ
ルを入して電圧変換回路5や電圧安定化回路40の回路
動作を停止を解除させると、電圧安定化回路40の入力
電圧印加端子7と安定化電圧出力端子8の間に直列に接
続されている駆動用MOSトランジスタ9は、オンオフ
動作制御用トランジスタ21が非導通状態になるので節
点29に接続されている駆動用MOSトランジスタのゲ
ート電極には差動段回路2の出力29が供給され動作状
態になる。また、放電防止用トランジスタ11のゲート
電極に接続されている節点31は、オンオフ動作制御用
エンハンスメント型NチャネルMOSトランジスタ16
が導通状態になるため、GNDレベルとなり、放電防止
用トランジスタ11は導通状態となる。また、トランジ
スタ12も導通状態となるため、出力段回路3は通常の
能動状態となる。なお、このとき常に導通状態となるオ
ンオフ動作制御用デプレッション型PチャネルMOSト
ランンジスタ15のドレインもGNDレベルとなるた
め、節点32からトランジスタ15、16を介してGN
Dに電流が流れるが、トランジスタ15の電気的特性を
適切に選んで微少電流しか流れないようなトランジスタ
に設計しておけば問題にならない。従って、出力端子8
からは安定化電圧が出力されることになる。
Next, the operation of this circuit configuration when an H level is input to the on / off operation control signal input terminal 14 will be described. When the H level is input to the on / off operation control signal input terminal 14 to stop the circuit operation of the voltage conversion circuit 5 and the voltage stabilization circuit 40, the input voltage application terminal 7 of the voltage stabilization circuit 40 and the stabilized voltage output The driving MOS transistor 9 connected in series between the terminals 8 has a differential stage connected to the gate electrode of the driving MOS transistor connected to the node 29 because the on / off operation control transistor 21 is turned off. The output 29 of the circuit 2 is supplied and the circuit 2 is activated. A node 31 connected to the gate electrode of the discharge prevention transistor 11 is connected to the on / off operation control enhancement type N-channel MOS transistor 16.
Are turned on, the GND level is reached, and the discharge prevention transistor 11 is turned on. In addition, since the transistor 12 is also in a conductive state, the output stage circuit 3 is in a normal active state. At this time, the drain of the depletion-type P-channel MOS transistor 15 for on / off operation control, which is always in a conductive state, is also at the GND level.
Although a current flows through D, there is no problem if the electrical characteristics of the transistor 15 are appropriately selected and the transistor is designed so that only a small current flows. Therefore, output terminal 8
Output a stabilized voltage.

【0018】このように本発明の回路構成が実現できれ
ば、安定化電圧出力端子8に液晶パネル等容量性負荷が
ほとんどを占める負荷が接続されている場合は、負荷電
流が非常に少ないので起動時に所望の電圧を発生させた
後は、出力安定化用コンデンサ10から負荷へ流れたわ
ずかな電荷分を出力電圧の許容される電圧範囲内で補充
できるように上記の電圧変換回路5と電圧安定化回路4
0を間欠動作させることが可能になり、たとえば、電圧
変換回路5及び電圧安定化回路40での消費電流をIo
pr、間欠動作時の動作時間と動作停止時間の割合を
1:9とすると、平均動作電流は1/10に減らすこと
が可能になる。即ち、電圧変換回路5や電圧安定化回路
40の動作停止時に出力安定化用コンデンサ10の負荷
以外への放電経路をなくす回路構成にしダイナミックホ
ールド可能な電圧安定化回路構成にしたので、電圧変換
回路5の昇圧回路動作と電圧安定化回路40の安定化回
路動作が停止して電圧安定化回路に印加される入力電圧
が出力電圧より低下した状態が存在しても出力安定化用
コンデンサ10の電荷が保持でき、特に負荷として液晶
パネル等容量性負荷を接続する場合は、電圧変換回路5
や電圧安定化回路40の間欠動作をさせて無効電流を減
らすことが可能になり、消費電流の低減と入力電圧と出
力電圧間の電圧変換効率を向上させることが可能にな
る。
If the circuit configuration of the present invention can be realized as described above, when a load occupied mostly by a capacitive load such as a liquid crystal panel is connected to the stabilized voltage output terminal 8, since the load current is very small, the start-up time is small. After the desired voltage is generated, the above-described voltage conversion circuit 5 and the voltage stabilizing circuit 5 can replenish a small amount of electric charge flowing from the output stabilizing capacitor 10 to the load within the allowable voltage range of the output voltage. Circuit 4
0 can be intermittently operated. For example, the current consumption of the voltage conversion circuit 5 and the voltage stabilization circuit 40 can be reduced by Io
Assuming that the ratio of pr and the operation time during the intermittent operation to the operation stop time is 1: 9, the average operation current can be reduced to 1/10. That is, the voltage conversion circuit 5 and the voltage stabilization circuit 40 have a circuit configuration that eliminates a discharge path to other than the load of the output stabilizing capacitor 10 when the operation of the voltage stabilization circuit 40 is stopped. 5 and the stabilization circuit operation of the voltage stabilization circuit 40 is stopped, and even if the input voltage applied to the voltage stabilization circuit is lower than the output voltage, the charge of the output stabilization capacitor 10 is present. Especially when a capacitive load such as a liquid crystal panel is connected as the load.
In addition, it is possible to reduce the reactive current by intermittently operating the voltage stabilizing circuit 40, thereby reducing the current consumption and improving the voltage conversion efficiency between the input voltage and the output voltage.

【0019】[0019]

【発明の効果】以上、述べたように本発明によれば、電
圧変換回路と電圧安定化回路の回路動作が停止状態でも
安定化出力用コンデンサに蓄積された電荷の負荷以外へ
の放電経路をなくしたので、特に液晶パネルのような容
量性負荷を接続して使用する場合には電圧変換回路や電
圧安定化回路を間欠動作させることが可能となり、消費
電流の低減、電圧変換効率の向上が図れるなどすぐれた
効果を有するものである。
As described above, according to the present invention, even if the circuit operation of the voltage conversion circuit and the voltage stabilization circuit is stopped, the discharge path of the charge accumulated in the stabilized output capacitor to a path other than the load is established. In particular, when a capacitive load such as a liquid crystal panel is connected and used, the voltage conversion circuit and voltage stabilization circuit can operate intermittently, reducing current consumption and improving voltage conversion efficiency. It has excellent effects such as being able to be achieved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の電圧安定化回路の一実施の形態を示す
回路図。
FIG. 1 is a circuit diagram showing one embodiment of a voltage stabilizing circuit of the present invention.

【図2】従来の電圧安定化回路の回路図。FIG. 2 is a circuit diagram of a conventional voltage stabilizing circuit.

【符号の説明】[Explanation of symbols]

1 基準電圧発生回路 2 オペアンプ差動段回路 3 オペアンプ出力段回路 5 電圧変換回路 6 電源電圧入力端子 7 電圧安定化回路入力電圧印加端子 8 安定化電圧出力端子 9 駆動用MOSトランジスタ 10 出力電圧安定化用コンデンサ 11 放電防止用MOSトランジスタ 12 放電防止用MOSトランジスタ 14 オンオフ動作制御信号入力端子 15 オンオフ動作制御用デプレッション型Pチャネル
MOSトランジスタ 16 オンオフ動作制御用エンハンスメント型Nチャネ
ルMOSトランジスタ 20 オペアンプ位相補償用コンデンサ 21 オンオフ動作制御用エンハンスメント型Pチャネ
ルMOSトランジスタ 22 PチャネルMOSトランジスタ 23 PチャネルMOSトランジスタ 24 NチャネルMOSトランジスタ 25 NチャネルMOSトランジスタ 27 オンオフ動作制御用エンハンスメント型Nチャネ
ルMOSトランジスタ 26 定電流用デプレッション型NチャネルMOSトラ
ンジスタ 33 接地端子 40 電圧安定化回路
REFERENCE SIGNS LIST 1 reference voltage generating circuit 2 operational amplifier differential stage circuit 3 operational amplifier output stage circuit 5 voltage conversion circuit 6 power supply voltage input terminal 7 voltage stabilization circuit input voltage application terminal 8 stabilization voltage output terminal 9 driving MOS transistor 10 output voltage stabilization Capacitor for discharge 11 Discharge prevention MOS transistor 12 Discharge prevention MOS transistor 14 ON / OFF operation control signal input terminal 15 Depletion type P channel MOS transistor for ON / OFF operation control 16 Enhancement type N channel MOS transistor for ON / OFF operation control 20 Operational amplifier phase compensation capacitor 21 ON / OFF operation control enhancement type P channel MOS transistor 22 P channel MOS transistor 23 P channel MOS transistor 24 N channel MOS transistor 25 N channel Le MOS transistor 27 off operation control enhancement type N-channel MOS transistor 26 constant current depletion type N-channel MOS transistor 33 ground terminal 40 voltage stabilizer

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】第1の電源端子に印加される電圧を安定化
して出力端子に出力する電圧安定化回路において、前記
第1の電源端子と前記出力端子との間に、放電防止手段
と駆動用トランジスタとを直列接続してなり、前記放電
防止手段は前記第1の電源端子に印加される電圧が前記
出力端子の電圧よりも低いときに、該出力端子から該第
1の電源端子への電荷の放電を防止してなることを特徴
とする電圧安定化回路。
1. A voltage stabilizing circuit for stabilizing a voltage applied to a first power supply terminal and outputting the voltage to an output terminal, wherein a discharge preventing means and a drive are provided between the first power supply terminal and the output terminal. And the discharge prevention means is connected to the first power supply terminal when the voltage applied to the first power supply terminal is lower than the voltage of the output terminal. A voltage stabilizing circuit characterized by preventing discharge of electric charges.
【請求項2】前記放電防止手段は、第1のトランジスタ
を有し、該第1のトランジスタのドレインには前記第1
の電源端子に印加される電圧が供給され、該第1のトラ
ンジスタのソースが前記駆動用トランジスタのソースに
接続され、該第1のトランジスタのゲートには該第1の
トランジスタのソースの電位と略同一の電位が供給され
てなることを特徴とする請求項1記載の電圧安定化回
路。
2. The discharge prevention means includes a first transistor, and the drain of the first transistor has a first transistor.
Is applied to the power supply terminal of the first transistor, the source of the first transistor is connected to the source of the driving transistor, and the gate of the first transistor has a potential substantially equal to the potential of the source of the first transistor. 2. The voltage stabilizing circuit according to claim 1, wherein the same potential is supplied.
【請求項3】前記第1のトランジスタのゲートとソース
との間に第2のトランジスタを有し、該第2のトランジ
スタのゲートとソースは前記第1のトランジスタのソー
スに接続され、該第2のトランジスタのドレインは前記
第1のトランジスタのゲートに接続されてなることを特
徴とする請求項2記載の電圧安定化回路。
3. A second transistor between a gate and a source of the first transistor, wherein a gate and a source of the second transistor are connected to a source of the first transistor, and the second transistor is connected to a source of the first transistor. 3. The voltage stabilizing circuit according to claim 2, wherein the drain of said transistor is connected to the gate of said first transistor.
【請求項4】基準電圧発生回路と、安定化電圧出力端子
と接地端子間に接続された分圧回路と、基準電圧発生回
路の出力と分圧回路の分圧出力を入力とする差動入力オ
ペアンプ回路と、ゲート電極が差動入力オペアンプ回路
の出力に接続されドレインが安定化電圧出力端子に接続
された駆動用トランジスタとを有する電圧安定化回路で
あって、電圧安定化回路の入力電圧印加端子にドレイン
を接続し前記駆動用トランジスタのソースにソースを接
続した第3のトランジスタと、安定化電圧出力端子と接
地端子との間に前記分圧回路と直列に接続された第4の
トランジスタと、該第4のトランジスタが非導通状態の
ときに、前記第3のトランジスタが非導通となるような
電圧を該第3のトランジスタのゲートに供給してなる手
段とを具備することを特徴とする電圧安定化回路。
4. A reference voltage generating circuit, a voltage dividing circuit connected between a stabilized voltage output terminal and a ground terminal, and a differential input having an output of the reference voltage generating circuit and a divided output of the voltage dividing circuit as inputs. A voltage stabilizing circuit having an operational amplifier circuit and a driving transistor having a gate electrode connected to an output of the differential input operational amplifier circuit and a drain connected to a stabilized voltage output terminal, wherein an input voltage of the voltage stabilizing circuit is applied. A third transistor having a drain connected to a terminal and a source connected to the source of the driving transistor; a fourth transistor connected in series with the voltage dividing circuit between a stabilized voltage output terminal and a ground terminal; Means for supplying a voltage to the gate of the third transistor so that the third transistor becomes non-conductive when the fourth transistor is non-conductive. Voltage stabilizing circuit according to claim.
JP26495496A 1996-10-04 1996-10-04 Voltage stabilization circuit Expired - Fee Related JP3543509B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26495496A JP3543509B2 (en) 1996-10-04 1996-10-04 Voltage stabilization circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26495496A JP3543509B2 (en) 1996-10-04 1996-10-04 Voltage stabilization circuit

Publications (2)

Publication Number Publication Date
JPH10111723A true JPH10111723A (en) 1998-04-28
JP3543509B2 JP3543509B2 (en) 2004-07-14

Family

ID=17410515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26495496A Expired - Fee Related JP3543509B2 (en) 1996-10-04 1996-10-04 Voltage stabilization circuit

Country Status (1)

Country Link
JP (1) JP3543509B2 (en)

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Publication number Priority date Publication date Assignee Title
JP2000039923A (en) * 1998-07-23 2000-02-08 Nec Corp Voltage regulator
WO2003071373A1 (en) * 2002-02-22 2003-08-28 Mitsubishi Denki Kabushiki Kaisha Voltage generation circuit
JP2005165716A (en) * 2003-12-03 2005-06-23 Toshiba Corp Regulator unit and backward flow prevention diode circuit using the same
US7002329B2 (en) 2001-04-10 2006-02-21 Ricoh Company, Ltd. Voltage regulator using two operational amplifiers in current consumption
JP2006228076A (en) * 2005-02-21 2006-08-31 Seiko Instruments Inc Voltage regulator
JP2009301261A (en) * 2008-06-12 2009-12-24 Seiko Epson Corp Load driving circuit and load driving method
JP2013150192A (en) * 2012-01-20 2013-08-01 Denso Corp Operational amplifier and series regulator
JP2019125082A (en) * 2018-01-15 2019-07-25 エイブリック株式会社 Backflow prevention circuit and power supply circuit

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000039923A (en) * 1998-07-23 2000-02-08 Nec Corp Voltage regulator
US7002329B2 (en) 2001-04-10 2006-02-21 Ricoh Company, Ltd. Voltage regulator using two operational amplifiers in current consumption
WO2003071373A1 (en) * 2002-02-22 2003-08-28 Mitsubishi Denki Kabushiki Kaisha Voltage generation circuit
JP2005165716A (en) * 2003-12-03 2005-06-23 Toshiba Corp Regulator unit and backward flow prevention diode circuit using the same
JP2006228076A (en) * 2005-02-21 2006-08-31 Seiko Instruments Inc Voltage regulator
JP2009301261A (en) * 2008-06-12 2009-12-24 Seiko Epson Corp Load driving circuit and load driving method
US8049368B2 (en) 2008-06-12 2011-11-01 Seiko Epson Corporation Load driving circuit and load driving method
US9250641B2 (en) 2008-06-12 2016-02-02 Seiko Epson Corporation Load driving circuit and load driving method
JP2013150192A (en) * 2012-01-20 2013-08-01 Denso Corp Operational amplifier and series regulator
JP2019125082A (en) * 2018-01-15 2019-07-25 エイブリック株式会社 Backflow prevention circuit and power supply circuit

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