JPH1011988A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory which assures lower power consumption and provides a sufficient read margin in the read operation. SOLUTION: At the time of reading data stored in a floating gate FG, the time required from start of impression of a voltage to a control gate CG to actual start of flow of a cell current by a memory cell 101 is counted and the recording data value is judged depending on this counted value. For example, when the recorded time is defined as '0' for under 50ns, '1' for 50ns or more and under 100 ns, '2' for 100ns or more and under 150ns, and '3' for 150ns or more and under 200ns, the recording data can be judged depending on the counted time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor nonvolatile memory, and more particularly, to a method for reading binary or ternary or more information recorded on a floating gate such as a flash EEPROM.

[0002]

2. Description of the Related Art In recent years, FRAM (Ferro-electric Random
Access Memory), EPROM (Erasable and Programma)
Non-volatile semiconductor memories such as a ble read only memory (EEPL) and an EEPROM are receiving attention. EPROM and EEPROM
In the OM, charge is stored in a floating gate, and data is stored by detecting a change in threshold voltage due to the presence or absence of a charge by a control gate. Also, EE
PROMs include a flash EEPROM that erases data in the entire memory chip or divides a memory cell array into arbitrary blocks and erases data in each block unit.

[0003] Memory cells constituting a flash EPROM are roughly classified into a split gate type and a stacked gate type. (Split-gate type) A split-gate type flash EEPROM is disclosed in US Pat. No. 5,029,130 (G11C 11/4).
0).

FIG. 5 shows a cross-sectional structure of a split gate memory cell 101 described in the publication. An N-type source S and a drain D are formed on a P-type single crystal silicon substrate 102. A floating gate FG is formed on a channel CH sandwiched between a source S and a drain D via a first insulating film 103. The control gate CG is formed over the floating gate FG with the second insulating film 104 interposed. A part of the control gate CG is arranged on the channel via the first insulating film 103, and forms a selection gate 105.

FIG. 6 shows a flash EEP using a split gate type memory cell 101 described in the publication.
1 shows the overall configuration of a ROM 121. Memory cell array 12
Reference numeral 2 denotes a configuration in which a plurality of memory cells 101 are arranged on a matrix. The control gates CG of the memory cells 101 arranged in the row direction are connected to common word lines WLa to WLz. The drains D of the memory cells 101 arranged in the column direction are connected to common bit lines BLa to BL. The sources S of all the memory cells 101 are connected to a common source line SL,
The common source line SL is grounded.

Each word line WLa-WLz is connected to a row decoder 123, and each bit line BLa-BLz is connected to a column decoder 124. The row address and column address specified from outside are stored in the address pad 1
25. The row address and the column address are transmitted from the address pad 125 to the address buffer 12.
6 to the address latch 127. Of the addresses latched by the address latch 127, the row address is transferred to the row decoder 123, and the column address is transferred to the column decoder 124. Low deco
The damper 123 selects one word line WLa to WLz corresponding to the row address, and controls the potential of the selected word line corresponding to each operation mode, as described later. The column decoder 124 selects a bit line BLa-BLz corresponding to the column address, and controls the potential of the selected bit line according to each operation mode, as described later.

Externally designated data is input to data pad 128. The data is stored in data pad 1
28 through the input buffer 129, the column decoder 1
24. The column decoder 124 controls the potentials of the bit lines BLa to BLz selected as described above in accordance with the data, as described later. Data read from any memory cell 101 is stored in bit line BLa
ＢＬBLz to the sense amplifier group 130 via the column decoder 124. The sense amplifier group 130 includes several sense amplifiers (not shown). The column decoder 124 is connected to the selected bit lines BLa to BLz.
And each sense amplifier. As will be described later, the data determined by the sense amplifier group 130 is output to the output buffer 13.
1 to the outside via the data pad 128.

The above circuits (123, 124, 12)
6, 127, 129, 130, 131) are controlled by the control core circuit 132. Next, flash E
Each operation mode (erase mode, write mode, read mode) of the EPROM 121 will be described with reference to FIG. 7A. In any of the operation modes, the potential of the common source line SL is maintained at the ground level (= 0 V).

(A) Erase Mode In the erase mode, the potentials of all bit lines BLa to BLz are held at the ground level. 15 V is supplied to the selected word line WLm, and the other word lines (non-selected word lines) WLa to WL1, WLn to WLz
Is set to the ground level. Therefore, each memory cell 101 connected to the selected word line WLm
Control gate CG is raised to 15V.

When the capacitance between the floating gate FG and the drain D is compared with the capacitance between the control gate CG and the floating gate FG, the former is overwhelmingly larger.
Therefore, when the control gate CG is 15 V and the drain is 0 V, a high electric field is generated between the control gate CG and the floating gate FG. As a result, Fowler-Nordheim Tunnel Current (hereinafter, FN)
(Referred to as a tunnel current), and electrons in the floating gate FG are extracted to the control gate CG side, and the memory cell 10
1 is erased.

This erasing operation is performed by selecting the selected word line WL.
This is performed for all the memory cells 101 connected to m. Note that by simultaneously selecting a plurality of word lines WLa to WLz, an erase operation can be performed on all the memory cells 101 connected to each word line. The erasing operation of dividing the memory cell array 122 into arbitrary blocks for each of a plurality of sets of word lines WLa to WLz and erasing data in each block is called block erasing.

(B) Write mode In the write mode, the selected memory cell 101
1V is supplied to the word line WLm connected to the control gate CG, and the potentials of the other word lines (non-selected word lines) WLa to WL1 and WLn to WLz are set to the ground level. 12 V is supplied to the bit line BLm connected to the drain D of the selected memory cell 101, and the other bit lines (unselected bit lines) BLa
To BLl and BLn to BLz are set to the ground level.

The threshold voltage V of the memory cell 101
th is 0.5V. Therefore, in the selected memory cell 101, the control gate CG becomes close to the threshold voltage Vth, and the electrons in the source S move into the weakly inverted channel CH. On the other hand, since 12 V is applied to the drain D, the potential of the floating gate FG is raised by the coupling between the drain D and the floating gate FG via the capacitance. Therefore, a high electric field is generated between the control gate CG and the floating gate FG. Therefore, the electrons in the channel CH are accelerated, become hot electrons, and are injected into the floating gate FG. As a result, charges are accumulated in the floating gate FG of the selected memory cell 101, and 1-bit data is written and stored.

This writing operation is different from the erasing operation.
This can be performed for each selected memory cell 101. (C) Read mode In the read mode, the selected memory cell 101
5V is supplied to the word line WLm connected to the control gate CG, and the potentials of the other word lines (non-selected word lines) WLa to WLl and WLn to WLz are set to the ground level. 2.5 V is supplied to the bit line BLm connected to the drain D of the selected memory cell 101, and the other bit lines (unselected bit lines) BL
a to BLl and BLn to BLz are set to the ground level.

As described above, since electrons are extracted from the floating gate FG of the memory cell 101 in the erased state, the floating gate FG is positively charged. Further, since electrons are injected into the floating gate FG of the memory cell 101 in the written state, the floating gate FG
Is negatively charged. Therefore, the channel CH immediately below the floating gate FG of the memory cell 101 in the erased state is on, and the channel CH immediately below the floating gate FG of the memory cell 101 in the written state is off. Therefore, when 5 V is applied to the control gate CG, the current (cell current) flowing from the drain D to the source S is larger in the erased memory cell 101 than in the written memory cell 101.

By determining the magnitude of the cell current between the memory cells 101 by each sense amplifier in the sense amplifier group 130, the value of the data stored in the memory cell 101 can be read. For example, reading is performed with the data value of the memory cell 101 in the erased state set to “1” and the data value of the memory cell 101 in the written state set to “0”. That is, each memory cell 101 can store two values of the data value “1” in the erased state and the data value “0” in the written state.

This read operation is different from the erase operation.
This can be performed for each selected memory cell 101. Incidentally, in the split gate memory cell 101, a flash EEPROM in which the source S is called a drain and the drain D is called a source is WO92 / 18980.
(G11C 13/00). FIG. 7B shows the potential of each part in each operation mode in that case.

By the way, in recent years, flash EEPROMs
In order to improve the degree of integration, there has been proposed a multi-valued memory that stores not only binary (= 1 bit) of an erased state and a written state but also three or more levels in a memory cell. FIG. 8 shows a split gate memory cell 1
11 shows characteristics of the potential Vfg of the floating gate FG and the cell current value Id at 01. Note that the floating gate potential Vfg is the potential of the floating gate FG with respect to the source S.

In the read mode, the control gate CG
Is applied with a constant voltage (= 5 V), the channel CH immediately below the control gate CG functions as a constant resistance.
Therefore, the split gate memory cell 101 includes a transistor including the floating gate FG, the source S and the drain D, and the channel C directly below the control gate CG.
It can be considered that a constant resistance made of H is connected in series.

Therefore, in the region where the floating gate potential Vfg is less than a certain value (= 3.5 V), the characteristics of the transistor become dominant. Therefore, in a region where the floating gate potential Vfg is lower than the threshold voltage Vth (= 0.5 V) of the memory cell 101, the cell current value Id becomes zero. When the floating gate potential Vfg exceeds the threshold voltage Vth, the cell current value Id shows a characteristic of rising to the right. In the region where the floating gate potential Vfg exceeds 3.5 V, the characteristic of the constant resistance formed by the channel CH immediately below the control gate CG becomes dominant, and the cell current Id is saturated.

The floating gate potential Vfg is the sum of the potential Vfgw generated by the charge stored in the floating gate FG in the write operation and the potential Vfgc generated by the coupling from the drain D (Vfg
= Vfgw + Vfgc). In the read operation, since the potential Vfgc is constant, the cell current value Id becomes the potential Vf
gw. In the write operation, the amount of charge of the floating gate FG can be controlled by adjusting the operation time. Therefore,
In the writing operation, if the potential Vfgw is controlled by adjusting the operation time and controlling the amount of charge of the floating gate FG, the floating gate potential Vfg can be controlled. As a result, the cell current value Id in the read operation can be set arbitrarily.

Therefore, as shown in FIG.
The area where d is less than 40 μA is the data value “11”, 40 μA
The data value “10”, 80 μA
The data value “01”, 120
The area of μA or more is associated with the data value “00”. Then, in the write operation, the floating gate potential Vfg (= Va, Vb, Vc) is changed to the cell current value Id.
(= 40, 80, 120 μA) to adjust the operation time. In this way, four-level (= 2 bits) data can be stored in one memory cell 101.

However, when each value of the data is made to correspond to the cell current value Id, in a region where the change in the cell current value Id is small with respect to the change in the floating gate potential Vfg, the floating gate potential Vfg is changed by the cell current value Id. It is not decided uniquely and multi-value cannot be obtained. That is, in the region where the floating gate potential Vfg is 0.5 to 2.5 V, the change in the cell current value Id is large with respect to the change in the floating gate potential Vfg. Therefore, the floating gate potential Vfg is univocal to the cell current value Id. And a plurality of data values can be made to correspond to the cell current value Id. However, in a region where the floating gate potential Vfg is less than 0.5 V or more than 3.5 V, the cell current value Id does not change with respect to the change in the floating gate potential Vfg. The cell current value Id is not uniquely determined.
Cannot correspond to multiple data values.

As described above, in the flash EEPROM using the split gate type memory cell 101, only a region where the change in the cell current value Id is large with respect to the change in the floating gate potential Vfg can be used in multi-leveling. . (Stacked Gate Type) FIG. 9 shows a sectional structure of a stacked gate type memory cell 201.

An N-type source S is formed on a P-type single crystal silicon substrate.
And a drain D are formed. A floating gate FG is formed on a channel CH interposed between the source S and the drain D via a first insulating film 203. Floating gate F
A control gate CG is formed on G via a second insulating film 204. The floating gate FG and the control gate CG are stacked without shifting from each other. Therefore, the source S and the drain D have a symmetric structure with respect to each of the gates FG and CG and the channel CH.

FIG. 10 shows an overall configuration of a flash EEPROM 221 using the stacked gate type memory cell 201. The flash EEPROM 221 differs from the flash EEPROM 121 using the split gate type memory cell 101 shown in FIG. 6 in the following points.

(1) In the memory cell array 122, a plurality of memory cells 201 are arranged in a matrix. (2) The sources S of the memory cells 201 arranged in the column direction are connected to common bit lines BLa to BLz. (3) The drains D of all the memory cells 201 are connected to a common drain line DL. The common drain line DL is connected to a common drain line bias circuit 222.
The common drain line bias circuit 222 controls the potential of the common drain line DL according to each operation mode, as described later. The operation of the common drain line bias circuit 222 is controlled by the control core circuit 132.

In this specification, the names of the source S and the drain D in the split gate memory cell 101 and the stacked gate memory cell 201 are determined based on the read operation, and the higher potential in the read operation is determined by the drain. , The lower potential is referred to as the source. In the writing operation and the erasing operation, the names of the source S and the drain D are the same as those in the reading operation.

Next, each operation mode (erase mode, write mode, read mode) of the flash EEPROM 221 will be described with reference to FIG. (A) Erasing Mode In the erasing mode, all the bit lines BLa to BLz are set to the open state, and the potentials of all the word lines WLm are set to the ground level. Common drain line bias circuit 2
Reference numeral 22 applies 12 V to the drains D of all the memory cells 201 via the common drain line DL.

As a result, an FN tunnel current flows, electrons in the floating gate FG are drawn to the drain D side, and data written in the memory cell 201 is erased.
This erase operation is performed on all the memory cells 201 connected to the selected word line WLm. still,
By simultaneously selecting a plurality of word lines WLa to WLz, an erasing operation (block erasing) can be performed on all the memory cells 201 connected to each word line.

(B) Write Mode In the write mode, the selected memory cell 201
12V is supplied to the word line WLm connected to the control gate CG, and the potentials of the other word lines (non-selected word lines) WLa to WL1 and WLn to WLz are set to the ground level. 5 V is supplied to the bit line BLm connected to the source S of the selected memory cell 201, and the other bit lines (unselected bit lines) BLa to
The potentials of BL1, BLn to BLz are set to the ground level. The common drain line bias circuit 222 holds the drains D of all the memory cells 201 at the ground level via the common drain line DL.

Then, the potential of the floating gate FG is raised by the coupling from the control gate CG, and hot electrons generated near the source S are injected into the floating gate FG. As a result, the selected memory cell 2
In the floating gate FG 01, charges are accumulated, and 1-bit data is written and stored. (C) Read mode In the read mode, the selected memory cell 201
5V is supplied to the word line WLm connected to the control gate CG, and the potentials of the other word lines (non-selected word lines) WLa to WLl and WLn to WLz are set to the ground level. The potentials of all bit lines BLa to BLz are set to the ground level. The common drain line bias circuit 222 applies 5 V to the drains D of all the memory cells 201 via the common drain line DL.

As a result, similarly to the case of the split gate memory cell 101, the current (cell current) flowing from the drain D to the source S is larger in the erased memory cell 201 than in the written memory cell 201. Become. Therefore, each memory cell 201 can store two values of the data value “1” in the erased state and the data value “0” in the written state.

Incidentally, a multi-valued memory has also been proposed for a flash EEPROM using the stacked gate type memory cell 201. FIG. 12 shows characteristics of the potential Vfg of the floating gate FG and the cell current value Id in the stacked gate memory cell 201. Note that the floating gate potential Vf
g is the potential of the floating gate FG with respect to the source S.

In the stacked gate type memory cell 201, since the floating gate FG and the control gate CG are stacked without being shifted from each other, the channel CH just below the control gate CG like the split gate type memory cell 101 is provided. Does not function as a constant resistor but has only the function of a transistor. Therefore, in a region where the floating gate potential Vfg is lower than the threshold voltage Vth (= 1 V) of the memory cell 201, the cell current value Id becomes zero. When the floating gate potential Vfg exceeds the threshold voltage Vth, the cell current value Id
Increases in proportion to the floating gate potential Vfg.

Therefore, the stacked gate type memory cell 2
01, the potential Vf is controlled by adjusting the operation time of the write operation to control the amount of charge of the floating gate FG.
By controlling gw, the floating gate potential Vfg can be controlled. As a result, the cell current value Id in the read operation can be set arbitrarily. Therefore, FIG.
As shown in the figure, the area where the cell current value Id is less than 40 μA is the data value “11”, the area where the cell current value is 40 μA or more and less than 80 μA is the data value “10”, and the area where the cell current value Id is 80 μA or more and less than 120 μA is the data value “01” or 120 μA or more. The areas less than are associated with the data value “00”. Then, in the write operation, the floating gate potential Vfg (=
Va, Vb, Vc, Vd) correspond to the respective cell current values Id (=
(40, 80, 120, 160 μA). In this way, four-level (= 2 bits) data can be stored in one memory cell 201.

However, in the stacked gate type memory cell 201, when an electric charge is excessively extracted from the floating gate FG in the erasing operation, a predetermined voltage (= 0V) for turning off the memory 201 is set. ) Is applied to the control gate CG, the channel CH is turned on. As a result, the memory cell 201 is always turned on, a cell current flows even in a standby state in which each operation mode (erase mode, write mode, read mode) is not performed, and correct data of a memory cell sharing a bit line is provided. A problem of so-called over-erasing occurs in which all values cannot be read. Therefore, it is not desirable to use the over-erased area for storing data.

In the read operation, the floating gate FG
Is determined by the sum of a potential Vfgc generated by coupling with the control gate CG and a potential Vfgw generated by charges accumulated in the floating gate FG (Vfg = Vfgc + Vfgw). That is, in the read operation, the potential of the floating gate FG is raised to 5 V by the coupling from the control gate CG (V
fgc = 5V), the floating gate potential Vfg to Vfg
c is greater than the threshold voltage Vth (V
fg−Vfgc = Vfgw> Vth) is excessively erased. That is, when Vfgc is 5 V, the floating gate potential Vf
A region where g is 6 V or more is excessively erased.

When each value of the data is made to correspond to the cell current value Id, in a region where the change in the cell current value Id is small with respect to the change in the floating gate potential Vfg, the floating gate potential Vfg is changed by the cell current value Id. It cannot be determined uniquely and cannot be multi-valued. That is, the floating gate potential Vfg
Is less than 1 V, the floating gate potential Vfg is not uniquely determined with respect to the cell current value Id because the cell current value Id does not change much to the change in the floating gate potential Vfg. Data values cannot be matched.

As described above, in the flash EEPROM using the stacked gate type memory cell 201, when multi-leveling is performed, an area where the change in the cell current value Id is large due to the change in the floating gate potential Vfg and the excessive erasing is performed. Only areas that are not available can be used.

[0041]

In order to increase the degree of integration of memory elements per unit area, multi-leveling is one of the powerful means, and has been receiving attention in recent years. Flash EEP
When reading the multi-valued cell data, the ROM compares the reference current value with the cell current of the read cell to determine the data value (0, 1, 2, 3, etc.) recorded in the memory cell.

However, it is necessary to keep the current of about 100 μA per cell while determining the recording data value by comparing the reference current with the cell current. I can't escape. Also, as the number of memory cells increases, the number of reference current values for comparison with each recorded value must be increased, and the number of comparisons with the reference current value increases. There is a problem that the read time per unit becomes long and it is not possible to cope with high speed.

On the other hand, in order to accurately and stably perform data writing and reading, in order to prevent erroneous writing and erroneous reading, the range of the floating gate potential Vfg corresponding to each multi-valued data value, and the cell current value It is desirable to provide a sufficient margin (wide allowable range) in the range of Id. However, as described above, the conventional flash EEPR
The OM can use only a region where the change in the cell current value Id is large with respect to the change in the floating gate potential Vfg when multi-valued. Therefore, it is difficult to secure a sufficient margin in the range of the floating gate potential Vfg and the cell current value Id corresponding to each multi-valued data value.

For example, in the split gate memory cell 101 shown in FIG. 8, the range of the cell current value Id corresponding to each data value is 40 μA, and the range of the floating gate potential Vfg corresponding to the data value “10” is 0. .5 V, the range of the floating gate potential Vfg corresponding to the data value “01” is 1 V
It is. In the stacked gate memory cell 201 shown in FIG. 12, the cell current value Id corresponding to each data value
Is 40 μA, and the range of the floating gate potential Vfg is 1.25 V.

As described above, when the range of the floating gate potential Vfg corresponding to each data value is narrow, the margin in the write operation is small, and it becomes difficult to set the floating gate potential Vfg accurately within the allowable range, and the read operation is performed. In operation, erroneous reading is likely to occur due to a small margin. This problem becomes more conspicuous as multi-valued data is advanced. In the case of 8-valued or 16-valued data, the range of the floating gate potential Vfg corresponding to each multi-valued data value and the cell current value Id are smaller than those of 4-valued data. As the range becomes narrower, it becomes more difficult to secure a margin for the write / read operation.

On the other hand, if the power supply voltage is increased only for the purpose of securing the margin, the upper limit of Vfg is increased, and the upper limit of the cell current value is increased, the sense amplifier can be supplied while reading more current. In this case, the data value of the cell is detected, which further promotes the above-described problem of increase in power consumption. The present invention has been made to solve the above problems, and an object of the present invention is to provide a nonvolatile semiconductor memory which consumes less power and can secure a sufficient read margin in a read operation. Is to do.

[0047]

According to the first aspect of the present invention, a floating gate and a control gate are provided.
And a memory cell including a source S, a drain D, and a channel CH. When reading data recorded in the floating gate FG, after starting to apply a voltage to the control gate CG, the memory cell The time required until the cell current actually starts to flow is counted, and the recording data value is determined based on the magnitude of the counted value.

That is, in the data reading, the time required from when the voltage starts to be applied to the floating gate FG to when the potential of the floating gate rises and the read memory cell actually starts flowing the cell current is counted. For example, when the recorded time is less than 50 ns, “0”, 5
"1" for 0 ns or more and less than 100 ns, 1 for 100 ns or more
If “2” is less than 50 ns and “3” is 150 ns or more and less than 200 ns, the recording data can be determined based on the magnitude of the counted time.

In the nonvolatile semiconductor memory according to the second aspect, the floating gate FG, the control gate CG, and the source S
When reading data recorded in the floating gate FG, a voltage is applied to the control gate CG of the reference cell, and the reference cell generates a cell current. The time from when the memory cell starts flowing to when the memory cell starts flowing the cell current is counted, and the recording data value is determined based on the magnitude of the counted value.

That is, in the data reading, the potential of the floating gate FG of the reference cell rises after the voltage starts to be applied to the floating gate FG, and the reference cell and the control gate CG start to flow after the reference cell starts flowing the cell current. The time until the memory cell to be shared starts to flow the cell current is counted.
This makes it possible to effectively exclude a time variation required for channel generation due to process variations such as gate processing from data detection errors.

The counted value is, for example, 50 ns.
Less than 0, 50 ns or more and less than 100 ns, 1, 100 n
s or more and less than 150 ns, 2, 150 ns or more, 200 n
If less than s is set to 3, the recording data value can be determined based on the magnitude of the counted time. In the nonvolatile semiconductor memory according to the third aspect, the floating gate FG
By controlling the amount of charge stored in the memory cell, multi-value data is recorded in the memory cell, and when reading data, a voltage is applied to the control gate CG with a constant current power supply, Floating gate FG by coupling
To control the potential Vfg.

That is, in the read mode, the amount of current flowing from the constant current power supply to the control gate CG is adjusted so that the potential rise rate of the control gate CG per time is reduced. In addition, in the nonvolatile semiconductor memory according to the fourth aspect, by controlling the amount of charge stored in the floating gate FG, multi-level data is recorded in the memory cell. A voltage is applied to the control gate CG through a circuit having a large time constant, and the potential Vfg of the floating gate FG is controlled by coupling from the control gate CG.

That is, in the read mode, by applying a voltage through a circuit having a large resistance and a time constant of about 1000 ns or more, control is performed such that the potential rise rate per unit time of the control gate CG is reduced. I do. According to a fifth aspect of the present invention, in the nonvolatile semiconductor memory according to the third or fourth aspect, a constant current source is used instead of applying a voltage to the control gate CG with a time constant current power supply. A voltage is applied to the drain D or the source S, and the potential Vfg of the floating gate FG is controlled by coupling from the drain D or the source S.

According to a sixth aspect of the present invention, there is provided the nonvolatile semiconductor memory according to the third or fourth aspect, wherein the control gate is connected through a circuit having a large time constant.
Instead of applying a voltage to G, a voltage is applied to the drain D or the source S through a circuit having a large time constant, and the potential Vfg of the floating gate FG is controlled by coupling from the drain D or the source S. .

In the nonvolatile semiconductor memory according to the present invention, a time counter for counting time by a clock is provided. Further, in the nonvolatile semiconductor memory according to the present invention, a control circuit for determining a recording data value based on the magnitude of the counting time is provided.

[0056]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) A first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a flash EEP using the split gate memory cell 101 of the present embodiment.
1 shows the overall configuration of a ROM. In this embodiment, one memory cell 101 can store data of four values (= 2 bits) or more.

In FIG. 1, a flash EEPROM 1
However, the difference from the conventional flash EEPROM 121 shown in FIG. Erase mode
There is no difference between the conventional example and the part relating to the write and write modes. (1) In the read mode, when a voltage is applied to the drain D by the column decoder, it is performed using the constant current power supply 2. In other modes, the constant current power supply 2 is bypassed to apply a voltage.

(2) In the read mode, the time counter 3 is used as an output buffer. In this method, a counter of 2 bits or more is provided for each bit line, and the time difference between the time when a voltage is applied by the common clock 4 and the time when the read memory cell starts flowing current is counted. The cross-sectional structure of the split gate memory cell according to the present embodiment is the same as that shown in FIG. When reading,
The constant current source 2 is connected to the drain D, and the potential of the drain D is increased with time. At this time, the potential Vfg of the floating gate FG also increases with time due to coupling from the drain D. When the potential Vfg of the floating gate exceeds the threshold voltage Vth of the memory cell, a channel CH is generated below the floating gate, and a cell current starts flowing.

In this embodiment, the capacitance Ccf between the control gate CG and the floating gate FG is equal to the drain D and the floating gate F
Since the capacitance is very small as compared with the capacitance between G and the capacitance between the floating gate FG and the substrate, this will be ignored and the description will be continued below. Drain D and floating gate F of read memory cell
C, the capacitance between the floating gate FG and the substrate (immediately before channel generation) is Cfs, and the drain D
As a result, the positive charges accumulated in the capacitors Cdf and Cfs are Qdf and Qfs, respectively, the potential of the drain D is Vd, the potential of the floating gate is Vfg, and the potential difference between the floating gate and the substrate is Vfs. Floating gate FG
Is generated when the potential Vfg becomes equal to Vth as shown in the following equation (1).

Vfg = Vth = Vfs = Vd−Vdf (1) In the present invention, the time t required for this is measured to determine the written data value. That is, when a channel is generated in a state where electrons (negative charges) -Qw are accumulated in the floating gate FG by writing data, Vdf = (Qw + Qdf) / Cdf Vfs = Vth = Vfg = Qfs / Cfs Qdf = Qfs Therefore, Vd = Vdf + Vth = (Qw + Qdf) / Cdf + Q
fs / Cfs, and channel generation does not occur unless a potential larger by Qw / Cdf is applied to the control gate CG than in the case where no charge is accumulated in the floating gate CG, and it takes time to generate a channel accordingly. Therefore, the constant current power supply 2 is used,
If a positive charge is applied to the drain D in proportion to time and the potential of the control gate CG is increased, the amount of electrons accumulated by data writing is uniquely detected by the time required for channel generation.

For example, when discriminating quaternary data, "00" is used when time t <a, "01" when a <t <b, "10" when b <t <c, t > B is defined in advance as “11” (a <b <c <d), and the control core circuit 132 compares and determines. (Second Embodiment) A second embodiment of the present invention will be described with reference to the drawings.

The present embodiment differs from the first embodiment in the following points relating to reading. Other parts are the same as in the first embodiment. (1) In the read mode, the column decoder 124
When a voltage is applied to the drain D by using a normal constant voltage power supply 6 through a circuit 5 having a large time constant as shown in FIG. In other modes, the circuit 5 having a large time constant is bypassed and voltage is applied.

That is, if the output voltage of the constant voltage power supply is V ₀ and the time constant of the circuit 5 is τ,
The drain voltage Vd is Vcg = V ₀ [1-exp (−t / τ)] (where τ is a time constant, t is time, and V ₀ is a power supply voltage).
The circuit 5 having a large time constant includes a large resistance R and a large capacitance C, and the time constant is 1000 ns or more. As described above, when a voltage is applied to the drain D through a circuit having a large time constant, a voltage rise per unit time can be reduced, and a gradually larger voltage is applied to the drain D as time passes. Circuit 5 with a large time constant as described above
Can reduce the rate of voltage rise of the drain D per time. In this case, as in the first embodiment, the more electrons accumulated in the floating gate by data writing,
It takes a long time for the read memory cell to reach the threshold voltage, and the written data value can be determined by counting this time. (Third Embodiment) A third embodiment of the present invention will be described below.

The second embodiment differs from the first embodiment in the following points relating to reading. Other parts are the same as in the first embodiment. (1) In the read mode, the time counter 3 serving as an output buffer is provided with a counter of 2 bits or more for the number of cells to be read at the same time. The time difference between the time when a voltage is applied to the drain D and the time when the read memory cell starts flowing current is counted.

Therefore, it is sufficient to prepare the number of counters by the number of data input / output lines, and it is not necessary to attach counters to all the bit lines, so that the circuit can be omitted and the size can be reduced. (Fourth Embodiment) A fourth embodiment of the present invention will be described with reference to the drawings. The second embodiment differs from the first embodiment in the following points related to reading. Other parts are the same as in the first embodiment.

(1) In FIG. 1, for each word line,
Reference cells REFa to REFz for detecting reference signals
Are provided one by one. For example, cells connected to the bit line BLz are referred to as reference cells REFa to REFz. The time counter 5 counts the time difference from the time when the cell starts flowing the cell current to the time when the read memory cell starts flowing the cell current, using the clock 4 signal.

As a result, in data reading, a voltage is applied to the floating gate FG due to the coupling from the drain D, the potential of the floating gate FG of the reference cell rises, and the reference cell starts flowing a cell current. The counting by the clock is started by the signal, the counting by the clock is stopped by the signal that makes the reference memory cell and the control gate CG common and the read memory cell starts to flow the cell current, and the two kinds of time differences are measured and recorded. In this way, even if there is a process variation such as a gate process, a time variation required for channel generation due to the process variation can be effectively excluded from the data detection error. (Fifth Embodiment) A fifth embodiment of the present invention will be described with reference to the drawings.

FIG. 3 shows the overall configuration of a flash EEPROM using the stacked gate type memory cell 201 of this embodiment. In this embodiment, one memory cell 201 can store data of four values (= 2 bits) or more. In FIG. 3, a flash EEPROM
2 is a conventional flash EEPROM 221 shown in FIG.
The following points are different from those in reading. The parts relating to the erase mode and the write mode are the same as in the conventional example.

(1) When a voltage is applied to the control gate by the row decoder 123 in the read mode, the constant current power supply 2 is used. In other modes, the constant current power supply 2 is bypassed to apply a voltage. (2) In the read mode, the time counter 3 is used as an output buffer. In this method, a counter of 2 bits or more is provided for each bit line, and the time difference between the time when a voltage is applied by the common clock 4 and the time when the read memory cell starts flowing current is counted.

The sectional structure of the stacked gate type memory cell in this embodiment is the same as that shown in FIG.
At the time of reading, a constant current power supply 151 is connected to the control gate CG, and the potential of the control gate CG is increased with time. At this time, the potential Vfg of the floating gate FG also increases with time due to coupling from the control gate CG.
When the potential Vfg of the floating gate exceeds the threshold voltage Vth of the memory cell 201, a channel CH is generated, and a cell current starts flowing.

The capacitance between the control gate CG and the floating gate FG of the read memory cell is Ccf, and the capacitance between the floating gate FG and the substrate (immediately before channel generation) is Cfs.
By coupling with the control gate CG, the capacitance Cc
The positive charges accumulated in ffs and Cfs are Qcf and Qf, respectively.
s, the potential of the control gate is Vcg, the potential of the floating gate is Vfg, and the potential difference between the control gate and the floating gate is Vc.
f, if the potential difference between the floating gate and the substrate is Vfs, the potential Vfg of the floating gate FG becomes Vfg as in the following equation (2).
When equal to th, a channel is created.

Vfg = Vth = Vfs = Vcg−Vcf (2) In the present invention, the time t required for this is measured to determine the written data value. That is, when a channel is generated in a state where electrons (negative charges) -Qw are accumulated in the floating gate CG by writing data, Vcf = (Qw + Qcf) / Ccf Vfs = Vth = Vfg = Qfs / Cfs Qcf = Qfs Therefore, VCG = Vcf + Vth = (Qw + Qcf) / Ccf +
Qfs / Cfs, and channel generation does not occur unless a potential larger by Qw / Ccf is applied to the control gate CG than in the case where no charge is stored in the floating gate CG, and it takes time to generate a channel accordingly. Therefore, the constant current power supply 2 is used,
When a positive charge is applied to the control gate CG in proportion to time and the potential of the control gate CG is increased, the amount of electrons accumulated by data writing is uniquely detected by the time required for channel generation.

For example, when quaternary data is determined, "00" is used for time t <a, "01" is used for a <t <b, "10" is used for b <t <c, t > B is defined in advance as “11” (a <b <c <d), and the control core circuit 132 compares and determines. (Sixth Embodiment) A sixth embodiment of the present invention will be described with reference to the drawings.

This embodiment is different from the fifth embodiment in the following points relating to reading. Other parts are the same as in the fifth embodiment. (1) In the read mode, when a voltage is applied to the control gate FG by the row decoder 123, a normal constant voltage power supply 6 is used through the circuit 5 having a large time constant shown in FIG. In other modes, the circuit 5 having a large time constant is bypassed and voltage is applied.

That is, if the output voltage of the constant voltage power supply is V ₀ and the time constant of the circuit 5 is τ, the control gate voltage Vcg in the read mode is Vcg = V ₀ [1-exp (−t / τ)] ( τ is a time constant, t is time, and V ₀ is a power supply voltage).
The circuit 5 having a large time constant includes a large resistance R and a large capacitance C, and the time constant is 1000 ns or more. As described above, when a voltage is applied to the drain D through a circuit having a large time constant, a voltage rise per unit time can be reduced, and a gradually larger voltage is applied to the drain D as time passes. Circuit 5 with a large time constant as described above
Is used, the rate of voltage rise of the drain D per time can be reduced. In this case, as in the fifth embodiment, as the number of electrons accumulated in the floating gate by data writing increases,
It takes a long time for the read memory cell to reach the threshold voltage, and the written data value can be determined by counting this time. (Seventh Embodiment) A seventh embodiment of the present invention will be described below.

The present embodiment differs from the fifth embodiment in the following points relating to reading. Other parts are the same as in the fifth embodiment. (1) In the read mode, the time counter 3 serving as an output buffer is provided with a counter of 2 bits or more corresponding to the number of cells to be read at the same time. The time difference between the time when the voltage is applied to the control gate CG and the time when the read memory cell starts flowing current is counted.

Accordingly, it is sufficient to prepare the number of counters by the number of data input / output lines, and it is not necessary to attach counters to all the bit lines, so that the circuit can be omitted and the scale can be reduced. (Eighth Embodiment) An eighth embodiment of the present invention will be described with reference to the drawings. The present embodiment differs from the fifth embodiment in the following points relating to reading. Other parts are the same as in the fifth embodiment.

(1) In FIG. 3, for each word line,
Reference cells REFa to REFz for detecting reference signals
Are provided one by one. For example, cells connected to the bit line BLz are referred to as reference cells REFa to REFz. The time counter 5 counts the time difference from the time when the cell starts flowing the cell current to the time when the read memory cell starts flowing the cell current, using the clock 4 signal.

In this case, data is read out from the floating gate FG by coupling from the control gate CG.
, The potential of the floating gate FG of the reference cell rises, the reference cell starts counting by a clock with a signal that starts flowing the cell current, and makes the reference cell and the control gate CG common. The counting by the clock is stopped by the signal at which the cell starts to flow the cell current, and the two types of time differences are measured and recorded. In this way, even if there is a process variation such as a gate process, a time variation required for channel generation due to the process variation can be effectively excluded from the data detection error.

[0080]

According to the nonvolatile semiconductor memory of the present invention, it is possible to secure a sufficient read margin in the operation of reading data from a memory cell storing multi-valued data of two or more values. Since it is possible, data can be read accurately.

Further, since multi-value data can be determined with almost no cell current flowing, a nonvolatile semiconductor memory with low power consumption can be supplied. In addition, since the power consumption is low, a large number of cells can be read at a time, and the data reading speed can be improved.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a flash EEPROM using a split gate memory cell according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a circuit having a large time constant and a constant voltage power supply.

FIG. 3 is an overall configuration diagram of a flash EEPROM using stacked gate memory cells according to an embodiment of the present invention.

FIG. 4 is a diagram showing a circuit having a large time constant and a constant voltage power supply.

FIG. 5 is a cross-sectional structure of a split gate memory cell.

FIG. 6 is an overall configuration diagram of a flash EEPROM using a conventional split gate type memory cell.

FIG. 7 is an explanatory diagram of each operation mode in a conventional flash EEPROM.

FIG. 8 is a diagram showing characteristics of a potential Vfg of a floating gate FG and a cell current value Id in a split gate type memory cell.

FIG. 9 is a diagram showing a cross-sectional structure of a stacked gate memory cell.

FIG. 10 is an overall configuration diagram of a flash EEPROM using a conventional stacked gate type memory cell.

FIG. 11 is an explanatory diagram of each operation mode in a conventional flash EEPROM.

FIG. 12 is a diagram showing characteristics of a potential Vfg of a floating gate FG and a cell current value Id in a stacked gate memory cell.

[Explanation of symbols]

 2 constant current power supply 3 hour counter 4 clock 5 circuit with large time constant 6 constant voltage power supply 101, 201 memory cell 132 control core circuit

Claims (8)

[Claims] In a nonvolatile semiconductor memory having a memory cell including a floating gate FG, a control gate CG, a source S, a drain D, and a channel CH, when reading data recorded in the floating gate FG,
A nonvolatile memory characterized in that a time required for the memory cell to actually start flowing a cell current after a voltage is applied to the control gate CG is counted, and a recording data value is determined based on a magnitude of the counted value. Semiconductor memory. 2. In a nonvolatile semiconductor memory having a memory cell including a floating gate FG, a control gate CG, a source S, a drain D, and a channel CH, when reading data recorded in the floating gate FG,
A voltage is applied to the control gate CG of the reference cell, the time from when the reference cell starts flowing the cell current to when the memory cell starts flowing the cell current is counted, and the recording data value is determined based on the magnitude of the count value. A nonvolatile semiconductor memory characterized by the above-mentioned. 3. The non-volatile semiconductor memory according to claim 1, wherein multi-level data is recorded in said memory cell by controlling an amount of charge stored in said floating gate FG, and data is read. In this case, a voltage is applied to the control gate CG by a constant current power supply, and the potential Vfg of the floating gate FG is controlled by coupling from the control gate CG. 4. The non-volatile semiconductor memory according to claim 1, wherein multi-level data is recorded in said memory cell by controlling an amount of charge stored in said floating gate FG, and data is read. In this case, a voltage is applied to the control gate CG through a circuit having a large time constant, and the potential Vfg of the floating gate FG is controlled by coupling from the control gate CG. 5. The nonvolatile semiconductor memory according to claim 3, wherein a voltage is applied to the drain D or the source S with a constant current source instead of applying a voltage to the control gate CG with a constant current power supply. A non-volatile semiconductor memory, wherein the potential Vfg of the floating gate FG is controlled by coupling from the drain D or the source S. 6. The nonvolatile semiconductor memory according to claim 3, wherein a voltage is applied to the control gate CG through a circuit having a large time constant, instead of applying a voltage to the control gate CG through a circuit having a large time constant. Apply voltage,
A nonvolatile semiconductor memory in which the potential Vfg of a floating gate FG is controlled by coupling from a drain D or a source S. 7. The nonvolatile semiconductor memory according to claim 1, further comprising a time counter for counting time by a clock. 8. The nonvolatile semiconductor memory according to claim 1, further comprising a control circuit for determining a recording data value based on a count time.