JPH0399470A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0399470A JPH0399470A JP23627089A JP23627089A JPH0399470A JP H0399470 A JPH0399470 A JP H0399470A JP 23627089 A JP23627089 A JP 23627089A JP 23627089 A JP23627089 A JP 23627089A JP H0399470 A JPH0399470 A JP H0399470A
- Authority
- JP
- Japan
- Prior art keywords
- via hole
- plating layer
- layer
- forming
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 238000007747 plating Methods 0.000 claims abstract description 66
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims description 51
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 26
- 239000010931 gold Substances 0.000 claims description 26
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 14
- 229910052737 gold Inorganic materials 0.000 claims description 14
- 229910052759 nickel Inorganic materials 0.000 claims description 12
- 239000012212 insulator Substances 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 10
- 239000003638 chemical reducing agent Substances 0.000 abstract description 3
- 238000005498 polishing Methods 0.000 abstract description 3
- 238000006722 reduction reaction Methods 0.000 abstract description 3
- 239000003054 catalyst Substances 0.000 abstract description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 8
- 230000004913 activation Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000000968 intestinal effect Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
- Chemically Coating (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置の製造方法に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.
第５図（ａ）乃至（ｄ）は従来の高周波・高出力ＧａＡ
ｓＩＣの製造方法の主要工程を示す断面図である。同図
において、（１）はＧａＡｓ基板、（３１）はバイアホ
ール、 （３２）はバイアホール（３１）の内部金属層
、（３３）はメッキ下地蒸着金属層、（３４）は放熱体
としてのプレーテッド・ヒート・シンク（以下ＰＨ９と
称する）である。Figures 5(a) to 5(d) show conventional high-frequency, high-power GaA
FIG. 3 is a cross-sectional view showing the main steps of the sIC manufacturing method. In the figure, (1) is a GaAs substrate, (31) is a via hole, (32) is an internal metal layer of the via hole (31), (33) is a vapor-deposited metal layer under plating, and (34) is a heat sink. It is a plated heat sink (hereinafter referred to as PH9).
第５図（ａ）に示すように、ＧａＡｓ基板（１）の第１
の面（表面）に深さ約３０＃Ｌｍのバイアホール（３１
）をＲＩＥ法等で形成し、そのバイアホール内部に電解
メッキで金属層（３２）を形成する。この後、ＧａＡｓ
基板（１）の第１の面とは反対側の第２の面（裏面）か
ら研削、ラッピング、ポリッシング等により基板（１）
の厚さを約３０μ−にまで均一に薄化して、バイアホー
ル内部金属層（３２）の底部を第５図（ｂ）に示すよう
に、第２の面に露出せしめ、次に、第２の面金面に第５
図（Ｃ）に示すように、メッキ下地蒸着金属層（３３）
を形成する。続いて、そのメッキ下地蒸着金属層（３３
）をカソード給電層とした電解メッキにより約４０１Ｌ
Ｉｌ厚さのＰＨ９（３４）を形成する。As shown in FIG. 5(a), the first layer of the GaAs substrate (1)
A via hole (31
) is formed by RIE method or the like, and a metal layer (32) is formed inside the via hole by electrolytic plating. After this, GaAs
The substrate (1) is ground by grinding, lapping, polishing, etc. from the second surface (back surface) opposite to the first surface of the substrate (1).
The thickness of the metal layer (32) inside the via hole is uniformly reduced to about 30 μ- to expose the bottom of the metal layer (32) inside the via hole on the second surface as shown in FIG. 5(b). 5th on the face of
As shown in Figure (C), plating base vapor deposited metal layer (33)
form. Subsequently, the plating base vapor-deposited metal layer (33
) as the cathode power supply layer, approximately 401L
A PH9 (34) having a thickness of Il is formed.
以上のようにして製造した半導体装置では、ＧａＡｓ基
板（１）の第１の面に形成されたＦＥＴ等の素子からの
熱はバイアホール（３１）及び薄化された熱伝導率の低
いＧａＡｓ基板（１）を介してその基板の第２の面側の
ＰＨ９（３４）へ放散される。In the semiconductor device manufactured as described above, heat from elements such as FETs formed on the first surface of the GaAs substrate (1) is transferred to the via hole (31) and the thinned GaAs substrate with low thermal conductivity. (1) to the PH9 (34) on the second surface side of the substrate.
上述の従来の製造方法では、基板厚さを基板全体にわた
って約３０１Ｌｍにまで均一に薄くし、且つ基板の第２
の面上に約４０１Ｌｍ厚さのＰＨ８を形成するため、メ
ッキ応力により第６図（ａ）に示すように基板（１）が
反り、その反り量ｈ（ｍ■）は第６図（ｂ）に示すよう
に基板寸法（長辺の長さ）ＪＬ＝２Ｒθ（ａｍ）が増す
に従って増加する傾向にあった。In the conventional manufacturing method described above, the substrate thickness is uniformly reduced to about 301 Lm over the entire substrate, and the second
In order to form PH8 with a thickness of about 401 Lm on the surface, the substrate (1) is warped due to plating stress as shown in Figure 6 (a), and the amount of warp h (m) is as shown in Figure 6 (b). As shown in the figure, there was a tendency to increase as the substrate dimension (length of the long side) JL=2Rθ (am) increased.
なお、Ｒは中心位置から基板までの距離、θは中心位置
から基板両端を見た角の半角である。基板反り量りが０
．１腸層を超えると、アッセンブリが困難になるため、
基板寸法文をあまり大きくすることができず、その寸法
文を約３．５ｍ■以下にしなければならないという問題
点があった。Note that R is the distance from the center position to the substrate, and θ is the half angle of the angle seen from the center position to both ends of the substrate. Board warpage amount is 0
．． If it exceeds one intestinal layer, assembly becomes difficult.
There was a problem in that the dimensions of the board could not be made very large, and the dimensions had to be about 3.5 m or less.
この発明は、上記のような問題点を解決するためになさ
れたもので、ＮＥＴ等の発熱部からＰＨ５への放熱効果
を損なうことなく、基板反り量を低減させ、且つ基板寸
法を大°きくすることができる半導体装置の製造方法を
提供することを目的とする。This invention was made to solve the above-mentioned problems, and it reduces the amount of board warpage and increases the board size without impairing the heat dissipation effect from the heat generating part of the NET etc. to the PH5. An object of the present invention is to provide a method for manufacturing a semiconductor device that can perform the following steps.
この発明に係る半導体装置の製造方法は、半導体基板の
第１の面から第１のバイアホールを形成し、その後、そ
の半導体基板の第１の面の反対側に在る第２の面から第
２のバイアホールを形成して第１のバイアホール底部を
覆う金属層を第２のバイアホール内に露出させ、その後
、その第２のバイアホールの内部に無電解メッキあるい
は電解メッキによりメッキ層を充填するようにしたもの
である。A method for manufacturing a semiconductor device according to the present invention includes forming a first via hole from a first surface of a semiconductor substrate, and then forming a first via hole from a second surface opposite to the first surface of the semiconductor substrate. A second via hole is formed to expose the metal layer covering the bottom of the first via hole into the second via hole, and then a plating layer is formed inside the second via hole by electroless plating or electrolytic plating. It is designed to be filled.
この発明では、第２のバイアホールを形成しその内部に
メッキ層を充填することによって、半導体基板の所要の
部分にのみ選択的に放熱体を形成する。In this invention, a heat sink is selectively formed only in a required portion of a semiconductor substrate by forming a second via hole and filling the inside with a plating layer.
以下、この発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図（ａ）乃至（ｄ）はこの発明の第１の実施例によ
る半導体装置の製造方法の主要工程を示す断面図である
。同図において、（１）はＧａＡｓ基板、（２）は第１
のバイアホール、（３）は第２のバイアホール、（０は
第１のバイアホール内部金属層、（５）は下地無電解ニ
ッケルメッキ層、（６）はフォトレジスト層、（７）は
無電解ニッケルメッキ層、（８）は電解金メッキ層、（
８１）は突起削り取り部分である。FIGS. 1(a) to 1(d) are cross-sectional views showing the main steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. In the figure, (1) is a GaAs substrate, (2) is a first
(3) is the second via hole, (0 is the metal layer inside the first via hole, (5) is the base electroless nickel plating layer, (6) is the photoresist layer, (7) is the blank Electrolytic nickel plating layer, (8) electrolytic gold plating layer, (
81) is a portion where the protrusion has been removed.
先ず、第１図（ａ）に示すように、ＧａＡｓ基板（１）
の第１の面側から約３０１Ｌｍ深さの第１のバイアホー
ル（２）をＲＩＥ法等によって形成し、その内部に金属
層（０を電解金メッキにより形成する。その後、基板（
１）の厚さを約１００舊鵬まで研削、ラッピング、ポリ
ッシング等によって薄く加工し、基板（１）の第１の面
とは反対側の第２の面側から第１のバイアホール内部金
属層（０の底部を露出させるように第２のバイアホール
（３）を化学エツチング等により形成する０次に、第１
図（ｂ）に示すように、第２のバイアホール（３）の内
面を含む基板（１）の第２の面全面にパラジウム（Ｐｄ
）活性化を行なった後、無電解ニッケル（Ｘｉ）メッキ
を行なって下地無電解Ｘｉメッキ層（５）を形成する。First, as shown in FIG. 1(a), a GaAs substrate (1) is
A first via hole (2) with a depth of approximately 301 Lm from the first surface side of the substrate is formed by RIE method or the like, and a metal layer (0) is formed inside the via hole (2) by electrolytic gold plating.
1) is reduced to a thickness of about 100 mm by grinding, lapping, polishing, etc., and the metal layer inside the first via hole is processed from the second surface side opposite to the first surface of the substrate (1). (Form the second via hole (3) by chemical etching etc. so as to expose the bottom of the 0th order,
As shown in Figure (b), palladium (Pd) is applied to the entire second surface of the substrate (1) including the inner surface of the second via hole (3).
) After activation, electroless nickel (Xi) plating is performed to form a base electroless Xi plating layer (5).
その後、写真製版によって第２のバイアホール（３）の
開口部を除く基板（１）の第２の面全面をフォトレジス
ト層（６）等でマスクする。この時、下地無電解Ｉｆメ
ッキ層（５）の表面を置換型無電解金（Ａｕ）メッキに
より数１００λ〜２０００Ｘ程度Ａｕで置換しておくと
胴表面不動態化による種々の不都合を防止することがで
きる（図示省略）。Thereafter, the entire second surface of the substrate (1) except for the opening of the second via hole (3) is masked with a photoresist layer (6) or the like by photolithography. At this time, if the surface of the base electroless If plating layer (5) is replaced with about several 100λ to 2000X of Au by substitution type electroless gold (Au) plating, various problems caused by passivation of the shell surface can be prevented. (not shown).
続いて、Ｐｄ活性化を行なわずに無電解重メッキ液で処
理を行なうと、第２のバイアホール（３）の内部に露出
している下地無電解Ｘｉメッキ層（５）を触媒として化
学還元が行なわれ、第１図（ｃ）に示すように第２のバ
イアホール（３）の内部に無電解重メッキ層（７）が充
填される０次に、第１図（ｄ）に示すように、フォトレ
ジスト層（６）を除去後、基板（１）の第２の面全面に
電解Ａｕメッキ層（８）を形成し、その後で、第２のバ
イアホール（３）の充填層（７）の起伏により生ずる突
起部（８１）を研摩して削り取る。Subsequently, when treatment is performed with an electroless heavy plating solution without Pd activation, chemical reduction occurs using the base electroless Xi plating layer (5) exposed inside the second via hole (3) as a catalyst. As shown in FIG. 1(c), the electroless heavy plating layer (7) is filled inside the second via hole (3). Next, as shown in FIG. 1(d), After removing the photoresist layer (6), an electrolytic Au plating layer (8) is formed on the entire second surface of the substrate (1), and then a filling layer (7) of the second via hole (3) is formed. ) The protrusions (81) caused by the undulations are ground and scraped off.
この方法では、上述のように、Ｐｄ活性化を行なわずに
無電解Ｎｉメッキ層（７）を形成することによって、フ
ォトレジスト層（６）上へのメッキ成長を防止している
。In this method, as described above, by forming the electroless Ni plating layer (7) without Pd activation, plating growth on the photoresist layer (6) is prevented.
次に、第２図（ａ）乃至（ｅ）によってこの発明の第２
の実施例による半導体装置の製造方法を説明する。この
方法では、第１図（ａ）の前工程、すなわち第２のバイ
アホール（３）を形成する前の工程において、基板（１
）の第２の面全面に窒化シリコン、酸化シリコン等の絶
縁体層（１１）を形成する。Next, referring to FIGS. 2(a) to (e), the second
A method of manufacturing a semiconductor device according to an embodiment will be described. In this method, the substrate (1
) An insulating layer (11) of silicon nitride, silicon oxide, etc. is formed over the entire second surface of the substrate.
次に、第２図（ｂ）に示すように、絶縁体層（１１）の
一部を選択的に除去して第２のバイアホール（３）を形
成する。続いて、第２図（ｃ）に示すように、Ｐｄ活性
化を行なった後、無電解重メッキを行ない、第２のバイ
アホール（３）の内部に下地無電解重メッキ層（５）を
形成する。この時、Ｐｄ活性化において、 Ｐｄ核はＧ
ａＡｓ部にのみ選択的に成長するため、第２のバイアホ
ール（３）の内部にのみ選択的に旧メッキ層（５）が形
成される０次に、化学還元型無電解Ａｕメッキにより無
電解Ａｕメッキ層（１２）を第２のバイアホール（３）
内に充填する。その後、第２図（ｄ）に示すように、基
板（１）の第２の面全面に蒸着あるいはスパッタリング
によって金属層（１３）を形成し、次に、第２図（ｅ）
に示すように、金属層（１３）上に電解Ａｕメッキ層（
１４）を形成し、点線で示す層（１４）の突起部（１４
１）を研摩して削り取る。Next, as shown in FIG. 2(b), a part of the insulating layer (11) is selectively removed to form a second via hole (3). Subsequently, as shown in FIG. 2(c), after Pd activation, electroless heavy plating is performed to form a base electroless heavy plating layer (5) inside the second via hole (3). Form. At this time, during Pd activation, the Pd nucleus becomes G
Since the aAs layer selectively grows only in the second via hole (3), the old plating layer (5) is selectively formed only inside the second via hole (3). The Au plating layer (12) is connected to the second via hole (3)
Fill inside. Thereafter, as shown in FIG. 2(d), a metal layer (13) is formed on the entire second surface of the substrate (1) by vapor deposition or sputtering, and then, as shown in FIG. 2(e).
As shown in , an electrolytic Au plating layer (
14) and the protrusion (14) of the layer (14) shown by the dotted line.
1) Polish and scrape off.
第２の実施例では、第２のバイアホール（３）内に旧の
代りにＡｕを充填することにより第１の実施例よりも大
きな放熱効果が得られる。なお、上述の化学還元型無電
解Ａｕメッキは使用するメッキ液がＰＨ１３〜１４程度
の強アルカリ性を示すため、通常、第１の実施例で使用
したフォトレジストは使用できないため、絶縁体層（１
１）のマスクにより選択成長を行なっている。In the second embodiment, by filling the second via hole (3) with Au instead of the old one, a greater heat dissipation effect than in the first embodiment can be obtained. Note that in the chemical reduction type electroless Au plating described above, the plating solution used exhibits strong alkalinity with a pH of about 13 to 14, so the photoresist used in the first embodiment cannot usually be used.
Selective growth is performed using the mask 1).
次に、第３図（ａ） 、 （ｂ）によってこの発明の第
３の実施例による半導体装置の製造方法を説明する。こ
の方法では、上述の第１図（ａ） 、（ｂ）の各工程を
経た後、第３図（ａ）に示すように、第２のバイアホー
ル（３）内に電解Ａｕメッキ層（１５）を充填する。こ
れは、第１の実施例における無電解Ｘｉメッキ層（７）
を電解Ａｕメッキ層に代えたものである。この時、電解
メッキは第３図（ｂ）にメッキ電流波形の五個を示す正
逆逆転法（Ｐ、Ｒメッキ法）によって行なう、このＰ、
Ｒメッキ法では、正方向の電流パルス（２０）により均
一なメッキ成長を行ない、また逆極性の直流電流（２１
）によりメッキの突起部位のみを優先的に電解エツチン
グする両方の作用を持った波形の電流を周期的に供給す
るので、第２のバイアホール（３）の内部に優先的、且
つ選択的にメッキ成長が行なわれて、電解Ａｕメッキ層
（１５）が充填される。Next, a method for manufacturing a semiconductor device according to a third embodiment of the present invention will be explained with reference to FIGS. 3(a) and 3(b). In this method, after passing through the steps shown in FIGS. 1(a) and (b) above, an electrolytic Au plating layer (15 ). This is the electroless Xi plating layer (7) in the first embodiment.
is replaced with an electrolytic Au plating layer. At this time, electrolytic plating is performed by the forward/reverse reversal method (P, R plating method), which shows five plating current waveforms in Figure 3(b).
In the R plating method, a positive current pulse (20) is used to achieve uniform plating growth, and a direct current pulse (21) of opposite polarity is used to grow the plating uniformly.
), a waveform current is periodically supplied that has the effect of electrolytically etching only the protruding parts of the plating, so that the inside of the second via hole (3) is preferentially and selectively plated. Growth is performed to fill in the electrolytic Au plating layer (15).
上述の第１、第２、第３の実施例により例えば第４図に
示す構造の半導体装置が得られる。同図において、ＦＥ
Ｔ部（１００）は例えばソースパッドが第１のバイアホ
ール（２）によって接地されたものであり、選択ＰＨ９
埋込み層（１０１）は第１の実施例における無電解重メ
ッキ層（７）に、また第２の実施例における無電解Ａｕ
メッキ層（１２）に、更に、また第３の実施例における
電解Ａｕメッキ層（１５）にそれぞれ相当するものであ
る。 ＦＥＴ部（１００）から発生した熱は第１のバイ
アホール（２）及び基板（１）を介して選択ＰＨＳ埋込
み層（１０１）へ放散される。According to the first, second, and third embodiments described above, a semiconductor device having the structure shown in FIG. 4, for example, can be obtained. In the same figure, FE
In the T part (100), for example, the source pad is grounded through the first via hole (2), and the selected PH9
The buried layer (101) is the electroless heavy plating layer (7) in the first embodiment and the electroless Au plated layer in the second embodiment.
This corresponds to the plating layer (12) and the electrolytic Au plating layer (15) in the third embodiment. Heat generated from the FET section (100) is dissipated to the selected PHS buried layer (101) via the first via hole (2) and the substrate (1).
以上の各実施例では、基板として半絶縁性ＧａＡｓ基板
を例に挙げたが、この基板はエピタキシャル層を有する
ＧａＡｓ基板、ＩｎＰ基板等、半導体基板であればどの
様なものであってもよい。In each of the above embodiments, a semi-insulating GaAs substrate is used as an example of the substrate, but the substrate may be any semiconductor substrate such as a GaAs substrate having an epitaxial layer or an InP substrate.
以上のように、この発明によれば、半導体基板の厚さを
その基板全体にわたって一様に薄化しなくても所要の部
分のみを薄くしてそこに放熱体（ヒートシンク）を形成
することができるので、放熱効果を損なうことなく、半
導体基板の反り量を低減させ、かつその基板寸法を大き
くすることができる。As described above, according to the present invention, even if the thickness of the semiconductor substrate is not uniformly thinned over the entire substrate, it is possible to thin only the required portion and form a heat radiator (heat sink) there. Therefore, the amount of warpage of the semiconductor substrate can be reduced and the dimensions of the substrate can be increased without impairing the heat dissipation effect.
第１図（ａ）乃至（ｄ）はこの発明の第１の実施例によ
る半導体装置の製造方法の主要工程を示す断面図、第２
図（ａ）乃至（ｅ）はこの発明の第２の実施例による半
導体装置の製造方法の主要工程を示す断面図、第３図（
ａ）はこの発明の第３の実施例による半導体装置の製造
方法の主要工程を示す断面図、第３図（ｂ）は第３図（
ａ）の工程に用いるノブキ電流波形の一例を示す図、第
４図はこの発明の第１乃至第３の実施例によって製造し
た半導体装置の主要部の構造を示す斜視断面図、第５図
（ａ）乃至（ｄ）は従来の半導体装置の製造方法の主要
工程を示す断面図、第６図（ａ）及び（ｂ）は従来の半
導体装置における半導体基板の反り量と基板寸法の関係
を示す図である。
各図において、（１）は半導体基板、（２）はｆ５１の
バイアホール、（３）は第２のバイアホール、（０は金
属層、（５）は下地無電解ニッケルメッキ層、（７）は
無電解ニッケルメッキ層、（８）は電解金メッキ層、（
１１）は絶縁体層、（１２）は無電解金メッキ層、（１
３）は金属層、（１４）は電解金メッキ層、（１５）は
電解金メッキ層である。
なお、各図中同一符号は同−又は相当部分を示す。1(a) to 1(d) are cross-sectional views showing the main steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention, and FIG.
Figures (a) to (e) are cross-sectional views showing the main steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention, and Figure 3 (
3(a) is a cross-sectional view showing the main steps of the method for manufacturing a semiconductor device according to the third embodiment of the present invention, and FIG.
FIG. 4 is a diagram showing an example of the knob current waveform used in the step a), FIG. a) to (d) are cross-sectional views showing the main steps of a conventional semiconductor device manufacturing method, and FIGS. 6(a) and (b) show the relationship between the amount of warpage of the semiconductor substrate and the substrate dimensions in the conventional semiconductor device. It is a diagram. In each figure, (1) is the semiconductor substrate, (2) is the f51 via hole, (3) is the second via hole, (0 is the metal layer, (5) is the base electroless nickel plating layer, (7) is (8) is an electroless nickel plating layer, (8) is an electrolytic gold plating layer, (
11) is an insulator layer, (12) is an electroless gold plating layer, (1
3) is a metal layer, (14) is an electrolytic gold plating layer, and (15) is an electrolytic gold plating layer. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (3)
形成し、その後、その第１のバイアホール底部及び側面
に金属層を形成し、次に上記第１の面の反対側に在る上
記半導体基板の第２の面から第２のバイアホールを形成
して上記第１のバイアホール底部に形成した上記金属層
をその第２のバイアホール内に露出させる第１の工程と
、 上記第２のバイアホールの内面を含む上記半導体基板の
第２の面に下地無電解ニッケルメッキ層を形成する第２
の工程と、 上記第２のバイアホールの内部に無電解ニッケルメッキ
層を充填する第３の工程と、 上記第２のバイアホールの内部に充填された上記無電解
ニッケルメッキ層表面及び上記半導体基板の上記第２の
面に形成された上記下地無電解ニッケルメッキ層表面に
電解金メッキ層を形成する第４の工程と、 を備えた半導体装置の製造方法。(1) Form a first via hole from the first surface of the semiconductor substrate, then form a metal layer on the bottom and side surfaces of the first via hole, and then form a metal layer on the opposite side of the first surface. a first step of forming a second via hole from a second surface of the semiconductor substrate and exposing the metal layer formed at the bottom of the first via hole into the second via hole; a second layer forming a base electroless nickel plating layer on the second surface of the semiconductor substrate including the inner surface of the second via hole;
A third step of filling the inside of the second via hole with an electroless nickel plating layer, and the surface of the electroless nickel plating layer filled inside the second via hole and the semiconductor substrate. a fourth step of forming an electrolytic gold plating layer on the surface of the base electroless nickel plating layer formed on the second surface of the semiconductor device.
形成し、その後、その第１のバイアホール底部及び側面
に金属層を形成し、次に上記第１の面の反対側に在る上
記半導体基板の第２の面に絶縁体層を形成し、その後そ
の第２の面から第２のバイアホールを形成して上記第１
のバイアホール底部に形成した上記金属層をその第２の
バイアホール内に露出させる第１の工程と、 上記絶縁体層をマスクとして上記第２のバイアホール内
部に下地無電解ニッケルメッキ層を形成する第２の工程
と、 上記第２のバイアホールの内部に化学還元型無電解金メ
ッキ層を充填する第３の工程と、 上記第２のバイアホールの内部に充填された上記無電解
金メッキ層表面及び上記半導体基板の第２の面に形成さ
れた上記絶縁体層表面を覆う金属層を形成し、その後、
その金属層上に電解金メッキ層を形成する第４の工程と
、 を備えた半導体装置の製造方法。(2) Forming a first via hole from the first surface of the semiconductor substrate, then forming a metal layer on the bottom and side surfaces of the first via hole, and then forming a metal layer on the opposite side of the first surface. forming an insulating layer on a second surface of the semiconductor substrate, and then forming a second via hole from the second surface to
a first step of exposing the metal layer formed at the bottom of the via hole into the second via hole; and forming a base electroless nickel plating layer inside the second via hole using the insulating layer as a mask. a second step of filling the inside of the second via hole with a chemically reduced electroless gold plating layer; and a surface of the electroless gold plating layer filled inside the second via hole. and forming a metal layer covering the surface of the insulator layer formed on the second surface of the semiconductor substrate, and then,
A method for manufacturing a semiconductor device, comprising: a fourth step of forming an electrolytic gold plating layer on the metal layer.
形成し、その後、その第１のバイアホール底部及び側面
に金属層を形成し、次に上記第１の面の反対側に在る上
記半導体基板の第２の面から第２のバイアホールを形成
して上記第１のバイアホール底部に形成した上記金属層
をその第２のバイアホール内に露出させる第１の工程と
、 上記第２のバイアホールの内面を含む上記半導体基板の
第２の面に下地無電解ニッケルメッキ層を形成する第２
の工程と、 上記第２のバイアホールの内部に正逆逆転法によって電
解金メッキ層を充填する第３の工程と、上記第２のバイ
アホールの内部に充填された上記電解金メッキ層表面及
び上記半導体基板の上記第２の面に形成された上記下地
無電解ニッケルメッキ層表面に電解金メッキ層を形成す
る第４の工程と、 を備えた半導体装置の製造方法。(3) Form a first via hole from the first surface of the semiconductor substrate, then form a metal layer on the bottom and side surfaces of the first via hole, and then form a metal layer on the opposite side of the first surface. a first step of forming a second via hole from a second surface of the semiconductor substrate and exposing the metal layer formed at the bottom of the first via hole into the second via hole; a second layer forming a base electroless nickel plating layer on the second surface of the semiconductor substrate including the inner surface of the second via hole;
A third step of filling the inside of the second via hole with an electrolytic gold plating layer by a forward/reverse method, and the surface of the electrolytic gold plating layer filled inside the second via hole and the semiconductor. A method for manufacturing a semiconductor device, comprising: a fourth step of forming an electrolytic gold plating layer on the surface of the base electroless nickel plating layer formed on the second surface of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1236270A JPH0821598B2 (en) | 1989-09-12 | 1989-09-12 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1236270A JPH0821598B2 (en) | 1989-09-12 | 1989-09-12 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0399470A true JPH0399470A (en) | 1991-04-24 |
| JPH0821598B2 JPH0821598B2 (en) | 1996-03-04 |
Family
ID=16998295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1236270A Expired - Lifetime JPH0821598B2 (en) | 1989-09-12 | 1989-09-12 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0821598B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05102200A (en) * | 1991-10-03 | 1993-04-23 | Mitsubishi Electric Corp | Semiconductor device |
| JPH0758132A (en) * | 1993-08-17 | 1995-03-03 | Nec Corp | Method of manufacturing semiconductor device |
| JP2007157844A (en) * | 2005-12-01 | 2007-06-21 | Sharp Corp | Semiconductor device, and method of manufacturing same |
| JP2007157883A (en) * | 2005-12-02 | 2007-06-21 | Mitsubishi Electric Corp | Semiconductor device and method of manufacturing same |
| JP2009064840A (en) * | 2007-09-04 | 2009-03-26 | Sanyo Electric Co Ltd | Solar cell |
| US7834461B2 (en) | 2006-09-27 | 2010-11-16 | Nec Electronics Corporation | Semiconductor apparatus |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5661170A (en) * | 1979-10-25 | 1981-05-26 | Mitsubishi Electric Corp | Preparation of field effect transistor |
| JPS60161651A (en) * | 1984-02-02 | 1985-08-23 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH01187955A (en) * | 1988-01-22 | 1989-07-27 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1989
- 1989-09-12 JP JP1236270A patent/JPH0821598B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5661170A (en) * | 1979-10-25 | 1981-05-26 | Mitsubishi Electric Corp | Preparation of field effect transistor |
| JPS60161651A (en) * | 1984-02-02 | 1985-08-23 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH01187955A (en) * | 1988-01-22 | 1989-07-27 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05102200A (en) * | 1991-10-03 | 1993-04-23 | Mitsubishi Electric Corp | Semiconductor device |
| JPH0758132A (en) * | 1993-08-17 | 1995-03-03 | Nec Corp | Method of manufacturing semiconductor device |
| JP2007157844A (en) * | 2005-12-01 | 2007-06-21 | Sharp Corp | Semiconductor device, and method of manufacturing same |
| JP2007157883A (en) * | 2005-12-02 | 2007-06-21 | Mitsubishi Electric Corp | Semiconductor device and method of manufacturing same |
| JP4637009B2 (en) * | 2005-12-02 | 2011-02-23 | 三菱電機株式会社 | Manufacturing method of semiconductor device |
| US7834461B2 (en) | 2006-09-27 | 2010-11-16 | Nec Electronics Corporation | Semiconductor apparatus |
| JP2009064840A (en) * | 2007-09-04 | 2009-03-26 | Sanyo Electric Co Ltd | Solar cell |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0821598B2 (en) | 1996-03-04 |
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