JPH0398392A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To display a video signal inputted with high resolution on a liquid crystal display panel without eminent flicker by writing the video signal inputted once into a memory and driving the liquid crystal display panel with the number of frames twice that of the signal of the NTSC system. CONSTITUTION:A video signal processing circuit consists of an A/D signal converter 1, a field memory 2 having a capacity of 2 frames exclusively for even and odd number fields, a line memory 5 operated at a clock being twice or over of the operating clock of the field memory 2, and a D/A converter 7 as major circuit blocks. Then the operation of displaying a picture data by one frame onto the liquid crystal display panel consecutively twice is repeated to apply liquid crystal display without thinning a picture data of an valid vertical scanning line number of the video signal of the NTSC system and apparent flicker is not made remarkable.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video signal processing circuit used in an active multiplex type liquid crystal television that inputs an analog N'I'SC type video signal. It is something.

BACKGROUND ART A conventional active matrix type liquid crystal television has a vertical M pixel count (number of scanning lines in CRi') of 220 to 240. This means that the N'I' SC video signal of the input analog 1 cog is divided into an even field and an odd field, and the image transmission is sent, and the frame frequency is 30Hz. It is based on.

Generally, when displaying video on a small liquid crystal panel, the liquid crystal panel itself has no resolution, so even NTSC video signals are displayed in even fields. There is no problem in treating odd fields as the same video signal. That is, N
When we consider the case of displaying 'I' SC video signals as they are, the repetition frequency is 15Hz, which causes noticeable flicker in the image, since the polarity of the signal must be reversed for each frame for the LCD panel. Therefore, even and odd fields are regarded as the same image, and by forming a liquid crystal panel with the number of scanning lines for one field (220 to 240), the repetition frequency can be set to 30Hz.
This makes flicker less noticeable.

Problems to be Solved by the Invention> Therefore, in this type of LCD television, the original NTSC
In recent years, as liquid crystal panels have become larger and more precise, it has become necessary to faithfully display each field.

On the other hand, if the NTSC system was followed directly, the frame frequency would be 30 Hz, and the frequency of the AC signal 9 that drives the liquid crystal panel would be 15 Hz, which had the problem of making it impractical due to flicker. Ta.

The present invention has been made in view of these problems of the conventional technology, and its purpose is to
NT on a high-definition liquid crystal panel with both prime numbers in the vertical direction (Y direction) equal to the effective number of vertical scanning lines of the SC (approximately 480).
The present invention provides a video signal processing circuit capable of displaying an SC video signal on a liquid crystal display without making flicker noticeable.

Means for Solving the Problems> In order to achieve the above objects, the present invention provides an analog N
'T' SC A video signal processing circuit that inputs a video signal, processes the video signal, and displays the video signal on a liquid crystal panel, at least an analog-to-digital signal converter that converts the video signal into a digital signal B, and an odd field. Memory and even field memory 3 A field memory in which two frames are arranged, a write timing control means for controlling the timing of writing digitally converted video signals into the odd field memory and the even field memory. a pair of selectors used when reading data from memory to select a frame opposite to the frame performing the write;
A line memory connected to the selector and configured to store one line of the video signal capable of operating at an evening lock of twice or more the operating clock of the field memory, comprising an odd line and an even line memory, and a line memory for the liquid crystal panel; a selector that selects the line memory in synchronization with odd and even lines of the liquid crystal panel when data in the line memory is not read; and a selector that transfers data from the field memory to the line memory and from the line memory to the liquid crystal panel. The device is characterized by being equipped with data transfer control means for controlling data transfer to. Effect> N
A video signal processing circuit for displaying a TSC video signal is an analog-to-digital signal converter (rA).
/DJ), a feed memory for two frames dedicated to each of the even and odd fields, and a line memory that can operate with a clock that is more than twice the operating clock of the field memory. and a digital-to-analog signal converter (hereinafter abbreviated as 1'D/AJ) as the main circuit block, and by repeating the operation of displaying one frame of image data on the liquid crystal panel twice in succession. 'rS
Effective number of vertical scanning lines of C format video signal (approximately 480 lines)
The image data is displayed on a liquid crystal display without being thinned out, and the apparent flicker is made independent.

Embodiments> Hereinafter, specific embodiments will be explained with reference to drawings. FIG. 1 is a block diagram of a video signal processing circuit which is a specific embodiment of the present invention.

In Figure 1, 1 is the input analog N'r s
A/D 2 converts the C-type video signal VAD into a digital signal, and 2 is an odd field memory 21.23 and an even field memory 22.2. This is a field memory consisting of a memory for two frames dedicated to each of the field signals J, -3. 1,+
Based on D, odd field data is written into 21 (23) and even field data is written into 22 (24), respectively. 3 is a write timing control means (14rite timing control means) for controlling the write operation of the field memory 2;
ntrol (hereinafter referred to as rWTCJ), 4 is used when reading data from the field memory 2, and a pair {41. 42}, and 5 is the selector 41. 42 is a line memory that stores one line of video data that can be operated with an evening lock of more than twice the operating clock of the field memory. Here, 51 is provided for odd lines, and 52 is provided for even lines. It is provided for the purpose of 6 is an active matrix (not shown) method with high precision (7180 double elements in the Y direction,
640 pixels or more in the direction, however, the X direction refers to the horizontal direction>
This is a selector that selects and outputs data when reading data from the line memory 5 to a liquid crystal panel (in this case, a liquid crystal panel includes a liquid crystal driver circuit). line. Select line memory in synchronization with even numbered lines. 7 is a D/A that converts the signal (digital value) selected by the selector 6 into an analog video signal for the liquid crystal panel.As for D/A 7, in a high-definition liquid crystal panel, the video signal is converted to digital data. Needless to say, there is no need to use it in such a case since there are many inputs. 8 is for data transfer from field memory 2 to line memory 5 and data transfer from line memory 5 to the liquid crystal panel. Control means (Read Tiiling Cont.
rol, hereinafter abbreviated as r R 'I' C J). SCK is the conversion clock (Sa-ρling
C.K. , a sampling frequency of 7 seconds), and should generally be generated from a horizontal synchronization signal of NTSC video signal (this technique is well known, so its explanation will be omitted). I{syNc is the horizontal synchronization signal, V
SYNc is a vertical synchronization signal, and this horizontal synchronization signal WHs
yNc and vertical synchronization signal 'tVsyNC are W'l'C3,
It is guided by R'l'C8 and is used as the timing for initialization and display operations. l. cD v c is a timing control signal.

Hereinafter, with reference to FIGS. 2 to 5 regarding such a configuration, we will explain how to avoid thinning out the image data by repeating the operation of displaying it on the liquid crystal panel twice in succession.
An explanation will be given of the operation that can display an SC system video signal on a liquid crystal display and eliminate the apparent flicker.

FIGS. 2 to 5 are diagrams for explaining FIG. 1. In detail, FIG. 2 is a time chart of video sampling, and FIG.
6 is a time chart for writing (W)/reading (R) to the line memory.

8 As mentioned above, the video signal of the N'T'SC system has approximately 480 effective vertical scanning lines, a signal with an effective horizontal display width of approximately 52 μs, and a vertical synchronization frequency of 60 μs in interlace scanning. Hz, so 30 frames/
An image will be created in step S.

Therefore, if the number of vertical scanning lines is 480, the sampling frequency /S in the horizontal direction is obtained from the asvec l ratio of the N 'I'' SC method, /s = 52, czs/ (480X (4/3)):
A frequency of 12.3 MHz or higher is desirable. This sampling frequency 7
The video signal vAD is sampled at 6 (Sck), and A
FIG. 2 shows the case where analog-to-digital conversion is performed based on the timing of ScK with /D1. This digitized video data is field signal-IjFo.
As shown in FIG.
The write operation is controlled by , and sequentially, the odd field data of the first frame is written to the field memory 21 (indicated by 14RITE), and the even field data is written to the field memory 22 (indicated by WRITE).
), the odd field data of the next frame is written to the field memory 23 (indicated by 11RITE),
Even field data is written into the field memory 24 (indicated by 14RIT), and this operation is repeated thereafter.

On the other hand, when writing data to the liquid crystal panel, the input video signals stored in the odd field 21 (23) and the even field 22 (24) are R T' C 8 as shown in FIG. Data transfer from the field memory 2 to the line memory 5 is performed via the selector 4 by the control signal of is stored, and further data is transferred from the line memory 5 to the liquid crystal panel via the selector 6, and at this time, the line memory is selected by the selector 6 in synchronization with the odd number line and c4 number line of the liquid crystal panel,
Since the data in the odd field memory and the data in the even field memory are combined and output as f,-1 video data by the driver of the liquid crystal panel (not shown), the liquid crystal panel concatenates the data into two frames. C1, the number of frames per second is set to 60, and the AC frequency of the liquid panel is set to 30 Hy. This will be displayed as follows.

The operations of the field memories 21-24 at this time correspond to the "RFAD" portion shown by broken lines in FIG. 3 (11>-(V)).

By the way, in order to realize such an operation, it is necessary to read the input video signal VAD from the field memory 2 at a frequency twice as high as the sampling clock (i.e., the writing frequency/S to the field memory 2). be. However, this is not realistic in terms of speed (when considering it as a real product including cost, etc.). Therefore, as a line memory, PIF'
High-speed line memory with O structure (memory with capacity to store one line of video signal VAD, 510
, 520). # is true.

As a result, as shown in FIG. 5, field memo 11 21. 22 ([R]) to line memory 5
10. When transferring data to 520 (FW]), read/write is performed at a frequency of /S, and the line memory 510,
When outputting from 520 ([W]) to the LCD panel (
[R] ) can achieve this purpose by reading out at a frequency of 2/s.

By the way, the above explanation is for the case where a single monochrome display of N'I'SC video 1g'3 is displayed on a monochrome liquid crystal panel, but in the case of a color liquid crystal panel, the field memory 2 to selector shown in Fig. 1. For the circuit configurations up to 6, if λ, G, and B are each given the same circuit power, color display can be achieved.

<Effects of the Invention> As explained in [2] below, the present invention has a configuration in which the input video signal is written into the memory and the liquid crystal panel is driven at twice the number of frames of NTSC, so that flicker is not noticeable. This has the effect that a video signal input at high resolution can be displayed on a liquid crystal panel.

1 2

[Brief explanation of drawings]

FIG. 1 is a block diagram of a video signal processing circuit which is a specific embodiment of the present invention, and FIGS. 2 to 5 are diagrams for explaining FIG. 1. 1...Analog-digital signal converter (A/D), 2.
...Feed memory, 3...Write timing control means (WTC), 4. 6...Selector, 5...Line memory, 7...Digital analog signal converter (I)
/A), 8...Data transfer control means (RTC).

Claims (1)

[Scope of Claims] A video signal processing circuit that inputs an analog NTSC video signal, processes the video signal, and displays it on a liquid crystal panel, at least an analog-to-digital signal converter that converts the video signal into a digital signal. , a field memory in which an odd field memory and an even field memory are arranged for two frames, a write timing control means for controlling the writing timing of a digitally converted video signal to the odd field memory and the even field memory; A pair of selectors that are used when reading data from the field memory and select a frame opposite to the frame that is being written; and a clock that is connected to each selector and that is twice or more the operating clock of the field memory. and a line memory for storing one line of the video signal, which is operable in the following manner: a line memory for odd lines and an even line; a selector that selects the line memory in synchronization with odd and even lines of the liquid crystal panel when reading data from the line memory to the liquid crystal panel; and a selector that transfers data from the field memory to the line memory and the line memory. 1. A video signal processing circuit comprising: data transfer control means for controlling data transfer from the liquid crystal panel to the liquid crystal panel.