JPH0374554B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an interline transfer CCD suitable for use in electronic still cameras or variable shutter time video cameras that capture images using solid-state image sensors.
The present invention relates to a drive device.

Electronic still camera, for example, a still image photographing device having an electronic imaging means as shown in Japanese Patent Application Laid-Open No. 49-52912 and an electric or magnetic recording means capable of recording or reproducing the electrical signal obtained by the electronic imaging means. When electronically providing a shutter function to a solid-state image sensor used in a recording camera or a video camera with variable shutter time, it has been known to use an interline transfer CCD as the solid-state image sensor.

Incidentally, a typical example of the structure of a conventional interline transfer CCD is partially shown in FIGS. 1a and 1b. That is, an overflow drain 2 serving as a means for discharging excess charge is placed on one side of the photodiode array 1 as a light receiving section.
A vertical transfer section 3 consisting of a CCD for vertical transfer of signal charges is arranged in parallel on the other side, and an overflow control gate 4 for controlling the overflow potential is arranged between the photodiode array 1 and the overflow drain 2. A channel is provided between the photodiode array 1 and the vertical transfer section 3 in order to transfer the signal charge accumulated in the photodiode array 1 to the buried channel 3-2 under the transfer electrode 3-1 of the vertical transfer section 3. A transfer gate 5 is provided for interline transfer.
A two-dimensional image sensor is created by arranging a plurality of these element units by arranging a channel stop 6 between each unit as one element unit of the vertical light reception/transfer channel of the CCD to prevent the spread of charge in the horizontal direction. It is structured as follows. Note that in the vertical transfer section 3 formed by the vertical transfer electrode 3-1 and the buried channel 3-2, the first
As shown in the potential diagram of FIG. 1c shown in the lower part of the figure, the potential at the bottom of the electrode 3-2 fluctuates between the solid line position and the broken line position during vertical transfer.

Traditional interline transfer for such a structure
To give the CCD an electronic shutter function,
First, the charges accumulated in the photodiode array of the light-receiving section are discharged all at once, and then exposure is performed for the necessary time, and when this exposure is completed, the unnecessary charges are already discharged by some means under the vertical transfer electrode. An operational function is required to transfer the signal charge of the photodiode obtained by the exposure. For this reason, in conventional drive devices, the bulk discharge of unnecessary charges from the photodiode array 1 prior to exposure is performed by applying a high voltage to the overflow control gate 4 to lower the potential barrier between the photodiode and the overflow drain. , unnecessary charges under the vertical transfer electrode 3-1 are transferred vertically and horizontally before the transfer after exposure is completed, so that they can be transferred along the same route as the signal charges.
The shutter function was obtained by sequentially ejecting light outside the CCD.

However, the electronic shutter function using such a conventional interline transfer CCD has several problems as described below.

That is, the first is that the same path as the signal charge transfer is used to discharge unnecessary charge under the vertical transfer electrode, such as charge due to dark current, so no matter how fast the transfer is performed, the discharge of unnecessary charge cannot be ignored. The point is that it takes time.

For example, if we consider the case where exposure control is performed using the TTL direct metering method, if unnecessary charges generated in the vertical transfer unit 3 due to dark current etc. are discharged after the completion of the photometry, it will be difficult to control the exposure due to high-speed shutter (exposure time If the exposure time is very short), the unnecessary charge discharge time is added to the exposure time, so there is a risk of overexposure. Therefore, it is conceivable to finish discharging unnecessary charges from the vertical transfer section 3 before the photometry is completed, but since the shutter speed cannot be known in advance with the TTL direct photometry method, the discharge of unnecessary charges from the vertical transfer section 3 may be terminated before the start of exposure or from the time of the start of exposure. Unnecessary charge must be discharged, and for this reason, in the case of a low-speed shutter (when the exposure time is very long), the transfer clock must be continuously applied for a long time, resulting in the problem of increased power consumption. I end up.

The second problem arose because unnecessary charges from the photodiode were discharged to the overflow drain using an overflow control gate without using a transfer gate. That is, prior to exposure, unnecessary charges are discharged to the overflow drain, and after exposure is continued for a time corresponding to the shutter time, the signal charge accumulated in the photodiode is transferred to the vertical transfer CCD using a transfer gate. However, due to reasons such as the manufacturing process, irregularities and non-uniformities in geometrical dimensions, impurity concentration, etc. occur inside the device, and the height of the potential barrier of the overflow control gate and the height of the potential barrier under the transfer gate may differ. , which vary horizontally for one photodiode. Furthermore, the two potential barriers also vary in the vertical direction, independently of each other. Therefore, when the charge is transferred from the photodiode to the vertical transfer CCD after exposure is completed, the signal charge may be transferred incompletely or even excess charge may be transferred, causing noise to be superimposed and significantly reducing the signal-to-noise ratio of the signal charge. This caused the inconvenience of putting it away. This results in deterioration of image quality, and thus has traditionally been a drawback in that high element uniformity is required in order to realize the function of discharging unnecessary charges to the overflow drain.

Furthermore, the third problem was the signal charge transfer from the photodiode to the vertical transfer CCD using a transfer gate. That is, conventionally, by applying a low voltage to the transfer gate, the height of the potential barrier under the transfer gate is higher than the height of the potential barrier under the overflow control gate, and then the charge is exposed to light. After accumulation, a high voltage pulse is instantaneously applied to the transfer gate to lower the potential barrier under the transfer gate and transfer the signal charge from the photodiode to the vertical transfer CCD.

However, due to such short-term transfer, the signal charge of the photodiode cannot be transferred to the vertical transfer CCD.
The disadvantage was that the signal charge was not completely transferred to the photodiode, and a portion of the signal charge inevitably remained in the photodiode. This also poses a problem with the discharge of unnecessary charge prior to exposure, as the unnecessary charge is not completely discharged from the photodiode and remains.
This was mixed with the signal charge caused by the original exposure, causing a loss of image quality.

The fourth problem is that when an interline transfer CCD is used to obtain a good shutter function, the electrode structure of the device becomes complicated, which results in a reduction in manufacturing yield. However, although this fourth problem has been partially solved by making the transfer gate and the vertical transfer electrode common, the electrode structure as a whole is still complicated.

In the case shown in FIGS. 2a and 2b, the vertical transfer electrode 3-1 is enlarged closer to the photodiode array 1 without using a transfer gate to serve the same purpose.
This is an example in which the complexity of the electrode structure, which is a disadvantage of the conventional method, is partially reduced. In other words, as shown in the potential diagram in FIG. 2c, if the high voltage V _H shown by the broken line is applied to the vertical transfer electrode 3-1, the potential barrier between the photodiode 1 and the transfer section channel 3-2 becomes the highest. The charge at the potential level lowering and exceeding it is transferred from the photodiode 1 to the channel 3-2 and thus the photodiode 1
Applying a high voltage _VH to the transfer electrode 3-1, which extends to 3-1, is equivalent to the function of a transfer gate. Thereafter, in order to transfer charges in the vertical direction, it is sufficient to repeatedly apply two voltages, V _I and V _L , to the electrode 3-1 as shown by the solid line in Fig. 2c. In this case, the electrode voltage for vertical transfer is The potential barrier between photodiode 1 due to V _I and V _L is adjusted to be higher than the potential barrier between photodiode 1 and overflow drain 2, so that the potential barrier between photodiode 1 and photodiode 1 during vertical transfer is All of the overflowing charges generated by light are discharged through the overflow drain 2 and do not interfere with vertical transfer.

However, even with this improvement, the first drawback, which is the discharge of unnecessary charges in the vertical transfer section 3, and the second and third drawbacks cannot be solved.
It is exactly the same as the example shown in Figures a and 1b, and there is no difference. When applied to an electronic still camera that uses the electronic shutter function of the CCD itself or a video camera that has a variable shutter time and a strobe effect, it will be the same as above. This caused problems and could not be said to have practically satisfactory performance.

The present invention eliminates these drawbacks of the conventional ones,
Interline transfer suitable for solid-state imaging devices such as electronic still cameras with high-performance electronic shutter function or video cameras with variable shutter time.
The aim is to provide a CCD drive device.
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on drawings of embodiments thereof.

FIG. 3a is an explanatory plan view showing the structure of an embodiment of the interline transfer CCD used in the present invention, and FIG.
It is a sectional view of the part indicated by -A'.

In these figures, 31 is a light receiving photodiode, 32 is an overflow drain, and 32'
33 is a buried channel of the vertical transfer CCD, 34 is an overflow control gate,
35 is a transfer gate. Above 31~
35 constitutes one element row unit. In this embodiment, the vertical transfer CCD is driven in four phases, and φ ₁ to _{φ 4} indicate the electrodes of the vertical transfer CCD. 36 and 37 are channel stops. Channel stop 37 prevents the charge generated by photodiode 31 from spreading in the vertical direction.

The difference between this device and conventional devices is that channel stops, which were conventionally provided to prevent the spread of charges in the horizontal direction and were provided in a continuous vertical line, are now provided for each pixel as shown in the figure. A gate 38 is provided with a notch and thereon controls a potential barrier to electrons in the notch.
(hereinafter referred to as a clear gate).

As shown in Figure 3b, this device is made by forming a p layer by implanting boron ions, etc. onto an n-type substrate, and by further implanting ions of phosphorus, arsenic, etc. into the p layer. ⁺ layer is formed to form an overflow drain section 32 and a photodiode section 3.
1. An embedded channel section 33 of the vertical transfer CCD is created.

Here, the transfer gate 35 can of course be replaced by making the electrode of a vertical transfer CCD have a structure as shown in FIG. 2b, as in the conventional example.

In FIG. 3b, numeral 39 is a light shielding film, which prevents exposure of parts other than the photodiode section 31, and particularly prevents signal deterioration when signal charges are held and read out in the vertical transfer CCD. Additionally, the photodiode portion of the device has an npn three-layer structure to prevent smear components, as is well known.

Hereinafter, a driving device according to an embodiment of the present invention will be described based on this element.

FIG. 4 shows a timing chart of main driving pulses when this device is used in an electronic still camera. ψ ₁ , ψ ₂ , ψ ₃ , ψ ₄ indicate the voltage waveforms applied to the four transfer electrodes of the vertical transfer CCD, and ψ _TG
and ψ _CG indicate the voltage waveforms applied to the transfer gate and clear gate, respectively.

In addition, Figures 5a to 5g show schematic diagrams of potential barriers to electrons in each part of the element at each time shown in Figure 4, and the explanation will be given below in accordance with the flow of time. That's it.

In this embodiment, the electronic still camera using this device maintains the state at time t=t ₀ before photographing exposure. That is, in the vertical transfer electrodes, ψ ₁ and ψ ₂ are applied with a high voltage, ψ ₃ and ψ ₄ are applied with a low voltage, and ψ _CG ,
Since both ψ and _TG are at low voltages, their potential barriers are as shown in FIG. 5a.

In FIG. 5a, the charge exceeding the saturation point of the photodiode is drained into the overflow drain 32 because the potential barrier under the overflow control gate 34 is set lower than the potential barrier under the transfer gate 35.

Further, dark current charges are accumulated in the vertical transfer CCD as shown in the figure. When starting photography from this state, first, at time t= _t1 , a high voltage is applied to the clear gate 38 to lower the potential barrier below it, and at the same time, the voltages of electrodes φ ₁ and φ ₂ are lowered to lower the potential barrier below it. By raising the potential barrier, unnecessary charges in the buried channel 33 of the vertical transfer CCD are discharged to the overflow drain 32' of another adjacent element column as shown in FIG. 5b. FIG. 5b shows that the potentials ψ ₁ and ψ ₂ for electrons under the electrodes φ ₁ and φ ₂ gradually rise, and finally rise to the level indicated by the broken line. By this operation, unnecessary charges in the buried channel 33 of the vertical transfer CCD are discharged all at once to the overflow drain 32' without performing a transfer operation.

Subsequently, the voltages of the transfer electrodes φ ₁ and φ ₂ are made high again, and a voltage is applied to the transfer gate 35 at time t=t ₂ . As a result, charges exceeding the potential barrier determined by the transfer gate applied voltage ψ _TG are transferred from the photodiode 31 to the potential wells below the electrodes φ ₁ and φ ₂ as shown in FIG. 5c. At this time, the voltage application time to the transfer gate 35 is sufficiently long, for example.
Even if it is about 1 msec, there is no practical problem. Therefore, this transfer can be considered almost a complete transfer.

Transfer gate 35 at time t= _t3
After returning the voltage to a low voltage again and transferring the charge exceeding the fixed reference potential barrier of the photodiode 31 to the vertical transfer CCD 33, at time t= _t4 , this charge is again transferred to the adjacent gate as shown in FIG. 5b. Overflow drain for each element row 3
Discharge to 2'.

With the above operations, vertical transfer is performed prior to shooting.
Unnecessary charges from both CCD 33 and photodiode 31 can be discharged through clear gate 38 or through this gate and transfer gate 35.

On the other hand, accumulation of signal charges starts at time t= _t3 when the transfer gate 35 is returned to a low voltage. The time from time t ₃ to time t ₅ for discharging the charge of the photodiode 31 transferred to the vertical transfer CCD 33 is sufficiently short as several microseconds. Therefore, the exposure is at time t ₅
It will be continued thereafter. After time _t5 , high voltage is applied to the transfer gate 35 again.
The potential barrier schematic diagram of FIG. 5d or FIG. 5e is maintained until time _t6 when the proper exposure time is completed. That is, the signal charge generated by the photodiode 31 crosses the potential barrier under the transfer gate 35 and moves to the vertical transfer CCD 33. At this time, the clear gate 38 has V _I shown in FIG.
A voltage indicated by is applied, and the potential barrier under the clear gate 38 is set lower than the potential barrier under the transfer gate 35.

At this time, the potential barrier under the clear gate 38 is of course lower than the potential ψ ₃ and ψ ₄ for electrons under the electrodes φ ₃ and φ ₄ to which no voltage is applied in the vertical transfer CCD 33, and the overflowing signal charge It goes without saying that the vertical expansion of

As a result, the charges overflowing in the vertical transfer CCD 33 are discharged to the overflow drain 32' of each adjacent element column as shown in FIG. 5e.

It is convenient to calculate the appropriate exposure time starting at time _t3 and ending at time _t6 using a separately provided photometric element and photometric circuit.

The signal charges accumulated in the vertical transfer CCD 33 after time _t7 when the exposure is completed and both the transfer gate voltage and the clear gate voltage become low voltages are transferred and read out in the same manner as in a normal interline transfer CCD. Figures 5f and 5g show potential diagrams at this time. Immediately after photographing is completed, most of the photodiodes 31 are not saturated and are as shown in FIG. 5f. However, after a certain amount of time passes, some photodiodes begin to become saturated in charge, and as shown in Figure 5g, the overflowing charge drains into the overflow drain 3 of the same element row.
2 is discharged. Therefore, the blooming phenomenon during signal charge readout is suppressed.

FIG. 6 is a partial block diagram of an electronic still camera shown to explain the operation of the present invention, and FIG. 7 is a timing chart showing pulse timings at various points in FIG. 6. To simplify the explanation, the method of generating the clear gate pulse ψ _CG , transfer gate pulse ψ _TG , and four-phase vertical transfer clocks ψ ₁ to ψ ₄ among the pulses necessary for the CCD image sensor will be shown here. When the release switch shown at 61 in FIG. 6 is turned on, the Q output _Q0 of the flip-flop 62 composed of two NAND gates becomes High level. The output Q ₀ is applied to a 14-bit shift register 63 and a photometric calculation circuit 64, and serves as a shift-in input for the shift register 63 and as an initialization pulse for the photometry calculation circuit 64.

In this embodiment, the exposure timing is synchronized with a television synchronization signal generation circuit (not shown).
The shift register 63 also receives the horizontal drive signal HD as a clock. Therefore, the 14-bit outputs _Q1 to _Q14 of the shift register 63 are given pulses as shown in the timing chart of FIG. 7 relative to the input _Q0 .

From these outputs, the logic _{circuit 72} shown in the center _{of FIG} . A pulse ₁₂ that forces the pulse ψ _TG and the vertical transfer clocks ψ ₁ and ψ ₂ to a low level is generated using a timing chart as shown in FIG. Further, the output Q ₉ is directly applied to the photometry calculation circuit 64, and the calculation of the exposure time is started according to the output of the photometry element 65. The photometric calculation circuit 64 generates an exposure completion pulse shown as ψ _e in FIGS. 6 and 7 when the appropriate exposure amount for the image sensor 66 is reached. The pulse ψ _e is
Flip-flop 62, shift register 63 and two D flip-flops 67 and 68 are cleared. However, one D flip-flop 67 is cleared through a delay circuit 69, so the fall of the pulse ψ _CGI is delayed by a time τ ₁ from the other pulses. This delay time τ ₁ is the seventh
In the timing chart shown in the figure, from time t = t ₆ to t = t ₇
corresponds to the time between. The pulse ψ _s becomes the start pulse ψ _e of the vertical transfer drive circuit 71 via another delay circuit 70, and vertical transfer of signal charges of the element is started.

The times t ₁ to t 7 shown at the bottom of the timing chart in FIG. ₇ completely correspond to the times t ₁ to t ₇ shown in FIG. 4 previously.

Figure 8 shows an example in which the present invention is applied to an autofocus sensor, and the autofocus principle can be applied to both the front focus and rear focus blur detection method and the double engagement method. is possible.

In the figure, two rows of light receiving parts PD are provided in parallel, a common overflow drain OFD is provided between these two light receiving parts PD, and a charge to this overflow drain OFD is provided on both sides of the overflow drain OFD. An overflow control gate OFCG is provided to control the height of the potential during discharge. Needless to say, each photodiode is separated horizontally by a channel stop (not shown). The charge generated in the photodiode PD is transferred to the barrier gate BG
is stored in the potential well under the store gate STORE. When the exposure for a predetermined time is completed, the barrier gate BG is closed and the store gate is closed.
The charge under STORE is the transfer gate TG
is read into the horizontal transfer CCD (H.CCD) via. The horizontal transfer CCD (H.CCD) is driven here by two-phase clocks ψ ₁ and ψ ₂ . Horizontal transfer CCD (H.
A clear gate CG and a clear drain CD are provided on the opposite side of the transfer gate of the horizontal transfer CCD (H.CCD), making it possible to discharge the charges of the horizontal transfer CCD (H.CCD) all at once. As a result, unnecessary charges inside the element (dark current charges or unnecessary charges generated due to the timing of driving the element) can be discharged to the outside of the element by transferring a few clocks at most. Note that the shaded MPD is a light-shielded light receiving element and is used as an optical black clamp.

Furthermore, in the figure, only the photodiode PD can be exposed to light, and the other parts of the device are shielded from light.

By using the image pickup device and drive device as described above, the drawbacks of the conventional technology can be fundamentally solved.

In other words, the first problem was vertical transfer.
The problem of unnecessary charge discharge from CCDs can be solved by installing a clear gate between the vertical transfer CCD and the adjacent overflow drain, and by controlling the height of the potential barrier under the gate, unnecessary charges can be removed all at once. This problem has been solved as it can be discharged in a short period of time.

The second problem, unnecessary charge from the photodiode was discharged all at once using an overflow control gate, so the influence of element irregularities and non-uniformity when reading out signal charges was solved. This problem was solved by discharging unnecessary charges under the same conditions as signal charge reading, by performing both via a transfer gate.

Furthermore, the third problem, the problem of incomplete transfer due to short-time transfer of signal charges, is that the potential barrier under the transfer gate continues to be lowered for most of the effective exposure time, and the photodiode is constantly lowered. This was solved by allowing the signal charge to flow from the to the vertical transfer CCD.

Furthermore, the fourth problem has been solved by obtaining a good shutter function with a simple electrode structure.

As is clear from the above description, according to the interline transfer CCD driving device according to the present invention,
Unnecessary charges can be discharged from photodiodes and vertical transfer CCDs in an extremely short time, and there is little influence from non-uniformity in the device manufacturing process, which not only reduces power consumption and improves yield, but also Since the signal charge is completely transferred from the CCD to the vertical transfer CCD, it has the effect of realizing a good electronic shutter function.

[Brief explanation of drawings]

1a, 1b, and 1c are a plan view, a sectional view, and a schematic diagram of a potential barrier schematically showing the main parts of an example of a conventional interline transfer CCD; FIGS. 2a, 2b, and 2c. The figures are a plan view, a sectional view, and a schematic diagram of a potential barrier schematically showing the main parts of another conventional example. Figures 3a and 3b
The figures are an explanatory plan view and a sectional view schematically showing essential parts of one embodiment of the element used in the present invention, FIG. 4 is a timing chart showing an example of a method for driving the element, and FIGS. FIG. 5g is a schematic diagram showing the state of potential barriers to electrons in each part at main times of the operation shown in FIG. 4. FIG. 6 is a block diagram of the main parts when the present invention is applied to an electronic still camera, FIG. 7 is a timing chart showing the timing of pulses at various points in FIG. 6, and FIG. It is an explanatory view when applied to a sensor for waste. 1, 31... Light receiving part photodiode, 2, 3
2... Overflow drain, 32'... Overflow drain in units of other element rows, 3, 33
... Vertical transfer section, 3-1 ... Vertical transfer CCD, 3
-2... Embedded channel, 4, 34... Overflow control gate, 5, 35... Transfer gate, 6, 36, 37... Channel stop, 38... Clear gate, 9, 39
...Light shielding film.

Claims (1)

[Claims] 1. An overflow drain is arranged in parallel through an overflow control gate on one side of a light receiving section, and a vertical transfer section is arranged in parallel through a transfer gate on the other side, and a channel stopper is formed in units of element rows. In a plurality of interline transfer CCDs arranged in parallel through the channel stopper, a clear gate is provided in the channel stopper, and the potential barrier to electrons can be controlled by the voltage applied to the clear gate, and each element column is After applying a high voltage to the unit transfer gate and transferring the unnecessary charges in the light receiving section to the vertical transfer section via the transfer gate, a high voltage is applied to the clear gate of each element column unit to transfer the unnecessary charge from the light receiving section to the vertical transfer section. 1. A driving device for an interline transfer CCD, characterized in that the device controls the overflow to be discharged to the overflow drain of each adjacent element column via the overflow drain of another adjacent element column. 2. In claim 1, after the start of exposure, a high voltage is applied to the clear gate to discharge unnecessary charges in the vertical transfer section to the overflow drain of other adjacent element columns through the clear gate. The interline transfer is characterized in that the signal charges in the light receiving section are controlled to be transferred to the vertical transfer section by applying an intermediate voltage to the clear gate and then applying a high voltage to the transfer gate.
CCD drive device. 3 In claim 2, during the period during which signal charges are being transferred after completion of exposure, a predetermined voltage is applied to the overflow control gate to remove a portion of the charges generated in the light receiving section during the period. A driving device for an interline transfer CCD, characterized in that it controls the overflow to be discharged to the overflow drain of the same element column. 4 In claim 3, the voltage applied to the overflow control gate is obtained by applying a high voltage to the transfer gate when transferring unnecessary charges in the light receiving section to the vertical transfer section prior to exposure. A driving device for an interline transfer CCD, characterized in that the voltage is such as to make a potential barrier for electrons under the overflow control gate higher than a potential barrier for electrons under the transfer gate.