JPH0369190A - Conductor paste for mullite multi-layer wiring board and mullite multi-layer wiring board using it - Google Patents
Conductor paste for mullite multi-layer wiring board and mullite multi-layer wiring board using itInfo
- Publication number
- JPH0369190A JPH0369190A JP20463889A JP20463889A JPH0369190A JP H0369190 A JPH0369190 A JP H0369190A JP 20463889 A JP20463889 A JP 20463889A JP 20463889 A JP20463889 A JP 20463889A JP H0369190 A JPH0369190 A JP H0369190A
- Authority
- JP
- Japan
- Prior art keywords
- mullite
- conductor
- wiring board
- wiring
- multilayer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 title claims abstract description 55
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 title claims abstract description 33
- 229910052863 mullite Inorganic materials 0.000 title claims abstract description 33
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000002245 particle Substances 0.000 claims description 13
- 238000005498 polishing Methods 0.000 claims description 4
- 238000007772 electroless plating Methods 0.000 claims 1
- 239000000843 powder Substances 0.000 abstract description 16
- 238000000034 method Methods 0.000 abstract description 7
- 238000007650 screen-printing Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 description 30
- 239000010410 layer Substances 0.000 description 16
- 239000000919 ceramic Substances 0.000 description 12
- 230000007547 defect Effects 0.000 description 9
- 238000005245 sintering Methods 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 239000010408 film Substances 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- QTBSBXVTEAMEQO-UHFFFAOYSA-M Acetate Chemical compound CC([O-])=O QTBSBXVTEAMEQO-UHFFFAOYSA-M 0.000 description 1
- 241000272525 Anas platyrhynchos Species 0.000 description 1
- 239000001856 Ethyl cellulose Substances 0.000 description 1
- ZZSNKZQZMQGXPY-UHFFFAOYSA-N Ethyl cellulose Chemical compound CCOCC1OC(OC)C(OCC)C(OCC)C1OC1C(O)C(O)C(OC)C(CO)O1 ZZSNKZQZMQGXPY-UHFFFAOYSA-N 0.000 description 1
- XSTXAVWGXDQKEL-UHFFFAOYSA-N Trichloroethylene Chemical group ClC=C(Cl)Cl XSTXAVWGXDQKEL-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 229920001249 ethyl cellulose Polymers 0.000 description 1
- 235000019325 ethyl cellulose Nutrition 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000003349 gelling agent Substances 0.000 description 1
- 239000002241 glass-ceramic Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920002037 poly(vinyl butyral) polymer Polymers 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はムライト多層配線基板に係シ、特に基板のそう
を小さくするに好適なムライト多層配線基板用導体ベー
ス）＞よびこれを用いたムライト多層配線基板に関する
。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a mullite multilayer wiring board, and in particular, a conductor base for a mullite multilayer wiring board suitable for reducing the size of the board) and a mullite using the same. It relates to a multilayer wiring board.
最近に電子計算機の演算速度を速くするために、薄膜と
厚膜を混成した多層基板が、米国特許第４２２１０４７
号や、アイ・イー・イー、トランザクシ冒ンズ オン
コンポーネント、ハイブリッド。Recently, in order to increase the calculation speed of electronic computers, a multilayer substrate made of a mixture of thin and thick films has been published in US Pat. No. 4,221,047.
No., I.E.E., Tranzakushi Adventures on
component, hybrid.
アンド マニエクアクチャリング テクノロジ。and mani-equacturing technology.
シー エイチ エム ７’−６（１９８ｓ牟６月）＄１
６８頁から８１７２頁（Ｉ Ｅ Ｂ Ｂ 、 ｙｒａ
ｎｓ。C.H.M. 7'-6 (June 198s) $1
pages 68 to 8172 (IEB, yra
ns.
Ｃｏｍｐｏｎｅｎｔｓ、 Ｈｙｂｒｉｄｓ、 ａｎｄ
Ｍａｎｕｆａｏｔｕｒｉｎｇ’ｆ：ｅＱｂｎｏｌＱｇ７
ｔ ＶＯｌ、 ＣＨＭＴ−６，ｔ’ｍ２ （Ｊｕｎｅ
１９８５）ｐｐ、 １６Ｂ−１７２）にかいて論じられ
ている。Components, Hybrids, and
Manufaoturing'f:eQbnolQg7
t VOl, CHMT-6, t'm2 (June
1985) pp. 16B-172).
第２図は従来のセ９ミック多層配線基板を例示する要部
断簡図である。これらの基板はガラスセラミックス等の
セラミック多層配線基板で、内層配線導体１と、層間接
続のためのスルーホールに充填された導体２と、表面配
線導体３とを形成したセラミック基板を２．５〜５μ溝
にラッピングして平坦化してから、薄膜プロセスで配線
層５を形成したのち、はんだ層６接続によｊ５ＬｓＩチ
ップ７を塔載する。FIG. 2 is a sectional view of the main parts illustrating a conventional ceramic multilayer wiring board. These boards are ceramic multilayer wiring boards such as glass ceramics, and are made of ceramic boards on which inner layer wiring conductors 1, conductors 2 filled in through holes for interlayer connections, and surface wiring conductors 3 are formed. After lapping into a 5 μm groove and flattening it, a wiring layer 5 is formed by a thin film process, and then a j5LsI chip 7 is mounted by connecting a solder layer 6.
第３図は第２図の製作プロセスの焼結時のセラミック基
板４のそ＃）ａの発生を示す断面図である。FIG. 3 is a cross-sectional view showing the generation of part a of the ceramic substrate 4 during sintering in the manufacturing process shown in FIG.
これらのセラミック基板４の製作プロセスにかける焼却
時にそｐａが発生する。When these ceramic substrates 4 are incinerated during the manufacturing process, sopa is generated.
第４図は第２図の製作プロセスのラッピング時のセラミ
ック基板４の表面配線導体３の欠損あるいは基板内部の
空孔８の露出による欠陥の発生を示す断面図である。こ
れらのセラミック基板４の製作におけるラッピング時に
Ａ −Ａ’までラッピングすると、表面配線導体３の欠
損あるいは基板４の空孔のない層すよシ内部に存在する
空孔８の露出による薄膜プロセスでの欠陥の発生に起因
するＬＳＩチップ７のはんだ層６のはんだ付は不良など
が発生する。FIG. 4 is a cross-sectional view showing the occurrence of defects due to defects in the surface wiring conductor 3 of the ceramic substrate 4 or exposure of holes 8 inside the substrate during lapping in the manufacturing process shown in FIG. When lapping to A-A' during the production of these ceramic substrates 4, defects may occur in the thin film process due to defects in the surface wiring conductor 3 or exposure of holes 8 existing inside the layer width of the substrate 4 without holes. Defects occur in the soldering of the solder layer 6 of the LSI chip 7 due to the occurrence of defects.
上記従来技術はムライトセラミックス基板の性質につい
て第３図に示す焼結時の基板４のそ夕ａの発生や、第４
図に示すラッピング時の表面配線導体３の欠損あるいは
基板４の内部に存在する空孔８の露出による薄膜プロセ
スでの欠陥の発生の点について配慮がされてからす、Ｌ
ＳＩチップ７のはんだ層６によるはんだ付は不良が発生
するなどの問題が多い。The above-mentioned prior art is concerned with the properties of mullite ceramic substrates, such as the generation of sores a on the substrate 4 during sintering as shown in FIG.
Consideration has been given to the occurrence of defects in the thin film process due to loss of the surface wiring conductor 3 during lapping as shown in the figure or exposure of holes 8 existing inside the substrate 4.
Soldering the SI chip 7 using the solder layer 6 has many problems such as the occurrence of defects.
本発明の目的は上記従来技術の問題点を解決し、そシの
ない平坦な基板を製作できるムライト多層配線基板用導
体ペーストおよびこれを用いたムライト多層配線基板を
提供することにある。An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a conductive paste for a mullite multilayer wiring board that can produce a smooth and flat board, and a mullite multilayer wiring board using the same.
上記目的を達成するために１本発明によるムライト多層
配線基板用導体ベース）＞よびこれを用いたムライト多
層配線基板は、ムライト多層配線基板の作製にかいて配
線導体形成に用いる導体ペースト原料のＷ（タングステ
ン）粉末の平均粒径を、スルーホール充填用と配線用と
に最適化して、スルーホール充填用にａ７〜ｌ１８μ情
で配線用に１〜ｔ５μ喝、またはスルーホール充填用に
ａ９〜１．５μ情で配線用にａ８〜３μ情としたもので
あシ、また上記の導体ペーストを用いて配線導体形成し
たムライト多層配線基板のメタライズ部分ｔ−機械的な
研摩によう平滑にするようにしたものであう、これによ
う必要とする基板のそシをＩ、ＳＩテップ塔載部分で２
０μ慣、基板全体で２００μ岳以内にし、またメタライ
ズ部分の凸を７μ情以内にすることができる。In order to achieve the above object, (1) a conductor base for a mullite multilayer wiring board according to the present invention and a mullite multilayer wiring board using the same are manufactured using W, which is a conductor paste raw material used for forming wiring conductors in the production of a mullite multilayer wiring board; The average particle size of the (tungsten) powder is optimized for through-hole filling and wiring, and the size is 1-t5μ for wiring, or A9-1 for through-hole filling. The metallized part of the mullite multilayer wiring board on which wiring conductors were formed using the above conductor paste was smoothed by mechanical polishing. This is probably the one that was used for this purpose.
0μ, the entire board can be kept within 200μ, and the convexity of the metallized portion can be kept within 7μ.
上記ムライト多層配線基板用導体ベース）＞よびこれを
用いたムライト多層配線基板は、薄膜形成あるいはＬＳ
Ｉチップ搭載のための微小パターンのはんだ接続が必要
であるため基板表面が平坦でなければならないが、一方
の配線導体には大きく分けて眉間の接続に用いるスルー
ホイール充填用と表面および内層配線ならびに封止キャ
ップ用メタライズやはんだ接続およびＩ１０ビンのろう
付は用メタライズの表面パターン形式用とが必要であυ
、これらの配線導体を個々にムライト基板に形成しても
基板にそうが発生しないが同時に同じ面に混在するとそ
うが発生するためそシが発生し慶いよつな導体配線が要
求されるので、スルーホール充填用と配線用とに配線目
的に応じて導体ペーストの材料であるＷ粉末の平均粒径
を変えることによう基板のそシを小さくするように作用
せしめ、またＷ粉末の粒径の組合せによっては配線部の
導体が基板表面よシも高くなって該高さにも差異がある
ため、焼結後！たはめっきシンタ後あるいは双方ともメ
タライズ部分を研摩することにより基板表面を平坦にす
るようにしている。The above conductor base for mullite multilayer wiring board)> and mullite multilayer wiring board using this can be formed by thin film formation or LS.
The surface of the board must be flat because solder connections with minute patterns are required to mount the I-chip, but one wiring conductor is broadly divided into one for filling through wheels used for connections between the eyebrows, and one for surface and inner layer wiring. Metallization for sealing caps, solder connections, and brazing of I10 bottles require surface pattern type metalization.
Even if these wiring conductors are individually formed on a mullite board, the problem will not occur on the board, but if they are mixed on the same surface at the same time, the problem will occur. By changing the average particle size of the W powder, which is the material of the conductor paste, depending on the purpose of wiring, whether for filling through holes or for wiring, the particle size of the W powder can be changed to reduce the warp of the board. Depending on the combination, the conductor of the wiring part will be higher than the board surface and there will be a difference in height, so after sintering! The substrate surface is made flat by polishing the metallized portion or after plating sintering or both.
以下に本発明による一実施例を第１図によう説明する。 An embodiment according to the present invention will be explained below as shown in FIG.
第１図は本発明によるムライト多層配線基板用導体ペー
ストおよびこれを用いたムライト多層配線基板の一実施
例を示す配線導体形成に用いるスルーホール充填用と表
面および内層配線用の導体ペーストのＷ粉末の平均粒径
（μｍ）と基板Ｏそシ量（μ慣）／１ＯＨとの関係のグ
ラフである。スルーホール充填用の導体ベース）１．１
のＷ粉末の平均粒径はそれぞれ（１７〜０８μ倶・α９
〜１・５μ洛である。このムライト多層配線基板用導体
ペーストおよびこれを用いたムライト多層配線基板の作
製方法について説明する。Fig. 1 shows an example of the conductor paste for a mullite multilayer wiring board according to the present invention and a mullite multilayer wiring board using the same.W powder of the conductor paste for filling through holes and for surface and inner layer wiring used in forming wiring conductors. It is a graph of the relationship between the average particle diameter (μm) and the substrate O stress amount (μm)/1OH. Conductor base for filling through holes) 1.1
The average particle size of the W powder is (17~08μ/α9), respectively.
~1.5μ Raku. This conductor paste for a mullite multilayer wiring board and a method for manufacturing a mullite multilayer wiring board using the same will be described.
ムライトセラミック基板４の作製は次に示す原料と配合
割合でボールミルを用いて混合してスリップを作製し、
ドクタブレード法によりα２〜（Ｌ５騙厚のシートを作
製した。The mullite ceramic substrate 4 was prepared by mixing the following raw materials and proportions using a ball mill to prepare a slip.
A sheet having a thickness of α2 to (L5) was prepared by the doctor blade method.
トリクロルエチレン ６１ ｗｔ％１ツキにこの
シートをホットプレスで平坦化したのち、ＮＧパンチで
（Ｌ１〜（Ｌ２１ＪＬφのスルーホールを形成した。こ
のシートのスルーホールにスクリーン印刷法でＷ粉末の
導体ペーストを充填して導体２を形成したのち、このシ
ートに表面配線導体３と裏面配線導体と内層配線導体１
を形成するため、目的に合った導体ペーストを用いて配
線−くターンをスクリーン印刷法で形成した。ついでホ
ットプレスにより熱圧着後に、１６４０℃の還元雰囲気
で焼結した。この焼結した基板４０表裏面を研摩剤を内
蔵したブラシ等で研摩して、表面のセラでツク〈ず等を
除去後に、再度サンドブラスト法で表面を粗化してから
、無電解ニッケルめっき法でめっき膜を形成したのち、
７００〜８００℃でクンタを行う。このあとサンドペー
パ等の研摩法によ多導体（メタライズ）のみを平滑にす
る。After flattening this sheet with 61 wt% trichlorethylene using a hot press, through holes of (L1 to (L21JLφ) were formed using an NG punch. A conductive paste of W powder was applied to the through holes of this sheet by screen printing. After filling and forming conductor 2, surface wiring conductor 3, back surface wiring conductor, and inner layer wiring conductor 1 are placed on this sheet.
In order to form the circuit, wiring turns were formed using a screen printing method using a conductive paste suitable for the purpose. Then, after thermocompression bonding using a hot press, sintering was performed in a reducing atmosphere at 1640°C. The front and back surfaces of this sintered substrate 40 are polished with a brush containing an abrasive, etc. to remove scratches, etc. on the surface, and then the surface is roughened again by sandblasting, and then electroless nickel plating is applied. After forming the plating film,
Kunta is performed at 700-800 degrees Celsius. After this, only the multi-conductor (metallized) is smoothed by polishing with sandpaper or the like.
本実施例のスルーホールへの充填用と表面）よび内層配
線用の導体ペーストは次の原料と配合割合でボールミル
・３本ロールミルを用いて作製した。Conductive pastes for filling through holes (for filling through holes, surface) and inner layer wiring were prepared using a ball mill and a three-roll mill using the following raw materials and mixing ratios.
Ｗ粉末 ７９〜８６ −％ビヒクル
１４〜２１ ｗｔ％（エチルセルロー
ズ・ポリビニールブチラール等８〜１２ ｗｔ％を溶剤
とした）
ｎブチルカルピトールアセテート
スルーホールへの充填用の導体ペーストは焼結助剤とゲ
ル化剤をそれぞれペーストに対して（Ｌ５〜３ｔｔ％添
加したものを使用した。W powder 79-86 -% vehicle
14 to 21 wt% (8 to 12 wt% of ethyl cellulose, polyvinyl butyral, etc. used as a solvent) n-butylcarpitol acetate The conductor paste for filling through holes uses a sintering aid and a gelling agent as pastes, respectively. (L5 to 3tt% added) was used.
導体ペーストに用いるＷ粉末の平均粒径は第１図に示す
ように基板４の焼結収縮率に微妙に関係する。つまり平
均粒径α７〜Ｉ１８μ情のＷ粉末を用いたスルーホール
充填用のペースト１と、平均粒径ｌ１ｌＬ９〜１．５３
ｍのＷ粉末を用いたスルーホール充填用のベース）Ｉと
、表面配線導体３シよび内層配線導体１等の配線用のペ
ーストに用いたＷ粉末の平均粒径と、基板４のそう量と
の関係から、スルホール充填用のペースト１．Ｉでは基
板４のそう量の仕様を満足する最適な配線用のペースト
のＷ粉末の平均粒径との組合せが異なる。The average particle size of the W powder used in the conductive paste is delicately related to the sintering shrinkage rate of the substrate 4, as shown in FIG. In other words, paste 1 for through-hole filling using W powder with an average particle size of α7 to I18μ, and paste 1 for filling through holes using W powder with an average particle size of l1L9 to 1.53.
The average particle size of the W powder used in the paste for wiring such as the surface wiring conductor 3 and the inner layer wiring conductor 1, and the amount of the W powder on the substrate 4. From the relationship, paste 1 for filling through holes. In I, the combination with the average particle size of the W powder of the optimum wiring paste that satisfies the specification of the amount of the substrate 4 is different.
よって本実施例ではムライト多層配線基板の配線導体形
式に用いる導体ペーストのＷ粉末の平均粒径として、ス
ルーホール充填用に０７〜＆８μｍｌと配線用に１〜ｔ
５μ情の組合せと、スルーホール充填用にＣＬ９〜Ｌ５
μ情と配線用に（Ｌ８〜５μ情の組合せの導体ペースと
した。またこの組合せの導体ペーストを用いてムライト
多層配線基板を作製するようにした。Therefore, in this example, the average particle size of the W powder of the conductor paste used for the wiring conductor type of the mullite multilayer wiring board is 07~&8μml for through hole filling and 1~t for wiring.
CL9 to L5 for the combination of 5μ and through hole filling
A combination of conductive pastes (L8 to 5 μm) was used for μ conductors and wiring. Also, a mullite multilayer wiring board was manufactured using this combination of conductor pastes.
またスルーホール充填用のベース）１．１とでは、焼結
後のスルーホール部分の導体２と基板４０表面との段差
に差異があう、ベース）Ｉでは１〜３μｍの凸でペース
ト亘では１０〜１５μ鴨の凸である。このためにスルー
ホール充填用のベース）１．１を用いた基板４では焼結
後の平坦化方法を異にした。つまシベース）１を用いた
場合にはスルーホール部分の導体２０表面を８〜１２μ
慣削シ取シ、ペーストＩを用いた場合には基板４そのも
ののそｂｔを小さくするために荷重をかけて再度焼成し
てそシを修正した。In addition, there is a difference in the level difference between the conductor 2 in the through-hole part after sintering and the surface of the substrate 40 in Base) 1.1 for filling through-holes; in Base) I, there is a convexity of 1 to 3 μm, and in the case of Paste, it is 10 μm. ~15μ duck convex. For this reason, the flattening method after sintering was different for the substrate 4 using the base 1.1 for filling through holes. When using Tsumashi base) 1, the surface of the conductor 20 in the through hole part is 8 to 12 μm.
When paste I was used, the thickness of the substrate 4 itself was corrected by applying a load and firing it again in order to reduce the thickness of the substrate 4 itself.
このように基板４０表面を平坦化してから無電解ニッケ
ルめっきで１〜３μ情のニッケル膜を形成し、これをシ
ンタ処理した後に、めっき膜の粒状析出による表面の凹
凸の粗化を修正するために。After flattening the surface of the substrate 40 in this way, a nickel film with a thickness of 1 to 3 μm is formed by electroless nickel plating, and after this is sintered, in order to correct the roughening of the surface irregularities caused by granular precipitation of the plating film. To.
めっき膜上をサンドペーパ等で研摩して平滑した。The plated film was polished and smoothed with sandpaper or the like.
その結果、基板４０そ少量ａはＬＳＩチップ７の搭載部
分では２０μ情以内で、基板４全体では２００μ情以内
になった。また基板４のメタライズ部分の凸は２〜４μ
ｍとなう、メタライズ表面の粗さも１μｓ （Ｒｍａｘ
）で良好であった。この場合にメタライズ部分のみを
研摩することを目的としているため、基板４のセラミッ
クを削る量が少なく、基板内部の空孔８が露出すること
もなかった。As a result, the amount a of the substrate 40 was within 20μ in the area where the LSI chip 7 was mounted, and within 200μ in the entire substrate 4. Also, the convexity of the metallized part of the substrate 4 is 2 to 4 μm.
The roughness of the metallized surface is also 1μs (Rmax
) was in good condition. In this case, since the purpose was to polish only the metallized portion, the amount of ceramic of the substrate 4 to be removed was small, and the holes 8 inside the substrate were not exposed.
本発明によれば、ムライト多層配線基板を平坦に作製で
きるので、はんだ付けによるＬＳＩチップ塔載および薄
膜形成の歩留シを従来の４０％から９５％程度に向上で
きる効果がある。According to the present invention, since a mullite multilayer wiring board can be fabricated flat, the yield of LSI chip mounting and thin film formation by soldering can be improved from 40% to about 95%.
第１図は本発明によるムライト多層配線基板用導体ベー
ス）Ｔｈよびこれを用いたムライト多層配線基板の一実
施例を示すスルーホール充填用と表面および内層配線用
の導体ペーストのＷ粉末の平均粒径と基板のそシ量の関
係のグラフ、第２図は従来のセラミック多層配線基板を
例示する断面図、第３図は第２図の焼結時の基板のそう
の発生を示す断面図、第４図は第２図のラッピング時の
表面配線導体の欠損あるいは基板内部の空孔の露出によ
る欠陥の発生を示す断面図である。
１・・・内層配線導体、２・・・スルーホールに充填さ
れた導体、５・・・内層配線導体、４・・・セラミック
基板、５・・・薄膜層、６−・はんだ層、７・・・ＬＳ
Ｉチップ、８・・・基板内の空孔、ａ・・・そ多量、ｂ
・・・空孔のない層、Ａ−Ａ’・・・研摩で削った面、
■・−・Ｗ粒径α７〜αＢ＃１％のスルーホール充填用
ペースト、Ｉ・・・Ｗ粒径（Ｌ？〜１．５μ情のスルー
ホール充填用ペースト。
第 ２Ｌ￥１
１ 図
蔦 ５図
第 ４回
Ｃ画乙赤果、用へ°−入トノFig. 1 shows an example of the conductor base for a mullite multilayer wiring board (Th) according to the present invention and a mullite multilayer wiring board using the same. A graph of the relationship between the diameter and the amount of deflection of the board, FIG. 2 is a cross-sectional view illustrating a conventional ceramic multilayer wiring board, and FIG. FIG. 4 is a cross-sectional view showing the occurrence of defects due to loss of the surface wiring conductor or exposure of holes inside the substrate during the lapping shown in FIG. 2. DESCRIPTION OF SYMBOLS 1... Inner layer wiring conductor, 2... Conductor filled in through hole, 5... Inner layer wiring conductor, 4... Ceramic substrate, 5... Thin film layer, 6-... Solder layer, 7...・・LS
I chip, 8...vacancies in the substrate, a...amount, b
... Layer without pores, A-A' ... Polished surface,
■...Paste for filling through holes with W grain size α7~αB#1%, I...Paste for filling through holes with W grain size (L?~1.5μ). 2nd L￥1 1 Figure Tsuta 5 Figure No. 4
Claims (4)
体ペーストのタングステン粉末の平均粒径を、スルーホ
ール充填用に０．７〜０．８μｍとし、配線用に１〜１
．５μｍとしたムライト多層配線基板用導体ペースト。1. The average particle size of the tungsten powder in the conductor paste used for forming wiring conductors on a mullite multilayer wiring board is 0.7 to 0.8 μm for through-hole filling, and 1 to 1 μm for wiring.
．． Conductive paste for mullite multilayer wiring boards with a thickness of 5 μm.
体ペーストのタングステン粉末の平均粒径を、スルーホ
ール充填用に０．９〜１．５μｍとし、配線用に０．８
〜３μｍとしたムライト多層配線基板用導体ペースト。2. The average particle diameter of the tungsten powder in the conductor paste used to form wiring conductors on a mullite multilayer wiring board is 0.9 to 1.5 μm for through-hole filling, and 0.8 μm for wiring.
A conductive paste for mullite multilayer wiring boards with a thickness of ~3 μm.
いて配線導体形成したムライト多層配線基板。3. A mullite multilayer wiring board in which wiring conductors are formed using the conductive paste according to claim 1 or 2.
解めっき後にシンタした基板のメタライズ部分のみを研
摩により平滑にしたムライト多層配線基板。4. The mullite multilayer wiring board according to claim 3, and a mullite multilayer wiring board in which only the metallized portion of the board sintered after electroless plating is smoothed by polishing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20463889A JPH0369190A (en) | 1989-08-09 | 1989-08-09 | Conductor paste for mullite multi-layer wiring board and mullite multi-layer wiring board using it |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20463889A JPH0369190A (en) | 1989-08-09 | 1989-08-09 | Conductor paste for mullite multi-layer wiring board and mullite multi-layer wiring board using it |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0369190A true JPH0369190A (en) | 1991-03-25 |
Family
ID=16493794
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20463889A Pending JPH0369190A (en) | 1989-08-09 | 1989-08-09 | Conductor paste for mullite multi-layer wiring board and mullite multi-layer wiring board using it |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0369190A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006331016A (en) * | 2005-05-25 | 2006-12-07 | Koha Co Ltd | Lighting system for article for display and vending machine equipped with the same |
| JP2008075278A (en) * | 2006-09-19 | 2008-04-03 | Giken Seisakusho Co Ltd | Excavating claw and auger head |
-
1989
- 1989-08-09 JP JP20463889A patent/JPH0369190A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006331016A (en) * | 2005-05-25 | 2006-12-07 | Koha Co Ltd | Lighting system for article for display and vending machine equipped with the same |
| JP2008075278A (en) * | 2006-09-19 | 2008-04-03 | Giken Seisakusho Co Ltd | Excavating claw and auger head |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0609861B1 (en) | Ceramic substrate and manufacturing method thereof | |
| JP3015621B2 (en) | Conductive paste composition | |
| US5787578A (en) | Method of selectively depositing a metallic layer on a ceramic substrate | |
| EP0905775A2 (en) | Electrically conductive paste for via-hole and method of producing monolithic ceramic substrate using the same | |
| JPH0369190A (en) | Conductor paste for mullite multi-layer wiring board and mullite multi-layer wiring board using it | |
| JP3354221B2 (en) | Method of forming bump electrode | |
| JPH0613755A (en) | Ceramic multilayer wiring board and manufacture thereof | |
| JPS6010696A (en) | Method of producing thin film ceramic circuit board | |
| JP3909196B2 (en) | Manufacturing method of glass ceramic substrate | |
| JP4518634B2 (en) | Manufacturing method of glass ceramic substrate | |
| JP3909186B2 (en) | Manufacturing method of glass ceramic substrate | |
| JP3171695B2 (en) | Manufacturing method of aluminum nitride circuit board | |
| JP3909189B2 (en) | Manufacturing method of glass ceramic substrate | |
| JPH06204645A (en) | Manufacture of ceramic circuit board | |
| JP3872289B2 (en) | Manufacturing method of glass ceramic substrate | |
| JP3909200B2 (en) | Manufacturing method of glass ceramic substrate | |
| JP3909201B2 (en) | Manufacturing method of glass ceramic substrate | |
| JP2004146701A (en) | Method for manufacturing glass ceramic substrate | |
| EP0269063A2 (en) | Mullite ceramic multi-layered substrate and process for producing the same | |
| JP3242459B2 (en) | Manufacturing method of ceramic wiring board | |
| JP3909182B2 (en) | Manufacturing method of glass ceramic substrate | |
| JP3282893B2 (en) | Method of forming bump electrodes on ceramic substrate | |
| JP3811381B2 (en) | Manufacturing method of glass ceramic substrate | |
| JP3241945B2 (en) | Glass ceramic multilayer circuit board and method of manufacturing the same | |
| JP3872284B2 (en) | Manufacturing method of glass ceramic substrate |