JPH0369166A - Manufacture of mos semiconductor element - Google Patents

Abstract

PURPOSE:To form a reverse taper surely below a gate edge, to relax field concentration and to improve the gate breakdown strength by oxidizing a gate electrode consisting of polycrystalline silicon, etc., whose impurity concentration is higher in an upper part than in a lower part and by forming a sidewall oxide film which corresponds to the distribution of impurity concentration. CONSTITUTION:A gate electrode 13 consists of polycrystalline or amorphous silicon having a specified distribution whose concentration of conductive impurity contact is higher in a lower part 13a than in an upper part 13b. The gate electrode 13 is formed on a semiconductor substrate 10 through an oxide film 12. Then, the gate electrode 13 is oxidized to form side wall oxide films 16, 17 having a film thickness corresponding to concentration distribution of the said conductive impurity onto the sidewall of the gate electrode 13. For example, after a polycrystalline Si gate 13 is formed which consists of high concentration phosphorus content layer 13a and a low concentration phosphorus content layer 13b, n-type impurity is doped to form an n-type high concentration source/drain region 11. Then, a polycrystalline Si gate 13 is thermally oxidized by wet oxidation at 750 deg.C to form an oxide film on the upper side and the sidewall of the polycrystalline Si gate 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a MOS type semiconductor device.

[Conventional technology]

As devices become smaller due to demands for higher integration, the thickness of gate oxide films in MO3 type semiconductor elements such as MOSFETs tends to become extremely thin. Therefore, the electric field strength applied to the gate oxide film increases, and the resulting dielectric breakdown of the gate oxide film becomes an unavoidable problem in MO3 type semiconductor devices. In particular, at the end of the gate electrode (point A in FIG. 6), since the shape of the gate electrode is steep, electric field concentration tends to occur, and dielectric breakdown of the gate oxide film at this part is very likely to occur. It has become a thing. Note that FIG. 6 shows a conventional n-channel MO3FE.
1 is a schematic cross-sectional view of T, where lO is a p-region formed on a single-crystal silicon substrate, 11 is an n-type high concentration source/drain region, 12 is a gate oxide film, and 13 is a gate electrode made of polysilicon (hereinafter referred to as polysilicon gate). ), 14
15 is a high concentration source/drain region 11.
and A electrically connected to polysi gate 13
This is ffi wiring.

[Problem to be solved by the invention]

In view of the above points, the present invention provides, for example, an n-channel M as shown in FIG.
As shown in O3FET, the end (A part) of the gate electrode (polysi gate) 13 is made into an inverted tapered shape, and this A
By increasing the thickness of the gate oxide film 12 in the region, the gate electrode 13 and the high concentration source/drain region 1 can be thickened.
Focusing on the fact that the electric field between 1 and 1 is relaxed, thereby relaxing the electric field concentration at the gate end A and improving the gate breakdown voltage, it is possible to reliably produce an MO3 type semiconductor device having the above structure. An object of the present invention is to provide a method for manufacturing an MO3 type semiconductor device that can be manufactured using the following methods.

[Means to solve the problem]

In order to achieve the above object, the present invention utilizes the dependence of the oxidation rate on the impurity concentration in polySi in thermal oxidation of polySi, and actively increases the thickness of the sidewall oxide film in the gate thickness direction on the gate sidewall. By changing
This is intended to reliably form an inverted taper at the lower part of the gate end.

As shown in the characteristic diagram of the relationship between oxide film thickness and impurity concentration in thermal oxidation of polysi in Figure 2, for example, the impurity concentration IX10'' (cm-3) and lXl0'' (c
l') has an oxidation rate ratio of about 8 times.

That is, in the invention according to claim 1, a gate electrode made of polycrystalline or amorphous silicon having a predetermined distribution in which the concentration of conductive impurities is higher in the lower part than in the upper part is attached to the semiconductor substrate through an oxide film. and a gate oxidation step of oxidizing the gate electrode to form a sidewall oxide film having a thickness corresponding to the concentration distribution of the conductive impurity on the sidewalls of the gate electrode. The technical means of manufacturing MO3 type semiconductor devices will be adopted.

[Action and effect]

As mentioned above, the oxidation rate of polySi depends on the concentration of impurities contained in polySi, so in the gate formation process, the concentration of conductive impurities is high in the lower part of the polySi gate, and the impurity concentration is lowered toward the top. If formed in this way, the sidewall oxide film (Sin film) will be formed thickly under the gate in the gate oxidation process as shown in FIG.
The Si gate will be shaved off at the lower end A. That is, according to the manufacturing method of the present invention, it is possible to reliably form an inverted taper at the lower part of the gate end, and to reduce the electric field concentration at the gate end, thereby improving the gate breakdown voltage. It has the excellent effect of being able to provide

〔Example〕

Hereinafter, the present invention will be explained based on embodiments shown in the drawings.

FIGS. 3(a) to 3(f) are cross-sectional views showing the manufacturing steps of an n-channel MO3FET to which an embodiment of the present invention is applied.

Refer to FIG. 3(a). First, an oxide film 12 is formed on the surface of a p-type single crystal silicon substrate 10.
is deposited to form a gate oxide film, and polysiN 13a' containing a high concentration of phosphorus is deposited as a first polysilicon layer on this gate oxide film 12 by low pressure CVD.

As a means of making polysilii contain phosphorus,
There is a method in which phosphorus is diffused after depositing a non-doped P01ySi layer, or a method in which phosphorus is contained at the same time as the polysi layer is deposited. Note that the latter is, for example, PH.

The polysilicon layer is deposited under a dopant gas atmosphere such as

Refer to FIG. 3(b) Next, the first pO1ysi containing this high concentration of phosphorus is
A polysi layer 13b' containing low concentration of phosphorus or non-doped as a second polysi layer on top of the layer 13a'
It is deposited by interlayer 3b' pressure CVD method.

If the process shown in FIG. 3(a) involves depositing a polySi layer in a dopant gas atmosphere, once polySiN containing a fairly high concentration of phosphorus is deposited, the dopant gas supply is cut off and the process is continued. polysi
When the layers are deposited, polysilicon layers with different phosphorus contents are deposited at the top and bottom.

Referring to FIG. 3(C), a resist 2 is then applied on the second polysilicon layer 13b'.
After applying 0 and buttering this, the second pol
The ysi layer 13b and the first polySi layer 13a' are successively anisotropically etched.

Then, as shown in the figure, a polysi gate 13 consisting of a high concentration phosphorus-containing JW 13a and a low concentration phosphorus-containing (or non-doped) layer 13b is formed.

See Figure 3(d) Next, after peeling off the resist 20, this p.

Using the IySi gate 13 as a mask, n-type impurities are doped to form n-type heavily doped source/drain regions 11 in self-alignment with the polysi gate 13.

Refer to FIG. 3(e). Next, the polysi gate 13 is rotated at an angle of, for example, 750°.
C is thermally oxidized by wet oxidation to form an oxide film on the top surface and sidewalls of the potySi gate 13. At this time, p
Since the phosphorus content differs between the upper and lower parts of the polysi gate 13, the oxidation rate of polysi depends on the phosphorus concentration as described above.
aJt! That is, the thickness of the sidewall oxide film 16 at the bottom of the polySi gate becomes thicker, while the thickness of the sidewall oxide film 17 at the upper part (layer 13b) of the polySi gate with a low concentration of phosphorus content becomes thinner. .

Refer to FIG. 3(f). Thereafter, the interlayer insulating film 14 is shaped using a normal manufacturing method, contact holes are opened, and predetermined /M2 wirings 15 are formed.
was formed to manufacture the n-channel MO3FET shown in the figure.

As shown in FIG. 3(f), in the thickness direction of the polysilicon gate 13, the sidewall oxide film has a distribution such that the upper part 17 is thinner and the lower part 6 is thicker, so the cross-sectional shape of the polysilicon gate 13 is at the edge. It becomes an inverted tapered shape at the end. That is, the film thickness of the gate oxide film 12 at the gate end becomes thicker, and the fringe electric field between the polySi gate 13 and the heavily doped source/drain region 11 is relaxed. Therefore, electric field concentration at the gate end is alleviated, and gate breakdown voltage can be improved.

Next, by applying the present invention, LDD (Lightly Do
An example of manufacturing an n-channel MO3FET with a pedDrain structure will be described with reference to FIGS. 4(a) to 4(e).

Refer to FIG. 4(a) First, in the same manner as the steps shown in FIGS. 3(a) to (C),
A polysi gate 13 consisting of a layer 13a with a high concentration of phosphorus and a layer 13b with a low concentration of phosphorus was formed on a p-type silicon substrate 10 with a gate oxide film 12 interposed therebetween.

Refer to FIG. 4(b) Next, using this polysilicon gate 13 as a mask, the p-type silicon substrate 10 is doped with n-type impurities to form polysilicon.
N-type low concentration source/drain regions 21 were formed in self-alignment with the i-gate 13.

See Figure 4 (C) Subsequently, p is carried out in the same manner as the step shown in FIG. 3(e).

The IySi gate 13 is thermally oxidized, and the polysi gate 1 is
3. Form an oxide film on the top and sidewalls.

At this time, as described above, in the thickness direction of the polys gate 13, the sidewall oxide film is thinner in the upper part 17 and thinner in the lower part 17.
6 is formed to have a large film thickness, and the lower part (layer 13a) of polySi gate 1-13 is shaved off by the oxide film, resulting in an inverted tapered shape.

Refer to FIG. 4(d) Next, using the polysilicon gate 13 and the sidewall oxide film 16 as a mask, the P-type silicon substrate 10 is doped with n-type impurities at a high concentration, and the n-type impurity is doped in a self-aligned manner with the sidewall oxide film 16. Concentrated source/drain regions 11 were formed.

Refer to FIG. 4(e). Then, by a normal manufacturing method, an interlayer insulating film 14 is formed, a contact hole is opened, and a predetermined Af wiring 15 is formed.
ET was manufactured.

LDD structure n-channel MO3FET shown in FIG. 4(e)
Also, the same effect as the n-channel MO3FET shown in FIG. 3(f) can be obtained. That is, polysi gate 13
Since the cross-sectional shape of the gate oxide film 12 becomes inversely tapered at the end, the thickness of the gate oxide film 12 at the gate end becomes thicker.
Electric field concentration at the gate end can be alleviated, and the lateral electric field intensity relaxation between the source and drain by the lightly doped drain region 21 can be further improved.

In addition, by forming a lightly doped drain region as described above, the LDT (LDT) structure alleviates the lateral spreading electric field between the source and drain when a voltage is applied, and prevents avalanche breakdown and hot carriers (which gain energy from the electric field). However, if the impurity concentration in the low-concentration drain region is lowered to enhance the electric field relaxation effect of this LDD structure, conversely, especially in the early stage of the stress period, It has been reported that (in the initial stage of high voltage application), significant deterioration in device characteristics appears due to hot carriers injected into the sidewall oxide film formed on the sidewalls of the gate electrode.

This is because the position where the electric field strength is maximum in the LDD structure is on the lightly doped drain region, and hot carriers are injected and trapped in the sidewall oxide film on this region, thereby forming an electric field due to negative charges. This is because the resistance of the lightly doped drain region increases. That is,
This parasitic resistance causes a decrease in drain current.

However, as shown in FIG. 4(e), the LDD structure MO3FET according to the present invention has a po
polysi formed during oxidation of lysi gate 13
Due to the thickness of the oxide film 16 on the gate sidewall, the sidewall oxide film can be used as a sidewall, and the electric field strength for injecting the generated hot carriers into the oxide film is relaxed, and the hot carriers are injected into the oxide film. Since the injection is suppressed, deterioration of the above-mentioned device characteristics can be prevented.

In addition, in FIGS. 3 and 4 above, n-channel MO
Although the manufacturing method of the present invention has been described using an SFET as an example, the present invention is not limited to this, and the present invention can be applied to MO3 type semiconductor devices such as p-channel MO3FETs and capacitors.

In addition, in the above manufacturing method, in forming the gate electrode,
Although polysilicon was deposited in the previous embodiment, amorphous silicon may also be used, and this material becomes polysilicon during the process of thermally oxidizing the polysilicon gate.

Further, although phosphorus is used as the impurity diffused into the polysi layer, the present invention is not limited to this, and other conductive impurities may be used.

In addition, in the above manufacturing method, the lower end of the polysi gate is cut into the sidewall oxide film and formed in a reverse tapered shape, but it is also possible to make it rounded by giving a distribution to the phosphorus content. It is possible.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view showing the basic structure of an MO3 type semiconductor device according to the present invention, Fig. 2 is a characteristic diagram showing the relationship between oxide film thickness and impurity concentration in thermal oxidation of polycrystalline Si, and Figs.
(f) is an n-channel MO3F to which an embodiment of the present invention is applied
4(a) to 4(e) are sectional views in the order of manufacturing steps of an ET. FIG. 4(a) to (e) are sectional views in the order of the manufacturing steps of an n-channel LDD structure MO3FET according to the present invention. FIG. FIG. 6 is a cross-sectional view of a conventional n-channel MO3FET in which the lower end of the D1-electrode has a steep shape. DESCRIPTION OF SYMBOLS 10...Substrate, 11...High concentration source/drain region, 12...Gate oxide film, 13...Polysi
Gate, 13a...High concentration phosphorus containing layer as a first gate electrode layer, 13b...Low concentration phosphorus containing layer as a second gate electrode layer, 16.17...Side wall oxide film. 21: Low concentration source/drain region, A: Lower end portion of gate electrode.

Claims (3)

[Claims] (1) A gate formation process in which a gate electrode made of polycrystalline or amorphous silicon having a predetermined distribution in which the concentration of conductive impurities is higher in the lower part than in the upper part is formed on the semiconductor substrate via an oxide film. and a gate oxidation step of oxidizing the gate electrode to form a sidewall oxide film on the sidewalls of the gate electrode with a thickness corresponding to the concentration distribution of the conductive impurity. A method for manufacturing semiconductor devices. (2) In the gate forming step, a first gate electrode layer made of a polycrystalline or amorphous silicon film in which conductive impurities are diffused at a high concentration is deposited on the oxide film, and a first gate electrode layer is deposited on the oxide film. A second gate electrode layer made of a polycrystalline or amorphous silicon film with conductive impurities diffused at a low concentration is deposited on the substrate, and then the second and first gate electrode layers are etched leaving a predetermined region. 2. The method of manufacturing a MOS type semiconductor device according to claim 1, wherein the gate electrode is formed by using a MOS semiconductor device. (3) The method for manufacturing a MOS type semiconductor device according to claim 1 or 2, wherein the conductive impurity is phosphorus.