JPH0366168A - Field-effect type semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To largely suppress an injection amount, into a source junction, of majority carriers which cause a parasitic bipolar effect and to largely improve a breakdown strength between a drain and a source by a method wherein a high impurity- concentration layer whose conductivity type is the same as that of an active layer is formed so as to be adjacent to a drain junction and a drain voltage is applied to the layer. CONSTITUTION:A semiconductor metal compound layer 31 such as titanium silicide or the like is arranged on an n<+> type source region 16 and a p<+> type source region 17; a semiconductor metal compound layer 32 such as the titanium silicide or the like is arranged on an n<+> type drain region 18 and a p<+> type drain region 19; in addition, a semiconductor metal compound layer 33 is arranged in a gate electrode 15; the n<+> type source region 16 and the p<+> type source region 17 are connected mutually by using a source electrode 21 via the semiconductor metal compound layer 31. When the semiconductor metal compound layers 31, 32, 33 are formed respectively on the source and drain regions and on the gate electrode, a parasitic resistance of the source and drain can be reduced relatively. Consequently, a high-speed operation of a semiconductor device can be promoted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field-effect semiconductor device that enables high-speed operation and high-pressure operation, and a method for manufacturing the same.

[Prior Art] An example of a conventional field effect semiconductor device is shown in FIG. 12 and will be described. FIG. 12 (B'+ is a cross-sectional view of this semiconductor device, 1 is a single crystal semiconductor substrate, 2 is a first conductivity type, for example, p-type, for electrically insulating the active layer 3 and the semiconductor substrate 1. 4 is a gate insulating film, 5 is a source region of a second conductivity type, for example, an n-type, 6 is a drain region of a second conductivity type, for example, an n-type, 7 is a gate electrode, and 8 is an electrical connection between wirings. An insulating film for insulation, 9 a source electrode, and 10 a drain electrode.

In this type of semiconductor device, the impurity concentration of the active layer 3 is designed so that the thickness of the depletion layer that can spread from the gate electrode 7 side is thicker than the thickness tst of the active layer 3, and the semiconductor device operates. The structure is such that the entire region of the active layer 3 is sometimes depleted. The reason for this configuration is (1) to suppress deterioration of the mobility of carriers in the inversion layer directly under the gate insulating film by reducing the effective electric field strength in the active layer, thereby increasing the drain current; : This is because it is possible to increase the drain current by increasing the number of carriers in the inversion layer corresponding to the decrease in the amount of charge in the depletion layer in the active layer. Furthermore, in the semiconductor device having this configuration, since the inside of the active layer is depleted by the gate electric field, the penetration of the drain electric field from the drain junction into the active layer can be suppressed, and the short channel effect of the threshold voltage can be suppressed. Therefore, this type of semiconductor device can be expected to achieve both high integration and high-speed operation due to miniaturization of dimensions, and its future potential has been attracting attention in recent years.

However, it has recently become clear that this type of semiconductor device has a drain-source breakdown voltage that is lower than the normally expected value. FIG. 12(b) shows an example of the drain voltage/drain current characteristics of this type of semiconductor device with a gate length of 0.5 μm.

In a conventional semiconductor device, when the gate length is 0.5 μm, the drain-source breakdown voltage is about 5 to 6 μm. On the other hand, in this type of semiconductor device, a breakdown voltage of only about 3 .ANG. is obtained.

The reason for this is thought to be a parasitic bipolar effect originating from the structure. This will be explained using FIG. 13. 1st
FIG. 3 shows an example of an n-channel type semiconductor device. This type of semiconductor device is normally operated by grounding the semiconductor substrate 1 and the source electrode 9, and applying a positive voltage to the gate electrode 7 and the drain electrode 10. When the drain voltage ■9 becomes high,
Electrons due to weak avalanche phenomenon near the drain junction
Hole pairs begin to be generated. Of these, the electron O is in the drain. ''!, but the holes ■ move to the vicinity of the interface between the active layer 3 and the lower insulating film 2, which has the lowest potential in the active layer as seen from the hole.After the holes are collected here, the drain electric field Correspondingly, a large amount of electrons are injected back into the active layer 3 from the source region 5.

The amount is approximately [amount of injected holes] x [source impurity concentration]/[active layer impurity concentration]. Some of the reversely injected electrons flow into the drain junction while inducing a new avalanche phenomenon near the drain junction. Since this is a positive feedback phenomenon, the drain current suddenly increases and the drain-source breakdown voltage decreases.

[Problems to be solved by the invention 1 to 1] As described above, this type of field-effect semiconductor device has great features such as high integration and high-speed operation due to miniaturization of the dimensions, but at the same time does not meet the above-mentioned problems. drain like
It has not yet been put into practical use due to the problem of reduced pressure resistance between sources.

The present invention has been made in view of the above points, and its purpose is to dramatically improve the drop in breakdown voltage between the drain and source, which has been a problem in conventional semiconductor devices, and to improve the ability to operate under high power supply voltages. An object of the present invention is to provide a field effect semiconductor device capable of high-speed operation and a method for manufacturing the same.

[Means to solve the problem]

In order to achieve the above object, a field effect semiconductor device according to the present invention includes a semiconductor active layer of a first conductivity type that is thinner than the thickness of a depletion layer that extends at least directly below a gate insulating film, and a gate electrode. A source region of a first conductivity type disposed on one side of the partitioned semiconductor active layer and a source region of a second conductivity type whose upper surface position level is higher than the position level of the bottom surface of the gate electrode, and a first source region disposed on the other side. A drain region of a conductivity type and a drain region of a second conductivity type whose top surface is higher than a bottom surface of the gate electrode, and a source region of the second conductivity type and a source region of the first conductivity type are mutually connected. The device is characterized in that it has a connected source electrode, and a drain electrode that connects the second conductivity type drain region and the first conductivity type drain region to each other.

That is, in the first aspect of the present invention, the gate structure is a recessed gate structure, the active layer is a semiconductor active layer of the first conductivity type that is thinner than the thickness of the depletion layer that can spread directly under the gate insulating film, and the source region A high impurity concentration region of the same conductivity type as the semiconductor active layer is provided in a part of or adjacent to the semiconductor active layer, and wiring is provided so that this and the source region of the second conductivity type are at the same potential. A high impurity concentration region of the same conductivity type as the semiconductor active layer is provided at or adjacent to the semiconductor active layer, and wiring is provided so that this and a drain region of a second conductivity type are at the same potential.

tyc, the manufacturing method according to the second aspect of the present invention includes a first insulating layer embedded in a semiconductor and a first semiconductor layer having a first conductivity type on the first insulating layer. forming a groove on the first semiconductor layer on the main surface of the semiconductor substrate; forming a second insulating film as a gate insulating film in the line groove;
A source region of a second conductivity type and a drain region of a second conductivity type are provided on both the gate electrode formed on the second insulating film and the first semiconductor layer separated in plane by the gate electrode, respectively. The semiconductor layer is formed so that its bottom surface does not touch the first insulating layer, and the first semiconductor layer separated in plan by the gate electrode has a semiconductor layer having an impurity concentration of the first conductivity type. forming a source region of a first conductivity type and a drain region of a first conductivity type higher than the impurity concentration of the active layer; forming contact holes on the drain region of the first conductivity type and the drain region of the second conductivity type, respectively, and connecting them on the source region of the first conductivity type and the source region of the second conductivity type; An electrode is formed on the drain region of the first conductivity type and on the second conductivity type drain region.
The method is characterized in that it includes a step of forming an electrode on the conductive type drain region to connect them.

Further, in the third aspect of the present invention, in the first aspect, the first semiconductor metal compound is arranged in one or both directions of the source region of the first conductivity type or the source region of the second conductivity type. a second semiconductor metal compound layer disposed on one or both of the drain region of the first conductivity type and the drain region of the second conductivity type;
The source regions of the conductivity type are connected to each other by a source electrode via the first semiconductor metal compound layer, and the drain region of the second conductivity type and the drain region of the first conductivity type are connected to each other by a second semiconductor metal compound layer. The drain electrodes are connected to each other via the drain electrodes.

In the manufacturing method according to the fourth aspect of the present invention, in the second aspect, a semiconductor metal compound layer is provided in one or both of the source region of the first conductivity type and the source region of the second conductivity type. and forming a semiconductor metal compound layer on one or both of the drain region of the first conductivity type and the drain region of the second conductivity type; A source region of a second conductivity type and a drain region of a first conductivity type are connected to each other by a source electrode via the semiconductor metal compound layer, and a drain region of a second conductivity type and a drain region of the first conductivity type are connected to each other through the semiconductor metal compound layer. This is characterized by mutual connection through electrodes.

Furthermore, a fifth aspect of the present invention provides a semiconductor active layer of a first conductivity type thinner than the thickness of a depletion layer that can spread at least directly below a gate insulating film, and one of the semiconductor active layers partitioned by a gate electrode. has a second conductivity type source region whose top surface is higher than the bottom surface of the gate electrode, and a second conductivity type source region whose top surface is higher than the bottom surface of the gate electrode. a source electrode having a drain region of the second conductivity type and interconnecting the source region of the second conductivity type and the semiconductor active layer of the first conductivity type in the vicinity of the source region; It is characterized by having a drain electrode that interconnects the semiconductor active layer of the first conductivity type in the vicinity of the drain region. That is, in the fifth invention, the gate structure is a recessed gate structure, and its active layer is composed of a semiconductor active layer of the first conductivity type that is thinner than the thickness of the depletion layer, which is spread directly under the gate insulating film, and is formed in the source region. In order to bring the adjacent region of the active layer of the first conductivity type to the same potential as the source region of the second conductivity type, an electrode is wired across the circumferential region, and the electrode of the active layer of the first conductivity type adjacent to the drain region is wired across the peripheral region. In order to make the region the same potential as the drain region of the second conductivity type,
The electrodes are wired across the circumferential area.

In the manufacturing method according to the sixth aspect of the present invention, a first insulating layer is embedded in a semiconductor, and a first semiconductor layer having a first conductivity type is formed on the first insulating layer. forming a groove on the first semiconductor layer on the main surface of the semiconductor substrate, forming a second insulating film in the line groove, and forming a gate electrode on the second insulating film; , a source region of a second conductivity type and a drain region of a second conductivity type are respectively placed on both sides of the first semiconductor layer which are separated in plane by the gate electrode so that their bottom surfaces are in contact with the first insulating layer. contact holes are respectively formed on the source region of the second conductivity type and on the semiconductor active layer of the first conductivity type in the vicinity of the source region; A contact hole is formed on the semiconductor active layer of the first conductivity type near the drain region, and a contact hole is formed on the source region of the second conductivity type and the first conductivity type near the source region. forming an electrode interconnecting the semiconductor active layer through a contact hole on the semiconductor active layer, and forming a contact hole on the second conductivity type drain region and a first conductivity type semiconductor near the drain region. The active layer is characterized in that it includes a contact hole on the active layer to form an electrode that interconnects the active layer through the contact hole.

In addition, a seventh aspect of the present invention is, in the fifth aspect, disposed in at least one or both of the source region of the second conductivity type or the semiconductor active layer of the first conductivity type in the vicinity of the source region. a second semiconductor metal compound layer disposed on one or both of the drain region of the second conductivity type or the semiconductor active layer of the first conductivity type in the vicinity thereof; A source region of a second conductivity type and a semiconductor active layer of a first conductivity type in the vicinity of the source region are interconnected by a source electrode via a first semiconductor metal compound layer, and a drain region of a second conductivity type is connected to each other by a source electrode. and a semiconductor active layer of the first conductivity type in the vicinity of the drain region are interconnected to a drain electrode via a second semiconductor metal compound layer.

Furthermore, in the manufacturing method according to the eighth aspect of the present invention, in the sixth aspect, a semiconductor is provided in one or both of the source region of the second conductivity type or the semiconductor active layer of the first conductivity type in the vicinity thereof. forming a metal compound layer, and forming a semiconductor metal compound layer on one or both of the drain region of the second conductivity type or the semiconductor active layer of the first conductivity type in the vicinity thereof; A source region of a shape and a semiconductor active layer of a first conductivity type in the vicinity of the source region are interconnected by an electrode via the semiconductor metal compound layer, and a drain region of a second conductivity type and a semiconductor active layer of a first conductivity type in the vicinity of the drain region are connected to each other by an electrode. The semiconductor active layer of the first conductivity type is interconnected by an electrode via the semiconductor metal compound layer.

[For production]

Therefore, the first aspect of the present invention. In the second invention, almost all of the carriers of the first conductivity type among the electron-hole pairs generated near the drain junction are absorbed into the high impurity concentration region of the first conductivity type on the drain side, so that parasitic Since the bipolar effect can be removed and a recessed gate structure is used as the gate structure, the short channel effect can be alleviated.

'4! In addition, the third aspect of the present invention. In the fourth aspect of the invention, by using a semiconductor metal compound on the source and drain regions, the first aspect of the invention is achieved. In addition to the effect of the second invention, the parasitic resistance of each source and drain can be relatively reduced.

Furthermore, the fifth aspect of the present invention. In the sixth invention, almost all of the carriers of the first conductivity type among the electron-hole pairs generated near the drain junction are absorbed into the drain electrode through the active layer of the first conductivity type on the drain side. In order to Similar to the second invention, the parasitic bipolar effect can be removed, and since the recessed gate structure is used as the gate structure, the short channel effect can be alleviated.

ffC, 7th aspect of the present invention. In the eighth invention, by providing a semiconductor metal compound on the source and drain regions, the fifth invention described above. In addition to the effect of the sixth invention, it is possible to relatively reduce the parasitic resistance of each source and drain.

〔Example〕

Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings.

Embodiment 1 FIG. 1 shows a cross-sectional view of an n-channel field effect semiconductor device according to an embodiment of the present invention.

11 is a single crystal semiconductor substrate; 12 is an insulating film as an insulator layer for electrically insulating the semiconductor substrate 11 from the active layer 13 of a first conductivity type, for example, p-type; 14 is a gate insulating film;
5 is a gate electrode; 16 is a source region of a second conductivity type, for example, an n-type; 17 is a source region of a first conductivity type, for example, a p-type;
Reference numeral 18 denotes a drain region of a second conductivity type, for example, an n-type, 19 a drain region of a first conductivity type, for example, a p-type, 20 an insulating film for electrically insulating between wirings, and 21 a source region of an n-type. 16 is a source electrode in contact with the p-type source region 1T, and 22 is a drain electrode in contact with the n-type drain region 18 and the n-type drain region 19.

However, in FIG. 1, the thickness t82 of the active layer 13 is designed to be thinner than the thickness of the depletion layer that can spread from directly under the gate insulating film.

That is, the n-channel type semiconductor device of this embodiment is an insulating gate in which a gate electrode 15 is formed on an active layer 13 formed on an upper part of an insulating film 12 with a gate insulating film 14 interposed therebetween;
In the gate structure, the gate insulating film 14 is used as the active layer.
A p-type active layer 13 with a very thin depletion layer that can spread directly below is provided, and a p-type source region 17 and an upper surface position level are provided on one side of the active layer 13 partitioned by the gate electrode 15. An n-type source region 16 whose position level is higher than that of the bottom surface of the gate electrode 15 is arranged, and an n-type drain region 19 on the other hand and a position level of the upper surface of which is higher than the gate electrode 1.
The n-type drain region 18 is higher than the position level of the bottom surface of 5.
Place each. The n+ type source region 16 and the p++ type source region 17 are connected to each other by a source electrode 21, and the n+ type drain region 1B and the n+ type drain region 19 are connected to each other by a drain electrode 22. It was designed to connect.

Next, the operation of the embodiment of the field effect semiconductor device of the present invention shown in FIG. 1 will be explained using FIG. 2.

In the device of this embodiment, the semiconductor substrate 11 and the source electrode 21 are grounded, and the gate electrode 15 and the drain electrode 22 are grounded.
Apply an appropriate Z positive voltage to. However, in this semiconductor device, when the gate voltage is Ov, the active layer 1 directly under the gate
The impurity concentration, etc. of the active layer is designed in advance so that 3 is depleted by 1 from directly below the gate to the lower insulating film 12. In each figure, the shaded area in the active layer 13 represents a depletion region.

However, the drain voltage ■. As the voltage becomes high, electron-hole pairs O begin to occur near the drain junction due to a weak avalanche phenomenon, similar to conventional semiconductor devices. Of these, electrons O directly flow into the drain. On the other hand, in the semiconductor device of the present invention in which the n-domain drain region 18 and the p-domain drain region 19 are arranged in parallel at the same potential, the increase in the electric field strength near the n-domain drain region 18 increases 1
suppressed by the presence of 9. In other words, since the nx type drain region 18 and the p+ drain region 19 are at the same potential, the thickness of the depletion layer that spreads from the nx type drain region 18 toward the semiconductor active layer 13 is significantly suppressed. . Therefore, the electric field strength within the depletion layer of the drain junction is significantly reduced.

Further, although the direction of motion of the holes (2) generated by the avalanche phenomenon is stochastically equal, the energy is extremely high at 3 to 5 eV.

For this reason, there is a high probability that the generated holes will be captured by the p-type drain region 19, which has a slightly higher potential but is close in distance. As a result, the active layer 13 and the lower insulating film 1
The amount of holes moving to the source side via the vicinity of the interface 2 is significantly reduced. Moreover, even if some holes move to the source side, these holes are transferred to the p-type source region 1.
7, the amount of holes injected into the n+ type source region 16 is extremely small. Therefore, deterioration in drain-source breakdown voltage due to the parasitic bipolar effect can be effectively eliminated.

Furthermore, most of the leakage current between the drain and source, which has conventionally been a problem in this type of semiconductor device, is the hole current flowing from the vicinity of the drain toward the source. In the device of the present invention, most of these holes flow into the p-type drain region 19, so that they are separated after generation and cancel out the current of electrons flowing into the n-type drain region 18. As a result, the hole current flowing to the source is reduced, which is also effective in reducing drain-source leakage current.

In addition, in FIG. 2, p 10 type drain region 1g or p
The lower portion of the 10-shaped source region 17 may be in contact with the lower insulating film 12. Further, the impurity concentration of either the source region 1T or the drain region 19 may be higher than the impurity concentration of the active layer 13 of the first conductivity type. In addition, the impurity concentration of the active layer 131 under the n-type drain region 18 is increased so that the depletion layer spreading in this region often reaches the lower insulating film 12, and the non-depleted region is By configuring it so that it exists in the lower part 131 of the shaped drain region 18, it is also possible to increase the efficiency of trapping holes in the drain region.

Also, in FIG. 2, when the gate voltage vG is 0■,
Since the semiconductor active layer 13 directly under the gate is depleted, almost no current flows between the source region 1T of the first conductivity type and the drain region 19 of the first conductivity type. In order to prove this, the drain current characteristics were measured using an actual semiconductor device, and the results are shown in FIG. 3(a). The cross-sectional structure of the semiconductor device used for the Jul determination is as shown in FIG.
．． The conductivity type of No. 19 is the same. n-type semiconductor active layer 13
The thickness is 90 nm. Since a p-type semiconductor is used as the gate electrode material, a feature of this structure is that the depletion layer already covers the entire active layer when V,=OV. However, the gate length of the semiconductor device at this time was 1.5 μm, the gate width was 20 μm, a silicon substrate was used as the semiconductor substrate 11, and a silicon oxide film was used as the lower insulating film 12.

In FIG. 3(a), it can be seen that the drain-source leakage current when the gate voltage is Ov is sufficiently small. Third
Although the figure shows a semiconductor device in which the source, drain, and active layer are all n-type semiconductors, the phenomena and effects are the same even if they are all p-type semiconductors.

Furthermore, if the semiconductor device is designed so that the depletion layer spreading from the n-domain drain region 18 reaches the lower insulating film 12,
Even if the drain voltage becomes 0.6 V or more, the potential of the depletion layer directly under the n-type drain region 18 as seen from the hole in the p-type drain region 19 is high, so that the p-type drain region 19 and the n-type drain region 19 are No forward current flows through the pn junction between the device and the shaped source region 16, and the same operation as a normal field effect semiconductor device can be realized.

Embodiment 2 FIG. 4 is a process sectional view showing an embodiment of a method for manufacturing a field effect semiconductor device according to the present invention. In Figure 4,
23 is a semiconductor layer on the main surface side of the semiconductor substrate 11 in which the insulating layer 12 is embedded, 24 is a groove for forming a gate electrode formed in a part of this semiconductor layer 23, and 25 is a semiconductor film for the gate electrode. , 26 is a female insulating film such as a silicon nitride film, 26a is a part of the insulating film 26 remaining after a predetermined processing, 2T is an insulating film with a relatively low softening temperature, such as an oxide film containing phosphorus, and 27a is an insulating film such as a silicon nitride film. is a portion of the semiconductor film 27 remaining after the predetermined processing.

In the manufacturing method of this embodiment, as shown in FIG. 4(a), an insulating layer 12 is embedded in the semiconductor, and a first layer having a conductivity type fEl is formed on the insulating layer 12. A semiconductor substrate 11 including a semiconductor layer 23 is prepared. Next, as shown in FIG. 4), a groove 24 for a gate electrode is formed in the main surface of the first semiconductor layer 23 by, for example, an anisotropic etching method. At this time, the thickness t83 of the active layer 13 left below the groove 24 is determined in consideration of the required value of the operating performance of the semiconductor device. On the other hand, in order to electrically insulate and separate the semiconductor devices, the semiconductor layer 23 is divided planarly into predetermined dimensions.

Although FIG. 4 shows the case where semiconductor devices are electrically isolated by etching the semiconductor layer 23, it is also possible to electrically isolate semiconductor devices by oxidizing the semiconductor layer and converting it into an insulator. You can. Further, either the step of electrically isolating the semiconductor devices or the step of forming a trench for the gate electrode may be performed first.

Next, as shown in FIG. 4C, a gate insulating film 14 is formed on the active layer 13 by, for example, oxidation, and then a semiconductor layer 25 for a gate electrode, for example, is formed on the gate insulating film 14.
An insulating film 26 such as a silicon nitride film is deposited on this semiconductor layer 25, and an insulating film with a low softening temperature such as a silicon oxide film containing phosphorus is further deposited on this insulating film 26. deposit n, and cover the hindlimb semiconductor substrate with an insulating film 27.
Heat treatment is performed at a temperature at which the gate electrode becomes soft, thereby flattening the recess at the top of the groove 24 for the gate electrode.

After this, as shown in FIG. 4(d), the insulating film 27 is etched using an anisotropic etching method until the insulating film 26 is exposed, and the insulating film 26a is etched only in the groove portion above the gate electrode.
and leave 27a.

Next, as shown in FIG. 4(e), the insulating film 27m is selectively removed, the insulating film 26a is used as a mask, and the semiconductor film 25 is etched by an anisotropic etching method to form the gate electrode 15. Form. After that, the insulating film 27a is removed. However, this insulating film 27m does not necessarily have to be removed.

Next, as shown in FIG. 4(f), an n+ type source region 16 and an n+ type drain region 18 having a conductivity type different from that of the active layer 13 are formed by, for example, ion implantation. Further, for example, a p-type source region 11 and a p-type drain region 19 having the same conductivity type as that of the active layer are formed outside the source region 16 and drain region 18 by, for example, ion implantation. At this time, these source regions 16 and drain regions 1
8 is arranged so that its bottom surface is in contact with the lower insulating film 12.

− side, p 10 type source region 17 and p 10 type drain region 19
may or may not have their bottom surfaces in contact with the insulating film 12.

Next, as shown in FIG. 40), an insulating film 20 is deposited on the main surface side of the semiconductor substrate, and then each source region 16.
Contact holes 28 and 29 are formed on the drain regions 18 and 17, and a source electrode 21 and a drain electrode 22 are formed.

At this time, the n-type source region 16 and the p+-type source region 1
7 are interconnected and intersected n-domain drain regions 18 and p
It is necessary that the dec-shaped drain regions 19 be interconnected.

The field effect semiconductor device manufactured in this way has a cessgate structure basically similar to that shown in FIG. 1, and the same effects as in Example 1 can be obtained.

Embodiment 3 FIG. 5 shows a cross-sectional view of an n-channel field effect semiconductor device according to another embodiment of the present invention. The n-channel type semiconductor device of this embodiment is different from that shown in FIG. A semiconductor metal compound layer 32 such as titanium silicide is disposed on the n-type drain region 18 and the p-type drain region 19, and a semiconductor metal compound layer 33 is further disposed on the gate electrode 15 to form each n-type source. area 16
and the p+ type drain region 17 are connected to each other by the source electrode 21 via the semiconductor metal compound layer 31, and the n+ type drain region 18 and the p type drain region 19 are connected to each other by the drain electrode 21 via the semiconductor metal compound layer 32. 22 to connect them to each other. Note that the same reference numerals in the figures indicate the same or corresponding parts.

According to the structure of this embodiment, semiconductor metal compound layers 31. are formed on the source and drain regions and on the gate electrode, respectively.
By providing 32.33, the parasitic resistance of the solar source, drain, and gate can be relatively reduced.
In addition to the effects of the first embodiment, this embodiment has the advantage of accelerating the speed of operation of the semiconductor device. In FIG. 5, the semiconductor metal compound layer is provided on both the source region 16.17 and the drain region 18.19, but the semiconductor metal compound layer may be provided on the negative side of each source region 16.17 and the semiconductor metal compound layer on the gate electrode 15. The metal compound layer may be omitted.

Embodiment 4 FIG. 6 is a process sectional view showing another embodiment of the method for manufacturing a field effect semiconductor device according to the present invention.

The difference between this embodiment and FIG. 4 is that the n-domain source region 16. A step of forming semiconductor metal compound layers 31 and 32 on the p+ 10-shaped source region 17, n 10-shaped drain region 1B, and p+ 19-shaped drain region 19, respectively, and forming a semiconductor metal compound layer 33 on the gate electrode 15 is performed. This is what we have in place.

In other words, in the manufacturing method of this embodiment, the housing shown in FIG. 6(a)
As shown in FIG. 1, a semiconductor substrate 11 is formed, in which, for example, silicon oxide is embedded as an insulator layer 12 in a silicon semiconductor, and a first semiconductor layer 23 having a first conductivity type is formed on the insulator. prepare. Next, as shown in FIG. 6(b), a groove 24 for a gate electrode is formed in the main surface of the first semiconductor layer 23 by an anisotropic etching method, for example, a reactive ion etching method. At this time, the thickness t83 of the active layer 13 left below the groove 24 is determined in consideration of the required operating performance of the semiconductor device. On the other hand, in order to electrically insulate and separate the semiconductor devices, the semiconductor layer 23 is etched to a predetermined size in, for example, a KOH solution using a mask such as a silicon oxide film, and divided planarly. Although FIG. 6 shows the case where semiconductor devices are electrically separated by etching the semiconductor layer, the semiconductor layer 23
Semiconductor devices may be electrically isolated by oxidizing the material and converting it into an insulator. Further, either the step of electrically isolating the semiconductor devices or the step of forming a trench for the gate electrode may be performed first.

Next, as shown in FIG. 6C, a gate insulating film 14, such as a silicon oxide film, is formed on the active layer 13 by, for example, oxidation, and then a gate electrode material such as a polycrystalline film is formed on the gate insulating film 14. A silicon film 25 is deposited, an insulating film 26 such as a silicon nitride film is deposited thereon, and an insulating film 27 such as a silicon oxide film containing phosphorus and having a low softening temperature is further deposited on the insulating film 26. , the hindlimb semiconductor substrate is heat-treated at a temperature at which the insulating film 2T is softened to flatten the depression above the groove 24 for the gate electrode.

Thereafter, as shown in FIG. 6(d), the insulating film 2 is etched by an anisotropic etching method, for example, a reactive ion etching method.
The insulating film 27 is etched to expose the insulating films 26a and 27a only in the groove portion above the gate electrode.

Next, as shown in FIG. 6(e), the insulator 1M 27a is selectively removed, and the semiconductor film 25 is etched by anisotropic etching using the insulating film 26a as a mask to form the gate electrode 15. After that, the insulating film 26a is removed. However, this insulating film 26a does not necessarily have to be removed.

Next, as shown in FIG. 6(f), an n+ type source region 16 and an n+ type drain region 18 having a conductivity type different from that of the active layer 13 are formed by, for example, ion implantation. In addition, for example, an nx type source region 17 and an nx type (nx type) ray Formed by injection method. At this time, the respective source regions 16 and drain regions 18 are arranged so that their bottom surfaces do not contact the lower insulating film 12. On the other hand, the bottom surfaces of the n+ type source region 17 and the n+ type drain region 19 may or may not be in contact with the lower insulating film 12.

Next, as shown in FIG. 6-), the source region 16°17
and a metal film 3 that exposes the upper surfaces of the drain regions 18 and 19 and the gate electrode 15 and can form a semiconductor metal compound.
4. Depositing, for example, a titanium film.

Next, as shown in FIG. 6(b), the metal film 34 and the semiconductor are reacted by a predetermined heat treatment to form, for example, titanium silicide, and then the unreacted metal film is removed.

Next, as shown in FIG. 60), an insulating film 23, for example, a silicon oxide film, is deposited on the main surface side of the semiconductor substrate, and then,
Contact holes 28.29 are formed on each source region 16.17 and drain region 18.19, and a source electrode 21, e.g. aluminum, a drain electrode 22,
For example, aluminum is formed. At this time, the n+ type source region 16 and the n+ type source region 17 are connected to each other, and the n+ type drain region 18 and the n+ type drain region 1 are connected to each other.
9 must be interconnected.

The field effect semiconductor device manufactured in this manner basically has the same hv access gate structure as shown in FIG. 5, and the same effects as in the third embodiment can be obtained. On the left, in FIG. 6, each source region 16, 17 and drain region 1
Although the semiconductor metal compound layer is provided on both sides of 8.19, the semiconductor metal compound layer provided on one of them or on the gate electrode 15 may be omitted.

Embodiment 5 FIG. 7 shows a cross-sectional view of an n-channel field effect semiconductor device according to another embodiment of the present invention. 41 is a single crystal semiconductor substrate; 42 is a first conductivity type, for example, p-type active layer 4;
4 is a gate insulating film, 45 is a gate electrode, 46 is a source region of a second conductivity type, for example, an n+ type;
Reference numeral 8 denotes a drain region of a second conductivity type, for example, an nx type, 50 an insulating film for electrically insulating between wirings, and 51 a nx type source region 46 and a part 43s of the active layer 43 adjacent thereto.
A source electrode 52 is in contact with the n-type drain region 48 and a portion 43D of the active layer 43 adjacent thereto. However, referring to FIG. 7, the thickness t8□ of the active layer 43 is designed to be thinner than the thickness of the depletion layer that can spread from directly under the gate insulating film.

That is, the n-channel type semiconductor device of this example is the first
The difference from the one shown in the figure is that the thickness of the depletion layer that can spread directly under the gate insulating film 44 is much thinner than that of the p-type active layer 43.
An n-type source region 46 whose top surface is higher than the bottom surface of the gate electrode 45 is disposed on one side of the anti-active layer 43 partitioned by the gate electrode 45, and an The position level is the gate electrode 45
An n+ 10-shaped rain region 4B having a very high bottom surface level is arranged. And these n-domain source regions 4
6 and the region 438 of the active layer 43 near the cough source region 46
are connected to each other by a source electrode 51, and further, the n-type drain region 48 and a region 43D of the active layer 43 near the drain region 48 are connected to each other by a drain electrode 52.

Next, the operation of the embodiment of the semiconductor device of the present invention shown in FIG. 7 will be explained using FIG. 8. In the device of this embodiment, the semiconductor substrate 41 and the source electrode 51 are grounded, and an appropriate positive voltage is applied to the gate electrode 45 and the drain electrode 52. However, in this semiconductor device, the gate voltage is O
The impurity concentration etc. of the semiconductor active layer are designed in advance so that the semiconductor active layer 43 directly under the gate is depleted by 1 from directly under the gate to the lower insulating layer 42 of the insulating film 1b when the voltage is V. In the button diagram, the shaded area in the active layer 43 represents a depletion region. However, the drain voltage ■.

As the voltage increases, electron-hole pairs (2) begin to occur near the drain junction due to a weak avalanche phenomenon, similar to conventional semiconductor devices. Of these, electron 0 is in the n+ type drain region 4
The meeting will take place on 8th.

On the other hand, in the semiconductor device of this embodiment in which the n+-type drain region 46 and the p-type active layer 43 are arranged in parallel at the same potential, the n+
The presence of the p-type active layer 43 suppresses an increase in the electric field intensity near the dec-shaped rain region 4B.

That is, since the nx type drain region 48 and the region 43D of the p type active layer 43 are at the same potential, the thickness of the depletion layer that spreads from the nx type drain region 48 toward the p type active layer 43 is significantly increased. suppressed. Therefore, the electric field strength within the depletion layer of the drain junction is significantly reduced.

Furthermore, although the direction of motion of the holes generated by the avalanche phenomenon is stochastically isodirectional, the energy is rapidly high at 3 to SeV. For this reason, the generated hole ■ has a slightly higher potential but is close to the p
The probability of being captured by the shaped active layer 43 increases. the result,
The amount of holes that move to the source side via the vicinity of the interface between the active layer 43 and the lower insulating film 42 is significantly reduced. However, even if some holes move to the source side, these holes are captured by the source electrode 51 via the p-type active layer 43 and are therefore injected into the n+ dec-type source region 46. The amount of holes is extremely small and disappears. Therefore, deterioration in drain-source breakdown voltage due to the parasitic bipolar effect can be effectively eliminated.

Furthermore, most of the drain-source leakage, which has conventionally been a problem in this type of semiconductor device, is the hole current flowing from the vicinity of the drain toward the source. In the device of this embodiment, most of these holes are in the p-type active layer 4.
3 and flows to the drain electrode 5° 2, so that it cancels out the current of the electrons that were separated after generation and flowed to the n-domain drain region 4B. As a result, the hole current flowing to the source is reduced, which is also effective in reducing drain-source leakage current.

Among them, in FIG. 8, the impurity concentration of the active layer 431 under the nx-type drain region 48 is increased so that the depletion layer spreading in this region does not reach the lower insulating layer 42, and a non-depleted By configuring the n-domain region to exist in the lower part 431 of the n+-type drain region 48, it is also possible to increase the efficiency of trapping holes in the drain region.

In addition, when the gate voltage is 0 in FIG. 8, the semiconductor active layer 43 directly under the gate is depleted, so both the source electrode 51 and the drain electrode 52 are in contact with the semiconductor layer 43 of the first conductivity type. However, almost no current flows between them. To confirm this, we measured the drain current characteristics using an actual semiconductor device, and found that the third
Similarly to the figure, it was confirmed that the drain-source leakage current when the gate voltage was 0 was sufficiently small.

Embodiment 6 FIG. 9 is a process sectional view showing another embodiment of the method for manufacturing a field effect semiconductor device according to the present invention.

In FIG. 9, 5.3 is a semiconductor layer on the main surface side of the semiconductor substrate 41 in which an insulating layer 42 is embedded, 54 is a groove for forming a gate electrode formed in a part of this semiconductor layer 53, and 55 56 is a semiconductor film for a gate electrode, 56 is an insulating film such as a silicon nitride film, 56a is a part of the insulating film 56 that remains after the predetermined processing, and 57 is a material with a softening temperature, such as an oxide film containing phosphorus. The relatively low insulating film 57a is a part of the semiconductor film 51 remaining after the predetermined processing.

In the manufacturing method of this embodiment, first, as shown in FIG. 9(a), an insulator layer 42 is embedded in a semiconductor, and a first semiconductor having a first conductivity type is formed on the insulator layer. A semiconductor substrate 41 including a layer 53 is prepared.

Next, as shown in FIG. 9), the first semiconductor layer 53
A groove 54 for a gate electrode is formed on the main surface of the substrate by, for example, an anisotropic etching method. At this time, the thickness ts3 of the active layer 43 left below the groove 54 is determined in consideration of the required operating performance of the semiconductor device. On the other hand, in order to electrically insulate and separate the semiconductor devices, the semiconductor layer 53 is divided planarly into predetermined dimensions. Although FIG. 9 shows the case where semiconductor devices are electrically isolated by etching the semiconductor layer, the semiconductor devices are electrically isolated by oxidizing the semiconductor layer 53- and converting it into an insulator. You may.

Further, either the step of electrically isolating the semiconductor devices or the step of forming a trench for the gate electrode may be performed first.

Next, as shown in FIG. 9C, a gate insulating film 44 is formed on the active layer 43 by, for example, oxidation, and then a semiconductor layer 55 for a gate electrode, for example, is formed on the gate insulating film 44.
An insulating film 56 such as a silicon nitride film is deposited thereon, and an insulating film 57 having a low softening temperature such as a silicon oxide film containing phosphorus is further deposited on the insulating film 56. , the hindlimb semiconductor substrate is heat-treated at a temperature at which the insulating film 57 is softened, and the depression above the gate electrode groove 54 is flattened.

After this, as shown in FIG. 9(d), the insulating film 57 is etched in the trench where the insulating film 56 is exposed using an anisotropic etching method, and the insulating film 56a is etched only in the trench above the gate electrode.
and leave 57a.

Next, as shown in FIG. 9(e), the insulating film 5Ta is selectively removed, and the semiconductor film 55 is etched by an anisotropic etching method using the insulating film 56a as a mask to form a gate electrode 45. . After that, the insulating film 57a is removed. However, this insulating film 57a does not necessarily have to be removed.

Next, as shown in FIG. 9(f), an n+ type source region 46 and an n+ type drain region 48 having a conductivity type different from that of the active layer 43 are formed by, for example, ion implantation. At this time, the bottom surfaces of each source region 46 and drain region 48 are arranged so as not to contact the lower insulating film 42.

Next, as shown in FIG. 90), an insulating film 50 is deposited on the main surface side of the semiconductor substrate, and then each source region 4B,)"
Contact holes 58 and 59 are formed in the active layer 43 near the drain region 48 and the source region 46 and drain region 48, respectively, and a source electrode 51 and a drain electrode 52 are formed.

At this time, the n-type source region 46 and the active layer 4.3 are connected to each other by the source electrode 51, the n-type source region 48 and the active layer 43 are connected to each other by the source electrode 51, and It is necessary that the n-type source region 4B and the active layer 43 be connected to each other through the drain electrode 52.

The field-effect semiconductor device manufactured in this manner has a cessgate structure basically similar to that shown in FIG. 7, and the same effects as in Example 5 can be obtained.

Embodiment 7 FIG. 10 shows a cross-sectional view of an n-channel field effect semiconductor device according to another embodiment of the present invention. The n-channel type semiconductor device of this embodiment is different from the embodiment shown in FIG. In addition to disposing the compound layer 61, a semiconductor metal compound layer 62 such as titanium silicide is disposed on the n-dos type drain region 48 and the region 43D of the active layer 43 in the vicinity thereof, and further a semiconductor metal compound layer 63 is disposed on the gate electrode 45. , each of the n-type source regions 46 and the region 43s of the active layer 43 are connected to each other by the source electrode 51 via the semiconductor metal compound layer 61, and the n-type drain region 4
8 and the region 43D of the active layer 43 as the semiconductor metal compound layer 6
2 and are connected to each other at the drain electrode 52. In the drawings, the same reference numerals indicate the same or corresponding parts.

According to the structure of this embodiment, the parasitic resistance of the source, drain, and gate can be relatively reduced by using semiconductor metal compound layers 61° and 62.63 for the source, drain, and gate, respectively. In addition to the effect No. 5, there is an advantage that speeding up the operation of the semiconductor device can be promoted. In addition, in FIG. 10, each source region 46° region 43B of the active layer 43 and the drain region 4
8. Although the semiconductor metal compound layer is provided on both regions 43D of the active layer 43, it may be provided on one of them, or the semiconductor metal compound layer on the gate electrode 45 may be omitted.

Embodiment 8 FIG. 11 is a process sectional view showing another embodiment of the method for manufacturing a field effect semiconductor device according to the present invention.

The difference between this embodiment and FIG. 9 is that n + 10 -
Semiconductor metal compound layers 61 and 62 are respectively formed on the drain region 46 and the region 43s of the active layer 43 in the vicinity thereof, and on the n-dos type drain region 48 and the region 43D of the active layer 43 in the vicinity thereof, and on the gate electrode 45. The present invention includes a step of forming a semiconductor metal compound layer 63.

That is, in the manufacturing method of this example, the manufacturing method shown in FIG. 11 (a
), a semiconductor, for example, a silicon oxide film is embedded as an insulating layer 42 in a semiconductor, for example silicon, and a first semiconductor layer 53 having a first conductivity type is formed on the insulating layer 42. A substrate 41 is prepared. Next, the 11th
As shown in FIG. 6), a groove 54 for a gate electrode is formed in the main surface of the first semiconductor layer 53 by an anisotropic etching method, for example, a reactive ion etching method. At this time, groove 5
The thickness ts3 of the active layer 43 left under the semiconductor device 4 is determined in consideration of the required operating performance of the semiconductor device. On the other hand, in order to electrically isolate the semiconductor devices, the semiconductor layer 53 is etched to a predetermined size using, for example, a KOH solution using a mask such as a silicon oxide film, and divided planarly. Although FIG. 11 shows the case where semiconductor devices are electrically isolated by etching the semiconductor layer, it is also possible to electrically isolate semiconductor devices by oxidizing the semiconductor layer 53 and converting it into an insulator. You can. -! Either the step of electrically isolating the semiconductor devices or the step of forming a groove for a gate electrode may be performed first.

Next, as shown in FIG. 11(C), a gate insulating film 44, for example a silicon oxide film, is formed on the active layer 43, and then a gate electrode 55, for example a polycrystalline silicon layer, is formed on the gate insulating film 44. An insulating film 56, such as a silicon nitride film, is deposited on this insulating film 56, and an insulating film 57, such as a silicon oxide film containing phosphorus and having a low softening temperature, is deposited on the insulating film 56. is heat-treated at a temperature at which the insulating film 5T is softened to flatten the recess at the top of the gate electrode groove 54.

Thereafter, as shown in FIG. 11(d), the insulating film 57 is etched in the casing where the insulating film 56 is exposed using an anisotropic etching method, for example, a reactive ion etching method, and only the groove portion above the gate electrode is etched. Insulating films 56a and 57a are left.

Next, as shown in FIG. 11(e), the insulating film 57m is selectively removed, and the semiconductor film 55 is etched using an anisotropic etching method, such as a reactive ion etching method, using the insulating film 56a as a mask. , a gate electrode 45 is formed. After that, the insulating film 57a is removed. However, this insulating film 57a does not necessarily have to be removed.

Next, as shown in FIG. 11(f), an n+ type source region 46 and an n+ type drain region 48 having a conductivity type different from that of the active layer 43 are formed by, for example, ion implantation.

At this time, the source region 46 and the drain region 48 are arranged so that their bottom surfaces do not come into contact with the insulating film 42.

Next, as shown in FIG. 11, the upper surfaces of the source region 46, drain region 48, and gate electrode 45 are exposed, and a metal film 64 capable of forming a semiconductor metal compound, for example, a titanium film, is deposited.

Next, as shown in FIG. 11(b), the metal film 64 and the semiconductor are reacted by a predetermined heat treatment to form, for example, titanium silicide, and then the unreacted metal film is removed.

Next, as shown in FIG. 11(i), an insulating film 53, for example a silicon oxide film, is deposited on the main surface side of the semiconductor substrate, and then the source region 46. Contact holes 58 and 59 are formed in the drain region 48 and the active layer 43 in the vicinity of the source region 46 and the drain region 48, respectively, and the source electrode 51, for example aluminum, and the drain electrode 52 are formed in contact holes 58, 59, respectively.
, for example, aluminum. At this time, it is necessary that the source region 46 and the active layer 43 in the vicinity thereof be connected to each other by the source electrode 51, and the Toyota drain region 48 and the active layer 43 in the vicinity thereof to be connected to each other by the drain electrode 52. It is.

The field effect semiconductor device manufactured in this way has a cessgate structure basically similar to that shown in FIG. 10, and the same effects as in Example 7 can be obtained. Naka, 1st
In Figure 1, each source region 46. Active layer 43 and drain region 48. The semiconductor metal compound layer may be provided on both sides of the active layer 43, or may be provided on one of them, or the semiconductor metal compound layer on the gate electrode 45 may be omitted.

〔Effect of the invention〕

As explained above, the first aspect of the present invention. According to the second invention, the following effects can be obtained.

(1) Since a highly impurity concentration layer of the same conductivity type as the active layer is provided adjacent to the drain junction and a drain voltage is applied to it, the majority carriers of the electron-hole pairs generated near the drain junction are Almost all of it can be absorbed, and the flow of majority carriers toward the source side can be effectively suppressed.

(11) Since a high impurity concentration layer of the same conductivity type as the active layer is provided adjacent to the source junction and a source voltage is applied to it, some of the electron-hole pairs generated near the drain junction are transferred to the source side. It captures all the small amount of majority carriers that flow and prevents insects from directly injecting them into the source junction.

(iii) Due to the effect described in (+), the amount of majority carriers injected into the source junction, which triggers the occurrence of the parasitic bipolar effect, can be dramatically suppressed, and the breakdown voltage between the drain and source can be significantly improved. .

(iv) The effect described in (+) can dramatically reduce the leakage current flowing between the drain and source when the semiconductor device is in the non-operating state.

(V) Since the recessed gate structure is used as the gate structure, the short channel effect can be alleviated.

Moreover, the third aspect of the present invention. According to the fourth invention, since a semiconductor metal compound is used in combination on the source and drain regions, the parasitic resistance of the source and drain can be relatively reduced.
Above 1. In addition to the effects (1) to (V) of the second invention, it is possible to obtain the effect of promoting faster operation of the semiconductor device.

Furthermore, the fifth aspect of the present invention. According to the sixth invention, the following effects can be obtained.

(1) Since the surface of the part of the active layer adjacent to the drain junction is set to the same potential as the drain region, almost all of the majority carriers among the electron-hole pairs generated near the drain junction can be absorbed and transferred to the source side. The flow of majority carriers can be effectively suppressed.

(11) Since the surface of a part of the active layer adjacent to the source junction is set to the same potential as the source region, a small amount of majority carriers that flow toward the source among the electron-hole pairs generated near the drain junction are All of this can be captured and prevented from being directly injected into the source junction.

Due to the effect described in (m+l), the amount of majority carriers injected into the source junction, which triggers the occurrence of the parasitic bipolar effect, can be dramatically suppressed, and the breakdown voltage between the drain and source can be significantly improved.

(lv) Due to the effect described in (i), the leakage current flowing between the drain and source of the semiconductor device in the non-operating state can be dramatically reduced.

(V) Since the recessed gate structure is used as the gate structure, the short channel effect can be alleviated.

Furthermore, the seventh aspect of the present invention. According to the eighth invention, since the semiconductor metal compound layer is provided on the source and drain regions, the parasitic resistance of the source and drain can be relatively reduced. In addition to the effects (1) to (V) of the sixth aspect of the invention, it is possible to obtain the effect of promoting faster operation of the semiconductor device.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the structure of a field-effect semiconductor device according to an embodiment of the present invention, FIG. 2 is a conceptual diagram showing the operation of the embodiment of FIG. 1, and FIGS. A characteristic diagram showing the drain current characteristics of a semiconductor device having a source/drain region of the same conductivity type as the semiconductor active layer in the embodiment shown in FIG. 1 and a structural diagram thereof, and FIG. 5 is a structural sectional view showing another embodiment of the present invention, FIG. 6 is a process sectional view showing another embodiment of the manufacturing method of the present invention, and FIG. 7 is a structural sectional view showing another embodiment of the present invention. 8 is a conceptual diagram showing the operation of the embodiment of FIG. 7,
FIG. 9 is a process cross-sectional view showing another embodiment of the manufacturing method of the present invention, FIG. 10 is a structural cross-sectional view showing yet another embodiment of the present invention, and FIG. 11 is a process cross-sectional view showing another embodiment of the manufacturing method of the present invention. FIGS. 12(a) and 12(b) are cross-sectional views of a semiconductor device showing an example of the conventional technology and operational characteristics diagrams obtained in the semiconductor device, and FIG. 13 is a cross-sectional view of FIG. 'l
FIG. 3 is a conceptual diagram for explaining the parasitic bipolar effect that appears in the semiconductor device shown in FIG. 11.41 ... single crystal semiconductor substrate, 12°42
...Insulating film (insulator layer), 13.43...1st
Conductive type active layer, 14.44...gate insulating film, 1
5.45...Gate electrode, 16.46...Second
Source region of conductivity type, 17...source region of first conductivity type, 18.48...drain region of second conductivity type,
19... Drain region of first conductivity type, 20.50.
... Insulating film, 21.51 ... Source electrode, 22゜52 ... Drain region, 438 ... Partial region of active layer 33 adjacent to source region, 43D ... Drain A partial region of the active layer 33 adjacent to the region.

Claims (1)

[Scope of Claims] (1) A field effect semiconductor device with an insulated gate structure in which a gate electrode is formed on a semiconductor active layer of a first conductivity type formed on an upper part of an insulating material layer via a gate insulating film. In,
A semiconductor active layer of a first conductivity type that is thinner than at least the thickness of a depletion layer that can spread directly under the gate insulating film; a source region of a first conductivity type disposed on one side of the semiconductor active layer partitioned by a gate electrode; A source region of a second conductivity type whose surface level is higher than the position level of the bottom surface of the gate electrode, a drain region of the first conductivity type placed on the other side, and a position level of the upper surface thereof is higher than the position level of the bottom surface of the gate electrode. Second
a drain region of a conductivity type; a source electrode in which the source region of the second conductivity type and the source region of the first conductivity type are interconnected; and the drain region of the second conductivity type and the drain region of the first conductivity type; 1. A field-effect semiconductor device comprising a drain electrode and a drain electrode connected to each other. (2) A first insulating layer is embedded in the semiconductor and the first insulating layer is embedded in the semiconductor.
forming a groove on the semiconductor layer on the main surface of the semiconductor substrate including a first semiconductor layer having a first conductivity type on the insulator layer, and forming a second insulating film in the groove as a gate insulating film. forming a gate electrode on the second insulating film; and forming a second conductivity type source region and a second conductivity type source region on both the gate electrode and the first semiconductor layer separated in plan by the gate electrode.
The step of forming conductive type drain regions so that their bottom surfaces do not contact the first insulating layer, and the first semiconductor layer divided two-dimensionally by the gate electrode, each having an impurity concentration of forming a source region of a first conductivity type and a drain region of a first conductivity type that has an impurity concentration higher than that of a semiconductor active layer of a first conductivity type; forming contact holes on the region and on the drain region of the first conductivity type and the drain region of the second conductivity type, respectively, and the source region of the first conductivity type and the source region of the second conductivity type. forming an electrode on the drain region of the first conductivity type and on the drain region of the second conductivity type to connect them. A method for manufacturing a field effect semiconductor device. (3) In claim 1, the first semiconductor metal compound layer is arranged at least in one or both of the source region of the first conductivity type or the source region of the second conductivity type, and the drain region of the first conductivity type or the source region of the second conductivity type. comprising a second semiconductor metal compound layer disposed on one or both of the drain regions of the second conductivity type;
The source region of the second conductivity type and the source region of the first conductivity type are connected to each other by a source electrode via the first semiconductor metal compound layer, and the drain region of the second conductivity type and the source region of the first conductivity type are connected to each other by a source electrode via the first semiconductor metal compound layer. A field-effect semiconductor device, characterized in that the drain region of the field-effect semiconductor device is connected to the drain region of the field-effect semiconductor device by a drain electrode via the second semiconductor metal compound layer. (4) In claim 2, a semiconductor metal compound layer is formed in at least one or both of the source region of the first conductivity type or the source region of the second conductivity type, and the semiconductor metal compound layer is formed in the drain region of the first conductivity type or the second conductivity type. forming a semiconductor metal compound layer on one or both of the conductivity type drain regions, and forming the second conductivity type source region and the first conductivity type source region with the first semiconductor metal compound layer an electric field characterized in that the drain region of the second conductivity type and the drain region of the first conductivity type are mutually connected by the electrode through the second semiconductor metal compound layer; A method for manufacturing an effective semiconductor device. (2) In a field-effect semiconductor device having an insulated gate structure in which a gate electrode is formed on a semiconductor active layer of a first conductivity type formed on an upper part of an insulating material layer via a gate insulating film,
A semiconductor active layer of a first conductivity type that is thinner than at least the thickness of a depletion layer that can spread directly under the gate insulating film, and one of the semiconductor active layers partitioned by a gate electrode have an upper surface level that is at the bottom surface of the gate electrode. 2nd higher than the position level
a source region of a conductivity type, and a drain region of a second conductivity type whose upper surface level is higher than a bottom level of the gate electrode; a source electrode that interconnects a semiconductor active layer of a first conductivity type in the vicinity; a drain electrode that interconnects a drain region of the first conductivity type and a semiconductor active layer of a first conductivity type in the vicinity of the drain region; A field effect semiconductor device comprising: (6) A first insulating layer is embedded in the semiconductor and the first insulating layer is embedded in the semiconductor.
forming a groove on the semiconductor layer on the main surface of the semiconductor substrate including a first semiconductor layer having a first conductivity type on the insulator layer, and forming a second insulating film in the groove as a gate insulating film. a step of forming a gate electrode on the second insulating film; and a step of forming a gate electrode on the second insulating film, and a step of forming a source region of a second conductivity type and a second conductivity type in both of the first semiconductor layer separated in plan by the gate electrode. forming drain regions of second conductivity type so that their bottom surfaces do not contact the first insulating layer; and forming semiconductor active regions of first conductivity type on and in the vicinity of the second conductivity type source region. forming contact holes on each layer, and forming contact holes on the drain region of the second conductivity type and on the semiconductor active layer of the first conductivity type in the vicinity of the drain region; forming an electrode that interconnects the contact hole on the source region of the second conductivity type and the contact hole on the semiconductor active layer of the first conductivity type near the source region; forming an electrode that interconnects the contact hole on the drain region of the shape and the contact hole on the semiconductor active layer of the first conductivity type near the drain region. A method for manufacturing a field effect semiconductor device. (7) In claim 5, the first semiconductor metal compound layer disposed on at least one or both of the source region of the second conductivity type or the semiconductor active layer of the first conductivity type in the vicinity of the source region; a second semiconductor metal compound layer disposed on one or both of the drain region of the shape or the semiconductor active layer of the first conductivity type in the vicinity of the drain region;
A source region of a conductivity type and a semiconductor active layer of a first conductivity type in the vicinity of the source region are interconnected by a source electrode via the first semiconductor metal compound layer, and a drain region of a second conductivity type is connected to the semiconductor active layer of a first conductivity type in the vicinity of the source region. A field effect semiconductor device, characterized in that a semiconductor active layer of a first conductivity type in the vicinity of the drain region is interconnected by a drain electrode via the second semiconductor metal compound layer. (8) In claim 6, a semiconductor metal compound layer is formed on at least one or both of the source region of the second conductivity type or the semiconductor active layer of the first conductivity type in the vicinity of the source region; forming a semiconductor metal compound layer on one or both of the drain region or the semiconductor active layer of the first conductivity type in the vicinity of the drain region; A semiconductor active layer of a first conductivity type is connected to each other by an electrode via the semiconductor metal compound layer, and a drain region of a second conductivity type and a semiconductor active layer of a first conductivity type in the vicinity of the drain region are connected to each other through the semiconductor metal compound layer. A method for manufacturing a field-effect semiconductor device, characterized in that the devices are connected to each other by electrodes via the semiconductor metal compound layer.