JPH0362705A - Clock signal generating circuit - Google Patents

Abstract

PURPOSE:To generate a clock pulse having a comparatively high frequency as 30-50MHz stably even when an additional capacitance is increased by providing a circuit comprising an inductor and a capacitor to a feedback part of an inverter acting like an oscillator. CONSTITUTION:A Colpitz oscillation circuit 10 in the clock signal generating circuit is constituted by connecting a crystal resonator 1 and a feedback resistor 3 in parallel between the input and the output of an inverter acting like an oscillator, connecting an input capacitor 4 and an output capacitor 5 between the crystal vibrator 1 and ground G and connecting a buffer inverter 6 to the output of the inverter 2. The overtone signal of 5th harmonic or over outputted from the inverter 2 is cut off by a filter circuit 20 comprising an inductor 7 connecting in series with the feedback resistor 3 and a capacitor 8 connected in parallel with the inductor 7 and to ground, and the signal from the inverter 2 is cut off by a feedback part through the feedback resistor 3 and the inductor 7 and only the 3rd order overtone signal is outputted from the inverter 2.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a circuit that generates a relatively high frequency clock pulse signal of 30 to 50 MHz. The present invention relates to a signal generating circuit that expressly oscillates overtones.

[Background of the invention]

In recent years, in order to increase the processing power of personal computers at the speed of sound, the processing bits of the central processing unit (CPU) have been improved and the operating speed has been increased.

To increase the operating speed, increase the processing speed of the CPU,
There is a need for a clock signal generation circuit that can stably and quickly generate a clock signal corresponding to the processing speed.

[Conventional technology]

As a conventional clock signal generation circuit that generates a clock signal at a high frequency, an LC tuning circuit as shown in FIG.
98904), or to remove this LC circuit and use a crystal in which the fundamental wave mode of the crystal resonator is suppressed.

Generally, a clock signal generation circuit has been comprised of a Colpitts oscillation circuit using a crystal resonator 21 and a tuning circuit consisting of an inductance 27 and a capacitor 28.

The Colpitts oscillation circuit uses an oscillation inverter (inverter I
A crystal oscillator 2] and a feedback resistor 23 are connected in parallel between the input and output of the
An input capacitor 24 and an output capacitor 25 are connected between 1 and ground G, and a puff fine inverter 26 is further connected to the output portion of the inverter IC 22.

In addition, the tuning circuit includes an inductance 27 and a capacitor 28.
are connected in series, and one end of the capacitor 28 is connected to the ground G.
has been done. This tuning circuit is connected to the output side of the crystal resonator 21.

In the clock pulse signal generation circuit configured as above, 3
In order to generate a clock pulse signal with a high frequency of 0 to 50 MHz, the third-order overtone of the crystal resonator 2 was used. Specifically, the inductance 27 and capacitor 28, which are a tuning circuit, are used to tune and focus on a predetermined third-order overtone frequency, and the fundamental wave mode signal is further suppressed by an L-C tuning circuit. be. Further, signals due to overtones of the fifth order or higher are not output by selecting constants such as the feedback resistor 23, the input end capacitor 24, and the output end capacitor 25.

[Problems to be solved by the invention]

However, recently, it is necessary to directly input a clock pulse signal with a high frequency of 30 to 50 MHz to a plurality of CPUs and other peripheral ICs where only one CPU requires a clock pulse signal. That is, the load capacity for the clock pulse signal generation circuit becomes large. If a conventional clock signal generation circuit is used with a high load capacity, the frequency-gain characteristics and drive capability of the inverter IC22 will cause the clock pulse signal to lose its steep rise and fall, causing problems with multiple CPUs and other peripheral ICs. It becomes difficult to operate normally.

In order to maintain the steep rise and fall of the clock pulse signal even when used with a high load capacity, the inverter TC22 must have high frequency-gain characteristics, that is, high gain even in the high frequency region, and high current drive capability. It is conceivable to use an inverter IC 22 having the following characteristics. In this case, even if the tuned circuit of the inductance 27 and the capacitor 28 can be focused in a region where the power supply voltage is low to some extent, if the frequency-gain characteristics are sufficiently higher than that of the fifth-order overtone, the feedback resistance 23
, it is impossible to suppress the fifth-order overtone with only the constants of the input side capacitor 24 and the output side capacitor 25, resulting in an unstable oscillator, and such a circuit is practically impossible to put into practical use. .

The present invention has been devised in view of the above-mentioned problems,
The purpose of this is that even if the number of CPUs and other TCs connected to the clock generation signal circuit increases and the load capacity increases, the
50M) (An object of the present invention is to provide a clock signal generation circuit that can stably derive a relatively high frequency clock pulse of Z.

[Means to solve the problem]

In order to solve the above problems, the present invention connects a crystal resonator and a feedback resistor in parallel between the input and output of an oscillation inverter, and further connects an input capacitor and an output capacitor between the crystal resonator and ground. In the clock signal generation circuit according to the present invention, an inductance is connected between the output side of the oscillation inverter and a feedback resistor, and a capacitor is connected to ground between the feedback resistor and the inductance. It is a circuit.

[Effect]

According to the clock signal generation circuit configured as described above, overtones of the fifth or higher order output from the oscillation inverter are generated by the inductance connected in series with the feedback resistor and the capacitor connected in parallel with the inductance and grounded. By a kind of filter circuit composed of
The signal is cut in feedback and feedback passing through the inductance, and only the signal due to the third-order overtone is output from the oscillating inverter. Note that the fundamental mode signal of the crystal resonator is suppressed by the capacitance value of the input/output side capacitor.

〔Example〕

Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 1 is a circuit diagram showing a clock signal generation circuit of the present invention.

The clock signal generation circuit is composed of a Colpitts oscillation circuit 10 using a crystal resonator 1 and a filter circuit 20 consisting of an inductance and a capacitor.

The Colpitts oscillation circuit 10 has a crystal oscillator 1 and a feedback resistor 3 connected in parallel between the input and output of an oscillation inverter (hereinafter referred to as inverter IC) 2, and an input between the crystal oscillator and ground G. A side capacitor 4 and an output side capacitor 5 are connected, and a buffer inverter 6 is further connected to the output portion of the inverter IC2.

The filter circuit 20 also has an inductance 7 connected in series between the output side of the inverter IC 2 and the feedback resistor 3, and a capacitor 8 connected in parallel with the inductance 7, the other end of which is grounded. ing.

In the above configuration, by using ICs with excellent frequency-gain characteristics and high driving ability for the inverter IC2 and the buffer inverter 6, the rise and fall of the clock pulse signal can be kept steep.

In the above circuit, harmonic components including the fifth-order overtone are filtered through a filter circuit 20 consisting of an inductance 7 and a capacitor 8 provided in the feedback section of the inverter TC2.
Accordingly, a predetermined frequency band having a cutoff frequency fc is passed.

Now, the filter constant is the cutoff frequency fc=1/2π(
Since it is an LC, for example, when setting the frequency of the clock pulse signal to 32MHz, the inductance 7 should be set to 0.
．． It is sufficient to set the capacitor 8 to 33 μH and 33 pF.

FIG. 2(a) is a characteristic diagram showing the frequency-gain characteristics of an inverter IC used in a clock signal generation circuit.

Solid line A in the characteristic diagram is the frequency-gain characteristic of the inverter IC used in the clock signal generation circuit of the present invention, and solid line B is the frequency-gain characteristic of the inverter IC used in the clock signal generation circuit of the present invention.
is an inverter I used in a conventional clock signal generation circuit.
It is a frequency-gain characteristic of C2.

Further, FIG. 2(b) shows the frequency gain characteristic of the entire clock signal generation circuit of the present invention (in the case of 40 MHz output).

As is clear from the characteristic diagram, the clock signal generation circuit of the present invention has a frequency-gain characteristic of the crystal oscillator determined by the frequency-gain characteristic of the inverter IC2.
It is possible to stably derive a third-order overtone oscillation signal of about 50 MHz.

Note that when setting the frequency of the clock pulse signal to 40 MHz, the inductance 7 may be set to 0.33 μH and the capacitor 8 may be set to 18 pF.

〔Effect of the invention〕

As described above, according to the present invention, since the inductance and capacitor circuits are provided in the feedback section of the inverter IC, by using the inverter IC with excellent frequency characteristics, the CPU and other ICs connected to the clock pulse generation signal can 30 to 50 even if the additional capacity increases.
This provides a clock signal generation circuit that can stably derive a relatively high frequency clock pulse of MH2.

Further, since the above-mentioned inductance and capacitor can be formed by a chip-shaped capacitor or coil, the entire circuit can be miniaturized.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a clock signal generation circuit of the present invention. FIG. 2(a) is a characteristic diagram showing the frequency-gain characteristics of an inverter IC used in a clock signal generation circuit.
Figure (b) is a characteristic diagram showing the frequency-gain characteristics of the clock signal generation circuit. FIG. 3 is a circuit diagram showing a conventional clock signal generation circuit. 0 1, 21 2, 22 3, 23 4.24 5, 25 6.26 7, 27 8.28 0 20 ・ ・ −・Crystal resonator・Inverter IC・Feedback resistance・Input capacitor Output capacitor・Buffer inverter・Inductance・Capacitor Colpitts oscillation circuit ・Filter circuit

Claims (1)

[Claims] In a clock signal generation circuit in which a crystal resonator and a feedback resistor are connected in parallel between the input and output of an oscillation inverter, and an input capacitor and an output capacitor are further connected between the crystal resonator and ground, the output side of the oscillation inverter is 1. A clock signal generation circuit comprising: an inductance connected between the feedback resistor and the feedback resistor, and a capacitor connected to ground between the feedback resistor and the inductance.