JPH036024A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH036024A JPH036024A JP14057189A JP14057189A JPH036024A JP H036024 A JPH036024 A JP H036024A JP 14057189 A JP14057189 A JP 14057189A JP 14057189 A JP14057189 A JP 14057189A JP H036024 A JPH036024 A JP H036024A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- organic film
- melting point
- metal
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 53
- 239000002184 metal Substances 0.000 claims abstract description 53
- 238000002844 melting Methods 0.000 claims abstract description 40
- 230000008018 melting Effects 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 19
- 229910052721 tungsten Inorganic materials 0.000 claims description 19
- 239000010937 tungsten Substances 0.000 claims description 19
- 229920001721 polyimide Polymers 0.000 claims description 17
- 239000009719 polyimide resin Substances 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 6
- 238000001947 vapour-phase growth Methods 0.000 description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 150000002739 metals Chemical class 0.000 description 10
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 3
- BIVUUOPIAYRCAP-UHFFFAOYSA-N aminoazanium;chloride Chemical compound Cl.NN BIVUUOPIAYRCAP-UHFFFAOYSA-N 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 239000011259 mixed solution Substances 0.000 description 3
- 239000003870 refractory metal Substances 0.000 description 3
- 239000012808 vapor phase Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、半導体装置の製造方法に適用して有効な技術
に関するもので、例えば、接続孔を穴埋めする技術に利
用して有効な技術に関するものである。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a technique that is effective when applied to a method of manufacturing a semiconductor device, for example, a technique that is effective when applied to a technique for filling connection holes. It is something.
[従来の技術]
従来、半導体基板表面の拡散層にコンタクトするコンタ
クトホールや、金屑配線にコンタクトするスルーホール
等の接続孔に対する導体Mによる穴埋めは、例えばアル
ミニウム等の金属の全面堆積、パターニングを行なうこ
とによりなされていた。しかしながら、このような方法
により接続孔の穴埋めを行なうと、該接続孔に充填され
る金属のカバレジがあまり良好でないために、該接続孔
において導通不良等が発生する畏れがあった。しかも、
最近においては、高集積化の要請に伴って該接続孔が小
さくなってきており、その畏れは増々強まる傾向にある
。[Prior Art] Conventionally, the filling of contact holes such as contact holes that contact a diffusion layer on the surface of a semiconductor substrate or through holes that contact a metal scrap wiring with a conductor M has been performed by, for example, depositing and patterning a metal such as aluminum on the entire surface. It was done by doing. However, when the connection hole is filled by such a method, the coverage of the metal filled in the connection hole is not very good, so there is a risk that poor conduction or the like may occur in the connection hole. Moreover,
Recently, with the demand for higher integration, the connection holes have become smaller, and this fear is becoming more and more common.
従って、近年においては、コンタクトホールやスルーホ
ール等の接続孔の穴埋めを金属の単なる全面堆積により
行な力ずに、例えばタングステン等の高融点金属の選択
気相成長法により行なうようにし、上記問題点に対処す
るようにしていた。Therefore, in recent years, instead of simply depositing metal on the entire surface to fill connection holes such as contact holes and through holes, selective vapor deposition of high melting point metals such as tungsten has been used to solve the above problems. I was trying to deal with the points.
この高融点金属の選択気相成長法とは、ガス条件をコン
トロールして高融点金属を気相化学堆積させると(例え
ば、温度は300〜350’C)、該高融点金属はシリ
コンやアルミニウム等の特定の物質上のみに成長し、5
i02等の上には形成されないという特性があることか
ら、この特性を利用してSin、等よりなる無機絶縁膜
から接続孔を通して露出するシリコン(半導体基板)や
アルミニウム(金属配線)上にのみタングステン等の高
融点金属を成長させるというものであり、接続孔に高融
点金属を入れて成長させる方法を採っているので、上記
の従来技術に比べてカバレジが極めて良好となるという
利点がある。This selective vapor phase growth method for high melting point metals is a process in which high melting point metals are vapor phase chemically deposited by controlling gas conditions (e.g., at a temperature of 300 to 350'C). grows only on certain substances, 5
Since tungsten has the characteristic that it is not formed on surfaces such as i02, this characteristic can be used to form tungsten only on silicon (semiconductor substrate) or aluminum (metal wiring) exposed through connection holes from an inorganic insulating film made of Sin, etc. This method involves growing a high-melting point metal such as, for example, by putting the high-melting point metal into a connection hole and growing it, which has the advantage of extremely good coverage compared to the above-mentioned conventional technology.
[発明が解決しようとする課題]
しかしながら、このような高融点金属の選択気相成長法
を用いて製造された半導体装置に対して本発明者は以下
の問題点を発見した。[Problems to be Solved by the Invention] However, the inventors of the present invention have discovered the following problems with semiconductor devices manufactured using such selective vapor phase epitaxy of high melting point metals.
すなわち、高融点金属を選択的に気相成長させる際に、
該高融点金属が付着しないと考えられていた5i02等
よりなる無機絶縁膜上に、該高融点金属が稀に付着する
ことがあるということを発見した。この無機絶縁膜上へ
の高融点金属の付着をそのままにしておくことは品質的
に問題があるのでこの高融点金属を無機絶縁膜上から除
去しなければならないが、追加エッチ等の工程が必要と
され、製造プロセスが煩雑となり好ましくない。In other words, when selectively vapor phase growing a high melting point metal,
It has been discovered that the high melting point metal may occasionally adhere to an inorganic insulating film made of 5i02 or the like, which was thought not to be attached to the high melting point metal. Leaving the refractory metal attached to the inorganic insulating film poses a quality problem, so this refractory metal must be removed from the inorganic insulating film, but additional etching steps are required. This makes the manufacturing process complicated and undesirable.
本発明は係る問題点に鑑みなされたものであって、製造
プロセスの簡略化が図られた半導体装置の製造方法を提
供することを目的としている。The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device in which the manufacturing process is simplified.
この発明の前記ならびにそのほかの目的と新規な特徴に
ついては、本明細書の記述および添附図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
[課題を解決するための手段]
本願において開示される発明のうち代表的なものの概要
を説明すれば、下記のとおりである。[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.
すなわち、高融点金属を半導体基板かつ/または金属配
線上の任意の部位にのみ選択的に気相成長させるにあた
り、前記任意の部位以外の部位を、選択気相成長時の温
度に耐え得る耐熱性を有する有機膜で覆うようにしたも
のである。In other words, when selectively vapor-depositing a high-melting point metal only on an arbitrary part on a semiconductor substrate and/or metal wiring, parts other than the above-mentioned arbitrary parts must have heat resistance that can withstand the temperature during selective vapor-phase growth. It is covered with an organic film having a
[作用]
上記した手段によれば、高融点金属を半導体基板かつ/
または金か配線上の任意の部位にのみ選択的に気相成長
させるにあたり、前記任意の部位以外の部位を、選択気
相成長時の温度に耐え得る耐熱性を有する有機膜で覆う
ようにしたので、高融点金属の高温なる選択気相成長時
において、有機膜が溶融することなく選択マスクとして
の機能を充分果たすと共に、そのマ入りには有機膜の特
性から該高融点金属が付着・成長することはないという
作用によって、この任意の部位以外の部位に付着してい
た高融点金属の除去工程が不要となり、製造プロセスの
簡略化を図るという上記目的が達成されることになる。[Function] According to the above-described means, the high melting point metal is applied to the semiconductor substrate and/or
Alternatively, when performing selective vapor phase growth only on an arbitrary part of the gold wiring, parts other than the above-mentioned arbitrary parts are covered with an organic film having heat resistance that can withstand the temperature during selective vapor phase growth. Therefore, during high-temperature selective vapor phase growth of high-melting point metals, the organic film does not melt and fully functions as a selective mask. This effect eliminates the need for the step of removing high melting point metals that have adhered to areas other than this arbitrary area, thereby achieving the above-mentioned objective of simplifying the manufacturing process.
[実施例コ
以下、本発明に係る半導体装置の製造方法の実施例を図
面を参照しながら説明する。[Embodiment 1] Hereinafter, embodiments of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.
第1図には本発明に係る半導体装置の製造方法の第1の
実施例を適用して得られた半導体装置が示されている。FIG. 1 shows a semiconductor device obtained by applying a first embodiment of the method for manufacturing a semiconductor device according to the present invention.
この第1の実施例の半導体装置では、例えばアルミニウ
ムよりなる金属配線1の任意の位置にコンタクトするス
ルーホールには1選択気相成長により形成された、例え
ばタングステンよりなる高融点金、[6が充填(成長)
されており、この第1の実施例の半導体装置にあっては
、このスルーホール以外の部位には選択気相成長時の温
度に耐え得る耐熱性を有すると共に上記高融点金、@6
が付着・成長することのない、例えばポリイミド系樹脂
(P i Q ;商標)よりなる有機膜3が途中工程に
おいて被膜されている。In the semiconductor device of this first embodiment, a through hole that contacts any position of a metal wiring 1 made of, for example, aluminum is formed by selective vapor deposition using a high melting point gold made of, for example, tungsten. Filling (growth)
In the semiconductor device of the first embodiment, the parts other than the through hole have heat resistance that can withstand the temperature during selective vapor phase growth, and the above-mentioned high melting point gold @6
An organic film 3 made of, for example, polyimide resin (P i Q (trademark)), which does not adhere or grow, is coated in an intermediate process.
以下、上記実施例の半導体装置の製造方法の一例を第2
図(a)〜第2図(f)に基づいて説明する。Hereinafter, an example of the method for manufacturing the semiconductor device of the above embodiment will be explained in the second example.
This will be explained based on FIG. 2(a) to FIG. 2(f).
先ず、例えばシリコンよりなる半導体基板5上の全面に
、例えばSin、よりなる無機層間絶縁膜2,400〜
450℃迄の耐熱性を有する例えばポリイミド系樹脂よ
りなる有機膜3.02反応性イオンエツチング耐性を有
するSi含有ホトレジスト4をその順で順次塗付、成膜
し1次いで周知のホトリソ技術により感光、現像して金
属配線1上の任意の位置のスルーホールパターンをSi
含有ホトレジスト4に転写し、第2図(a)に示される
状態とする。First, on the entire surface of the semiconductor substrate 5 made of silicon, for example, an inorganic interlayer insulating film 2,400 made of, for example, Sin is formed.
An organic film 3 made of, for example, a polyimide resin having heat resistance up to 450°C, and a Si-containing photoresist 4 having resistance to reactive ion etching are sequentially applied in that order to form a film. Through development, a through hole pattern at an arbitrary position on the metal wiring 1 is formed using Si.
The photoresist 4 is then transferred to the containing photoresist 4 to form the state shown in FIG. 2(a).
次に、02反応性ドライエツチング技術により上記Si
含有ホトレジスト4上のパターンを下層の有機膜3に転
写し、第2図(b)に示される状態とする。Next, the above Si was etched using 02 reactive dry etching technology.
The pattern on the containing photoresist 4 is transferred to the underlying organic film 3, resulting in the state shown in FIG. 2(b).
次に、レジスト除去液を用いてSi含有ホトレジスト4
を剥離し、第2図(Q)に示される状態とする。Next, the Si-containing photoresist 4 is removed using a resist removal solution.
is peeled off to obtain the state shown in FIG. 2 (Q).
次に、有機膜3を加工マスクとしたCF4系ガス中にお
ける反応性イオンエツチング技術により。Next, using a reactive ion etching technique in CF4 gas using the organic film 3 as a processing mask.
無機層間絶縁膜2に上記スルーホールパターンを透孔し
、第2図(d)に示される状態とする。The above-mentioned through-hole pattern is formed in the inorganic interlayer insulating film 2 to form the state shown in FIG. 2(d).
次に、上記有機膜3を残した状態、すなわちスルーホー
ルパターン以外の部位を有機膜3で覆った状態で、例え
ばタングステンよりなる高融点金属の選択気相成長を約
300〜350℃の温度で行ない、透孔部にのみ選択的
にタングステンを成長させ、第2図(e)に示される状
態とする。ここで、ポリイミド系樹脂3の耐熱温度は上
述の如く400〜450℃となっているので、該ポリイ
ミド系樹脂3が選択気相成長時に溶融することはなく、
しかも該ポリイミド系樹脂3にはその特性上タングステ
ン6が付着・成長することはないので、タングステン6
のアルミニウム1とポリイミド系樹脂3とに対する選択
性が良好に確保され得るようになっている。Next, with the organic film 3 remaining, that is, parts other than the through hole pattern covered with the organic film 3, selective vapor phase growth of a high melting point metal such as tungsten is performed at a temperature of about 300 to 350°C. Then, tungsten is selectively grown only in the through holes, resulting in the state shown in FIG. 2(e). Here, since the heat resistant temperature of the polyimide resin 3 is 400 to 450°C as described above, the polyimide resin 3 does not melt during selective vapor growth,
Moreover, since tungsten 6 does not adhere or grow on the polyimide resin 3 due to its characteristics, tungsten 6
Selectivity between the aluminum 1 and the polyimide resin 3 can be ensured favorably.
次いで、有機膜3をヒドラジンヒトラードとエチレンジ
アミンとの混合液によりエッチ除去して第2図(f)に
示される状態とし、電極7を形成すると第1図に示され
る半導体装置が得られることになる。Next, the organic film 3 is etched away using a mixed solution of hydrazine hydrogen chloride and ethylene diamine to form the state shown in FIG. 2(f), and the electrode 7 is formed to obtain the semiconductor device shown in FIG. Become.
その結果、上記第1の実施例の半導体装置の製造方法に
よれば次のような効果を得ることができる。As a result, according to the method of manufacturing a semiconductor device of the first embodiment, the following effects can be obtained.
すなわち、タングステンよりなる高融点金属をアルミニ
ウムよりなる金属配IjAl上の任意の部位(スルーホ
ール内)にのみ選択的に気相成長させるにあたり、前記
任意の部位(スルーホール内)以外の部位を、選択気相
成長時の温度に耐え得る耐熱性を有するポリイミド系樹
脂よりなる有機膜3で覆うようにしたので、高融点金属
の高温なる選択気相成長時において、有機膜3が溶融す
ることなく選択マスクとしての機能を充分果たすと共に
、そのマスクには有機膜3の特性から該高融点金属が付
着・成長することはないという作用によって、この任意
の部位(スルーホール内)以外の部位に付着していた高
融点金属の除去工程が不要となり、製造プロセスの簡略
化を図ることが可能となる。That is, when selectively vapor-depositing a high-melting point metal made of tungsten only on an arbitrary part (inside the through-hole) on the metal interconnection IjAl made of aluminum, a part other than the above-mentioned arbitrary part (inside the through-hole) is Since it is covered with an organic film 3 made of a polyimide resin having heat resistance that can withstand the temperature during selective vapor phase growth, the organic film 3 will not melt during selective vapor phase growth at high temperatures of high melting point metals. In addition to fully functioning as a selective mask, the high melting point metal does not adhere to or grow on the mask due to the characteristics of the organic film 3, so that it does not adhere to any part other than this arbitrary part (inside the through hole). This eliminates the need for the process of removing high-melting point metals, which has been previously used, making it possible to simplify the manufacturing process.
なお、この第1の実施例においては、万が一ポリイミド
系樹脂3上にタングステンが付着するような間違いがあ
った場合のことも考えて、該ポリイミド系樹脂3を除去
するようにしているが、このポリイミド系樹脂3を除去
せずに残したまま電極7を形成し、第3図に示される半
導体装置とすることも勿論可能である。この場合1層間
膜として平坦性に優れたポリイミド系樹脂13を用いる
ようにしているので、多層構造をなす半導体装置の加工
性がさらに向上されるという効果も得られるようになっ
ている。In this first embodiment, the polyimide resin 3 is removed in case there is a mistake such as tungsten adhering to the polyimide resin 3. Of course, it is also possible to form the electrode 7 while leaving the polyimide resin 3 without removing it, and to obtain the semiconductor device shown in FIG. 3. In this case, since the polyimide resin 13 having excellent flatness is used as the interlayer film, it is possible to further improve the processability of the semiconductor device having a multilayer structure.
第4図には本発明に係る半導体装置の製造方法の第2の
実施例を適用して得られた半導体装置が示されている。FIG. 4 shows a semiconductor device obtained by applying the second embodiment of the method for manufacturing a semiconductor device according to the present invention.
この第2の実施例の半導体装置が先の第1の実施例のそ
れと違う点は、無機絶縁膜2の機能をポリイミド系樹脂
よりなる有機膜23に持たせるようにした、すなわち無
機絶縁膜2を不要とした点である。The semiconductor device of this second embodiment differs from that of the first embodiment in that the function of the inorganic insulating film 2 is given to an organic film 23 made of polyimide resin, that is, the inorganic insulating film 2 The point is that it is no longer necessary.
この第2の実施例の半導体装置の製造方法の一例を第5
図(a)〜第5図(c)に基づいて説明する。An example of the method for manufacturing the semiconductor device of this second embodiment is described in the fifth example.
This will be explained based on FIG. 5(a) to FIG. 5(c).
先ず、例えばシリコンよりなる半導体基板5上の全面に
、400〜450℃迄の耐熱性を有する例えばポリイミ
ド系樹脂よりなる有機膜23を塗付、成膜し、第5図(
a)に示される状態とする。First, an organic film 23 made of, for example, a polyimide resin having heat resistance up to 400 to 450° C. is coated and formed on the entire surface of a semiconductor substrate 5 made of, for example, silicon, and then the film shown in FIG.
Set the state shown in a).
次いで、02反応性イオンエツチング耐性を有するSi
含有ホトレジスト14を塗付し、周知のホトリソ技術に
より感光、現像して金属配線1上の任意の位置のスルー
ホールパターンをSi含有ホトレジスト14に転写し、
第S図(b)に示される状態とする。Next, Si with 02 reactive ion etching resistance
A Si-containing photoresist 14 is applied, exposed and developed using a well-known photolithography technique, and a through-hole pattern at an arbitrary position on the metal wiring 1 is transferred to the Si-containing photoresist 14.
The state shown in FIG. S(b) is established.
次に、02反応性トライエツチング技術により上記Si
含有ホトレジスト14上のパターンを下層の有機膜23
に転写し、その後レジスト除去液を用いてSi含有ホト
レジスト14を剥離して第5図(c)に示される状態と
する。Next, the above Si
The pattern on the containing photoresist 14 is transferred to the underlying organic film 23.
After that, the Si-containing photoresist 14 is peeled off using a resist removal solution to obtain the state shown in FIG. 5(c).
次いで、この状態、すなわちスルーホールパターン以外
の部位を有機膜23で覆った状態で5例えばタングステ
ンよりなる高融点金属の選択気相成長を約300〜35
0 ’Cの温度で行ない5透孔部にのみ選択的にタング
ステン16を成長させると、第4図に示される半導体装
置が得られることになる。Next, in this state, that is, with the parts other than the through hole pattern covered with the organic film 23, selective vapor phase growth of a high melting point metal such as tungsten is performed for about 30 to 35 minutes.
If tungsten 16 is selectively grown only in the 5-hole portion at a temperature of 0'C, the semiconductor device shown in FIG. 4 will be obtained.
このように、第2の実施例においても上記第1の実施例
の半導体装置の製造方法によるのと同様な効果、すなわ
ち任意の部位(スルーホール内)以外の部位に付着して
いた高融点金属の除去工程が不要となり、製造プロセス
の簡略化を図ることが可能となるという効果が得られる
ようになっている。In this way, the second embodiment also has the same effect as that achieved by the semiconductor device manufacturing method of the first embodiment, that is, the high melting point metal adhered to a region other than the arbitrary region (inside the through hole). This eliminates the need for the removal process, and the manufacturing process can be simplified.
そして、第3の実施例として、第4図に示される半導体
装置の有機膜23をヒドラジンヒトラードとエチレンジ
アミンとの混合液によりエッチ除去すれば、第6図に示
される柱状を形成することができる。As a third example, if the organic film 23 of the semiconductor device shown in FIG. 4 is etched away using a mixed solution of hydrazine hydrogen chloride and ethylene diamine, the columnar shape shown in FIG. 6 can be formed. .
この柱状の形成は、従来においてはリフトオフ法により
なさ肛でおり異物等の付着があり量産性に乏しいという
問題点があったが、この第3の実施例の製造方法により
形成すればそのような問題が回避されるという利点があ
る。Conventionally, the formation of this columnar shape was done by the lift-off method, which had the problem that it was difficult to mass-produce due to the adhesion of foreign matter, but if it is formed by the manufacturing method of this third embodiment, such a problem can be avoided. The advantage is that the problem is avoided.
第7図には本発明に係る半導体装置の製造方法の第4の
実施例を適用して得られた半導体装置が示されている。FIG. 7 shows a semiconductor device obtained by applying the fourth embodiment of the method for manufacturing a semiconductor device according to the present invention.
この第4の実施例の半導体装置にあっては、選択気相成
長により形成されたタングステンよりなる高融点金属が
半導体チップ15の上面より突出しており、ポンディン
グパッド26として機能している。In the semiconductor device of this fourth embodiment, a high melting point metal made of tungsten formed by selective vapor phase epitaxy protrudes from the upper surface of the semiconductor chip 15 and functions as a bonding pad 26.
この第4の実施例の半導体装置の製造は、先ず、例えば
シリコンよりなる半導体基板5上の全面に、例えばS
i O,よりなる無機層間絶縁膜12.400〜450
℃迄の耐熱性を有する例えばポリイミド系樹脂よりなる
有機膜33、Si含有ホトレジストをその順で順次塗付
、成膜し、次いで周知のホトリソ技術により感光、現像
して金属配線1上の任意の位置のスルーホールパターン
をSi含有ホトレジストに転写し、次に、02反応性ド
ライエツチング技術により上記Si含有ホトレジスト上
のパターンを下層の有機膜33に転写し、次に、レジス
ト除去液を用いてSi含有ホトレジストを剥離し、有機
膜33を加工マスクとしたCF、系ガス中における反応
性イオンエツチング技術により、無機層間#@縁膜12
に上記スルーホールパターンを透孔し、次に、上記有機
膜33を残した状態、すなわちスルーホールパターン以
外の部位を有機膜33で覆った状態で、例えばタングス
テンよりなる高融点金属の選択気相成長を約300〜3
50’Cの温度で行ない、透孔部にのみ選択的にタング
ステンを成長させ、第8図に示される状態とする。To manufacture the semiconductor device of this fourth embodiment, first, for example, S
i O, inorganic interlayer insulating film 12.400-450
An organic film 33 made of, for example, a polyimide resin having a heat resistance of up to The through-hole pattern at the position is transferred to the Si-containing photoresist, and then the pattern on the Si-containing photoresist is transferred to the underlying organic film 33 using the 02 reactive dry etching technique. The photoresist contained therein is peeled off, and the inorganic interlayer #@edge film 12 is removed using reactive ion etching technology in CF and gases using the organic film 33 as a processing mask.
The above-mentioned through-hole pattern is penetrated, and then, with the above-mentioned organic film 33 remaining, that is, the parts other than the through-hole pattern are covered with the organic film 33, a selective vapor phase of a high melting point metal such as tungsten is applied. Growth about 300-3
The process is carried out at a temperature of 50'C, and tungsten is selectively grown only in the through-hole portions, resulting in the state shown in FIG.
そして、有機膜33をヒドラジンヒトラードとエチレン
ジアミンとの混合液によりエッチ除去し、この除去によ
り突呂するタングステンよりなるポンディングパッド2
6にインナーリード30を接続すると第7図に示される
半導体装置が得られることになる。Then, the organic film 33 is removed by etching with a mixed solution of hydrazine hydrogen chloride and ethylene diamine, and this removal causes the pad 2 made of tungsten to be exposed.
When the inner lead 30 is connected to 6, the semiconductor device shown in FIG. 7 is obtained.
このように、本発明は上記ボンディング技術に対しても
応用することが可能となっている。In this way, the present invention can also be applied to the above-mentioned bonding technology.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが1本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor.
例えば、上記各実施例においては、専ら金属配線1にコ
ンタクトするスルーホールに対しての適用例が述べられ
ているが、本発明は半導体基板5表面に形成される拡散
層にコンタクトするコンタクトホールに対しても同様に
適用可能である。For example, in each of the above embodiments, application examples are described exclusively to through holes that contact metal wiring 1, but the present invention is applicable to contact holes that contact diffusion layers formed on the surface of semiconductor substrate 5. The same applies to
また、上記各実施例においては、高融点金属6゜16.
26をタングステンとしているがタングステンに限定さ
れるものではなく、選択気相成長を行ない得る高融点金
属であれば何でも良い。Further, in each of the above embodiments, the high melting point metal is 6°16.
Although tungsten is used as 26, it is not limited to tungsten, and any high melting point metal that can perform selective vapor phase growth may be used.
また、半導体基板5をシリコン、金属配線1をアルミニ
ウムとしているがこれらに限定されるものではなく、要
は高融点金属の選択気相成長性が良い材質であればなん
でも良い。Further, although the semiconductor substrate 5 is made of silicon and the metal wiring 1 is made of aluminum, the material is not limited to these, and any material may be used as long as it has good selective vapor phase growth properties of a high melting point metal.
また同様に、有機膜3,13,23.33をポリイミド
系樹脂としているがポリイミド系樹脂に限定されるもの
ではなく、高融点金属の選択気相成長時の温度に耐え得
る耐熱性を有すると共に高融点金属の付着・成長がなさ
れない有ia膜であれば何でも良い。Similarly, although the organic films 3, 13, 23, and 33 are made of polyimide resin, they are not limited to polyimide resins, and have heat resistance that can withstand the temperature during selective vapor phase growth of high melting point metals. Any ia film may be used as long as it does not allow attachment or growth of high melting point metals.
さらにまた、無機絶縁膜2,12を5in2としている
がプラズマ酸化膜の3層膜等を用いることも可能である
。Furthermore, although the inorganic insulating films 2 and 12 are 5 in 2 in size, it is also possible to use a three-layer film of plasma oxide film or the like.
[発明の効果]
水頭において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば下記のとおりである
。[Effects of the Invention] The effects obtained by the typical inventions disclosed in Suito are briefly described below.
すなわち、高融点金属を半導体基板かつ/または金属配
線上の任意の部位にのみ選択的に気相成長させるにあた
り、前記任意の部位以外の部位を、選択気相成長時の温
度に耐え得る耐熱性を有する有機膜で覆うようにしたの
で、高融点金属の高温なる選択気相成長時において、有
機膜が溶融することなく選択マスクとしての機能を充分
果たすと共に、そのマスクには有機膜の特性から該高融
点金属が付着・成長することはない。その結果、この任
意の部位以外の部位に付着していた高融点金属の除去工
程が不要となり5製造プロセスの簡略化を図ることが可
能となる。In other words, when selectively vapor-depositing a high-melting point metal only on an arbitrary part on a semiconductor substrate and/or metal wiring, parts other than the above-mentioned arbitrary parts must have heat resistance that can withstand the temperature during selective vapor-phase growth. Since the organic film is covered with an organic film having a high melting point metal, it does not melt during selective vapor phase growth at high temperatures and functions as a selective mask without melting. The high melting point metal does not adhere or grow. As a result, the step of removing the refractory metal adhering to parts other than this arbitrary part becomes unnecessary, making it possible to simplify the manufacturing process.
第1図は本発明に係る半導体装置の製造方法の第1の実
施例を適用して得られた半導体装置の縦断面図、
第2図(a、 )〜第2図(f)は同上第1の実施、例
の各工程図、
第3図は、本発明に係る半導体装置の製造方法の第1の
実施例を応用して得られた半導体装置の縦断面図、
第4図は本発明に係る半導体装置の製造方法の第2の実
施例を適用して得られた半導体装置の縦断面図、
第5図(a)〜第5図(c)は同上第2の実施例の各工
程図、
第6図は本発明に係る半導体装置の製造方法の第3の実
施例を適用して得られた半導体装置の縦断面図、
第7図は本発明に係る半導体装置の製造方法の第4の実
施例を適用して得られた半導体装置の縦断面図、
第8図は同上第4の実施例の工程図である。
1・・・・金属配線、3,13,23.33・・・・有
機膜、5・・・・半導体基板、6,16.26・・・・
高融点金属。
第 2 図
(b)
第
2
図
((1)
第
図
第
図
第
図
+01FIG. 1 is a vertical cross-sectional view of a semiconductor device obtained by applying the first embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIGS. FIG. 3 is a vertical cross-sectional view of a semiconductor device obtained by applying the first embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 5(a) to 5(c) are longitudinal cross-sectional views of a semiconductor device obtained by applying the second embodiment of the semiconductor device manufacturing method according to the above. 6 is a vertical cross-sectional view of a semiconductor device obtained by applying the third embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. FIG. 8 is a longitudinal sectional view of a semiconductor device obtained by applying the fourth embodiment, and FIG. 8 is a process diagram of the fourth embodiment. 1...Metal wiring, 3,13,23.33...Organic film, 5...Semiconductor substrate, 6,16.26...
High melting point metal. Figure 2 (b) Figure 2 ((1) Figure Figure Figure +01
Claims (3)
の任意の部位にのみ選択的に気相成長させるにあたり、
前記任意の部位以外の部位を、選択気相成長時の温度に
耐え得る耐熱性を有する有機膜で覆うようにしたことを
特徴とする半導体装置の製造方法。1. When selectively vapor-depositing a high-melting point metal only on an arbitrary location on a semiconductor substrate and/or metal wiring,
A method for manufacturing a semiconductor device, characterized in that parts other than the arbitrary parts are covered with an organic film having heat resistance that can withstand temperatures during selective vapor growth.
とする特許請求の範囲第1項記載の半導体装置の製造方
法。2. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the organic film is made of polyimide resin.
とする特許請求の範囲第1項または第2項記載の半導体
装置の製造方法。3. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the high melting point metal is tungsten.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1140571A JP2799731B2 (en) | 1989-06-01 | 1989-06-01 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1140571A JP2799731B2 (en) | 1989-06-01 | 1989-06-01 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH036024A true JPH036024A (en) | 1991-01-11 |
JP2799731B2 JP2799731B2 (en) | 1998-09-21 |
Family
ID=15271784
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JP1140571A Expired - Fee Related JP2799731B2 (en) | 1989-06-01 | 1989-06-01 | Method for manufacturing semiconductor device |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0653331A (en) * | 1992-07-31 | 1994-02-25 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60111421A (en) * | 1983-11-22 | 1985-06-17 | Toshiba Corp | Manufacture of semiconductor device |
-
1989
- 1989-06-01 JP JP1140571A patent/JP2799731B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60111421A (en) * | 1983-11-22 | 1985-06-17 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0653331A (en) * | 1992-07-31 | 1994-02-25 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
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