JPH0358623A - Clocked inverter circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction due to the effect of noise at a power supply by connecting a MOS transistor(TR) to a common connecting point of main electrodes of 1st and 2nd MOS TRs. CONSTITUTION:P-channel MOS TRs T1, T2 and N-channel MOS TRs T3, T4 are connected in series between a Vcc power voltage and GND (ground). The source of an N-channel MOSTR T5 is grounded and the drain is connected to a common connecting point of the TRs T1, T2. With an input signal A logical '1', with the TR T1 turned off and a clock signal PHI at logical '0', the TRs T2, T3 are turned off, and the TR T5 is turned on. In such a case, even when power supply noise is generated, and the TR T1 is turned on, since the drain of the TR T1 is at a ground level, the TR T2 is not turned on. Thus, even when power noise takes place, no malfunction is caused.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clocked inverter circuit, and particularly to a clocked inverter constructed from a semiconductor integrated circuit.

[Conventional technology]

FIG. 2 is a circuit diagram showing a conventional clocked inverter circuit. In FIG. 2, depending on the clock signal Φ,
This is a circuit in which the output O can have a high impedance state when the transistors T3 and T2 are turned off.

Initially, input signal A is I+1. 1+, l- transistor T1 is OFF, transistor T4 is ON, clock signal Φ is "1'", and clock signal group is "0", transistor T3 is ON, transistor T2 is ON, and output O is grounded. level, and the charge in the load capacitor c is discharged.Next, when the clock signal Φ is set to II O and the II clock signal group is set to ``'1'', the output 0 becomes high impedance. At that time, noise is generated in the power source, which is the source electrode of the transistor T1, and when the source electrodes of the transistors Tl and T2 become positive voltages, the gate-source voltage exceeds the threshold value. Then, transistors Tl, T2
is turned on and the load capacitor C of the output O is charged with charge, causing malfunction. Transistors T2, T3, T4 are OFF
However, when the output O is in a high impedance state, if noise occurs in the power supply that is the source electrode of the transistor T1, the voltage between the gates and sources of the P-channel transistors TI and T2 changes, causing the transistors Tl and T2 to become O
NL, the load capacitance C of the output O may be charged and malfunction may occur.

[Problem to be solved by the invention]

The conventional clocked inverter circuit described above has a drawback that when noise occurs in the power source, which is the source electrode of the transistor T1, the transistors Tl and T2 may turn on and malfunction.

An object of the present invention is to provide a clock device that does not malfunction even when power supply noise occurs. The purpose of the present invention is to provide a converter circuit.

[Means for Solving the Problems] According to the structure of the present invention, a series body of first and second one-channel MOS transistors and a series body of third and fourth other-channel MOS transistors are connected in series. , the series connection point thereof is used as an output terminal, the gates of the first and fourth MOS transistors are commonly connected and used as an input terminal, the gates of the second and third MOS transistors are respectively clock input signal terminals, In the clocked inverter circuit, the first and second MO
The present invention is characterized in that a multi-channel MOS transistor is provided in which the common connection point of the main electrodes of the S transistors is the -main electrode, the ground is the other main electrode, and the gate is the clock input negative phase signal input terminal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a clocked inverter circuit according to an embodiment of the present invention.

In FIG. 1, the closed-circuit inverter circuit of this embodiment has a P-channel MOS transistor T. 1, T2, and N channel MOS transistors T3 and T4 are all connected in series, and the gates of transistor TI and transistor T4 are connected in common to serve as an input. A clock signal is input to the gate of transistor T2, and the gate of transistor T3 is input to the gate of transistor T2. A clock signal is input to the terminal, the common connection point of the transistors T2 and T3 is used as an output, the source of the N-channel MOS transistor T5 is grounded, and the drain is connected to the transistor T.
It is connected to the common connection point of I and T2, and its gate serves as an electrode to which the clock signal Φ is input.

In order to prevent the above-mentioned malfunction, transistors T2,
The drain electrode of the transistor T5 is connected to the common connection part of Tl, and when the input signal A is "1'", the transistor T1 is turned off, and the clock signal Φ becomes "1". T3 is OFF
L, transistor T5 is turned on, transistor T2,
The TI common connection is stable at ground level voltage.

At this time, even if power supply noise 5 occurs and the transistor TI turns ON, the drain electrode of the transistor T1 is at the ground voltage, so the transistor T2 does not turn ON and is not affected by the power supply noise.

〔Effect of the invention〕

As described above, the present invention has the effect of preventing malfunctions due to the influence of power supply noise by connecting MOS transistors.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a clocked inverter circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional clocked inverter circuit. A...Gate input signal, Φ...Clock signal, Distortion...Clock reverse phase signal, O...
...Transistor output, Vcc...Power supply voltage,
GND...Grounding, C...Load capacity, Tl
, T2...P channel MOS transistor, T
3, T4, T5...N channel MOS transistor.

Claims (1)

[Claims] A series body of first and second one-channel MOS transistors and a third and fourth series body of other-channel MOS transistors are connected in series, and the series connection point is used as an output terminal;
The gates of the first and fourth MOS transistors are commonly connected to serve as an input terminal, and the gates of the second and third MOS transistors are used as a clock input signal terminal and a clock input negative phase signal terminal, respectively. In the inverter circuit, a multi-channel MOS transistor is provided in which the common connection point of the main electrodes of the first and second MOS transistors is one main electrode, the ground is the other main electrode, and the gate is the clock input negative phase signal input terminal. A clocked inverter circuit characterized in that: