JPH0349461Y2 - - Google Patents

Description

[Detailed description of the invention] (a) Industrial application field The present invention relates to a transistor circuit for generating a signal according to the level difference between two common-mode signals.
In particular, the present invention relates to a transistor circuit suitable for use in an IC (integrated circuit) rectifier circuit.

(b) Prior Art Conventionally, as shown in FIG. 1, a rectifier circuit using a diode 1 is known. In the rectifier circuit shown in FIG. 1, a predetermined voltage V _R is applied to the cathode of the diode 1 by a DC power supply 2.
When an input signal of [V _D + V _R ] (where V _D is the forward voltage of the diode) or more is applied, the output terminal 3
It is configured so that an output signal is generated. Therefore, if an AC input signal that changes between positive and negative is applied as an input signal, only a positive output signal will be generated at the output terminal 3, and the input signal will be rectified. However, in the rectifier circuit shown in Figure 1, a DC voltage is generated at the output terminal 3, so a DC cut capacitor is required to obtain only an AC signal, and the DC level on the input and output sides must be matched. Because it is difficult to integrate the circuit into an IC, it is not suitable for IC implementation.

Further, a differential type rectifier circuit as shown in FIG. 2 is also known. This rectifier circuit includes first and second differential transistors 4 and 5 whose emitters are commonly connected.
, a constant current source 6 connected to the common emitters of the first and second differential transistors 4 and 5, and an output transistor 7 whose base is connected to the collector of the first transistor 4, and has an input terminal. 8
The output terminal 9 generates an output signal corresponding to an input signal applied to the output terminal 9. In the circuit of FIG. 2, the base of the first differential transistor 4
A DC bias voltage of V _B1 is applied, and a DC bias voltage of V _B2 is applied to the base of the second differential transistor 5. V _B1 < V _B2 is set so that no output signal is generated when there is no signal. There is. and,
With respect to the AC input signal Vin applied to the input terminal 8, the output signal is generated when Vin + V _B1 > V _B2 , so the rectifier generates the output signal at exactly half the wave of the input signal Vin. It has an effect.

However, the circuit shown in FIG. 2 has the disadvantage that the rectification level changes due to fluctuations in the DC bias voltage, and therefore, like the case shown in FIG. 1, it is not suitable for IC implementation.

(c) Purpose of the invention The present invention has been made in view of the above-mentioned points, and aims to provide a transistor circuit that operates stably and correctly as an IC-based rectifier circuit.

(d) Structure of the invention The transistor circuit according to the invention includes first and second differential transistors whose emitters are commonly connected, an input end of which is connected to the collector of the first differential transistor, and an output end of which is connected to the collector of the first differential transistor. The current mirror circuit is connected to the collectors of the second differential transistors and has a mirror ratio of 1:n, and an output transistor whose base is connected to the collector of the second differential transistor.

(e) Embodiment Figure 3 is a circuit diagram showing an embodiment of the present invention.
10 and 11 are first and second differential transistors whose emitters are commonly connected; 12 is the first and second differential transistor;
A constant current source 13 is connected to the common emitter of the differential transistors 10 and 11, and the input terminal of the constant current source 13 is connected to the collector of the first differential transistor 10, and the output terminal is connected to the collector of the second differential transistor 11. A current mirror circuit; 14 is a PNP type output transistor whose base is connected to the collector of the second differential transistor 11 and whose emitter is connected to the power supply (+V _CC ); 15 and 16 are the first and second differential transistors, respectively; First and second input terminals are connected to the bases of 10 and 11, and 17 is an output terminal connected to the collector of the output transistor 14. Therefore, the current mirror circuit 13
is composed of a first mirror transistor 18 whose collector and base are short-circuited and connected as a diode, and a second mirror transistor 19 whose base and emitter are commonly connected to the first mirror transistor 18. The emitter area ratio of the first and second mirror transistors 18 and 19 is 1:2.

Next, the operation will be explained. First and second input terminals 1
In a no-signal state in which no input signal is applied to transistors 5 and 16, it is assumed that an equal DC bias voltage is applied to the bases of the first and second differential transistors 10 and 11 by a DC bias source (not shown). Therefore, if the current flowing through the constant current source 12 is _I0 , then the first and second differential transistors 1
The collector currents of 0 and 11 are equal to I ₀ /2.

On the other hand, since the collector current I ₀ /2 of the first differential transistor 10 becomes the input current of the current mirror circuit 13 , the collector current of the first mirror transistor 18 also becomes I ₀ /2. It is assumed that a collector current of I ₀ flows into the collector of the second mirror transistor 19 which has a 1:2 mirror relationship. However, the second differential transistor 1
Since the collector current of the second mirror transistor 19 is I ₀ /2, the collector current of the second mirror transistor 19 cannot exceed I ₀ /2.
The above relationship is maintained in a state where the current amplification factor decreases and becomes saturated. Therefore, the output transistor 14 is never turned on, and no output signal is generated at the output terminal 17 when there is no signal.

Assume that an input signal shown in solid line A in FIG. 5 is applied to the first input terminal 15, and an input signal shown in dashed line B in FIG. 5 is applied to the second input terminal 16. Then, in the positive half cycle of the input signal, the base voltage of the first differential transistor 10 becomes higher than the base voltage of the second differential transistor 11, and the first differential transistor 10 is turned on and the second differential transistor 10 is turned on. Since the dynamic transistor 11 is turned off,
As in the case of no signal, the output transistor 14 remains off. On the other hand, in the negative half cycle of the input signal, the base voltage of the first differential transistor 10 becomes lower than the base voltage of the second differential transistor 11, the first differential transistor 10 is turned off, and the second differential transistor 10 is turned off. Since the dynamic transistor 11 is turned on, the output transistor 14 is also turned on, current flows through the load resistor 20, and an output signal is generated at the output terminal 17. The output transistor 14 is turned on when the base current begins to flow, and the condition for this is when the collector current of the second differential transistor 11 becomes slightly larger than the collector current of the second mirror transistor 19. That is, if the collector current of the first differential transistor 10 is I ₁ and the collector current of the second differential transistor 11 is I ₂ , then the collector current I ₃ of the second mirror transistor 19 is I ₃ =I ₂ =
When 2I ₁ , the output transistor 14 starts to turn on. Considering this state from the transfer curve of a differential circuit, when a voltage difference of approximately 50 mV occurs between input signals, the collector currents I ₁ , I ₂ and I ₃ will have the above relationship, and the output transistor 14 will turn on. I'm about to start. Then, the voltage difference between the input signals is
As the voltage exceeds 50mV, the output transistor 14
The collector current of the output transistor 14 increases, and the collector current of the output transistor 14 becomes proportional to the level difference of the input signals.

Therefore, by using the transistor circuit shown in FIG. 3 and applying AC input signals of the same phase and different levels to the first and second input terminals 15 and 16, an output signal corresponding to the level difference can be obtained at the output terminal 17. rectification of the alternating current signal is achieved.

The mirror ratio of the current mirror circuit 13 shown in FIG. 3 is set by using a circuit as shown in FIG. 4, for example. In the case of FIG. 4, the first to third mirror transistors 21 to 23 are composed of equal transistors, and the bases and emitters of the first to third mirror transistors 21 to 23 are commonly connected to each other, and The collectors of the second and third mirror transistors 22 and 23 are commonly connected. Therefore, if the collector current of the first mirror transistor 21 is I ₄ , the collector currents of the second and third mirror transistors 22 and 23 are also I ₄ , which is twice the current I ₄ flowing to the input terminal 24. A current 2I ₄ can be obtained at the output terminal 25. Therefore, if you do as shown in Figure 4,
A current mirror circuit with a mirror ratio of 1:2 can be easily obtained. Incidentally, the mirror ratio of the current mirror circuit 13 shown in FIG. 3 can be arbitrarily set according to the design. If the mirror ratio n is increased, the rectification efficiency for the same input signal will decrease,
Conversely, if the mirror ratio n is made small, the rectification efficiency increases.

(f) Effect of the invention As mentioned above, according to the invention, the mirror ratio between the collectors of the differential transistor is 1:n (however,
Since the present invention has a configuration in which current mirror circuits (n>1) are connected, a transistor circuit that does not malfunction when there is no signal can be provided. Further, since it is possible to obtain an output signal corresponding to the level difference of the input signals according to the mirror ratio of the current mirror circuit, it is possible to provide a transistor circuit suitable for use in a rectifier circuit. Furthermore, the transistor circuit according to the present invention is stable against variations in circuit elements and temperature changes, so it is particularly
Suitable for use in ICs.

[Brief explanation of drawings]

1 and 2 are circuit diagrams showing a conventional rectifier circuit, and FIG. 3 is a circuit diagram showing an embodiment of the present invention.
FIG. 4 is a circuit diagram showing a specific example of the current mirror circuit, and FIG. 5 is a characteristic diagram showing input signals used in the present invention. Explanation of main figure numbers, 10, 11...Differential transistor, 13 ...Current mirror circuit, 14...Output transistor.

Claims (1)

[Scope of utility model registration request] a first conductivity type whose emitters are commonly connected;
and a second differential transistor, an input terminal of which is connected to the first differential transistor.
a current mirror circuit configured with a transistor of a second conductivity type, the output end of which is connected to the collector of the second differential transistor, and the base of which is connected to the collector of the second differential transistor; and a second conductivity type output transistor connected to each other, the mirror ratio of the current mirror circuit is 1:n (however, n>1), and the bases of the first and second differential transistors have a frequency and 1. A transistor circuit, wherein two input signals having the same phase and different levels are applied, and the output transistor obtains an output corresponding to a difference between the two input signals.