JPH0348528A - A/d converter - Google Patents

Abstract

PURPOSE:To execute the operation by a single power source without reducing an input range of an analog signal and to prevent the reduction of a dynamic range of a circuit by executing a comparing operation of a differential amplifier within a range extending from the ground potential to the power source potential. CONSTITUTION:In a capacity array 10, binary weighted capacities 10b, 10c and 10d, etc., are placed in parallel. To a first electrode side of this array 10, a first reference potential between the ground potential and the power source potential is given, and also, an analog signal value brought to digital conversion is given to a second electrode of the array 10. Subsequently, to a second electrode side of this array 10, a first reference potential is given, and to a second electrode side of each capacity of the array 10, a second reference potential of the power source potential being a higher potential than a first reference potential or a third reference potential of the ground potential being lower potential is given. Next, the potential of a first electrode side is compared 17 with a first reference potential, and from its result, a control circuit 16 generates digital data, and also, brings supply of the reference potential to the array 10 to switching control.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a charge redistribution type A/D converter with a binary weighted capacitor array. (b) Prior Art FIG. 3 is a circuit diagram of a conventional charge redistribution type A/D converter, and shows the case of a 4-bit configuration. Binary weighted capacitor array (1) is composed of five capacitors (1a) to (1e) with capacitances of 8C, 4C, 2C, and C, respectively, in the case of a 4-bit configuration. The first electrodes of the capacitors (1a) to (1e) are connected in common and grounded via the switch (2>),
The second electrodes are connected to the changeover switches (3a> to (3e)). One end of each changeover switch (3a> to (3e)) is grounded, and the other end is connected to the changeover switch (4>). The changeover switch (4) receives the reference voltage v6 on one side and receives the analog signal v, on the other side.These switches (3a) to (3e), (4), and (2) will be described later. Switching control signal SC from control logic (5)
The switching is controlled according to the following.

The first electrode side of the capacitor array <1) is connected to the switch (2>) and to the inverting input side of the differential amplifier (6>).The non-inverting input side of the differential amplifier (6) is grounded. Therefore, if the potential vx on the first electrode side of the capacitor array (1) is negative, the output of the differential amplifier (6) becomes r'0 if 1 is positive. The output of (6) is input to the control logic (5), and the digital data D.U7
is created. Furthermore, in the control logic (5>, the switching control signal SC.~S based on the output state of the differential amplifier (6>)
C. is created, and each switch (3a) to (3e),
(4) and (2>).

Next, the operation of the circuit will be explained.

FIG. 4 is a timing diagram of the switch operation of FIG. 3.

Here, each switch (3a> to (3e> and (4)) is switched to the H side shown in FIG. 3 when each switching control signal SC, to SC. and switch (
2> is turned on when the switching control signal SC is "1".

First, during the sampling period, the switching control signal SC. ~SC. becomes l″1” and each switch (3a) to (3e) (4)
is switched to the H side and switch (2) is turned on,
An analog signal v4 is applied to the second electrode side of each capacitor (1a) to (1e), and an analog signal v4 is applied to the second electrode side of each capacitor (1a) to (1e).
> husband/r8CV,. ,4CV,. , 2CV, N. CV
IN. The amount of charge of C V I N is accumulated. and,
During the hold period, the switching control signal S''C.~SC, is rO''
When each switch (3a> to (3e) is switched to the L side and the switch (2) is turned off, each capacitor (1
The second electrode side of a> to (1e) is lowered to the ground potential, and the potential of the first electrode side in the floating state is =
■, becomes. At this time, capacitor (la) ~ <1e)
The total amount of charge stored in is 16CV+s, and this amount of charge is held.

Next, when the switch (3a) is switched to the H side again during the MSB determination period, the second electrode of the capacitor (1a)
is applied, and the amount of charge held during the hold period is distributed to each capacitor (1a) to (1e). This charge distribution is such that the potentials between the two electrodes of the capacitors (1a) to (1e) are equal, and the potential of the second electrode of the capacitor (1a) is equal to the potential of the second electrode of the capacitors (1b) to (1e). Therefore, the capacitance of capacitor <1a> and capacitors (1b) to (
1e) are equal to each other, the potential V x on the first electrode side becomes V IN + V */2, and this v8 is compared with the ground potential in the differential amplifier <6>. Therefore, if the analog signal VIN is higher than v8/2,
v8 becomes negative, the output of the differential amplifier (6) becomes "1", and the control logic (5) determines the MSB to be "1". Conversely, if the analog signal ■1,l is lower than V,/2, then
v8 becomes positive and the MSB is determined to be OJ.The control logic (5) determines the MSB and also outputs the switching control signal SC.
When the MSB is "r1", the switching control signal SC1 is maintained at "r1", and when it is "0", it is set to "0" in the next period (B2 determination period).

If the MSB is determined to be "1", in the continuation<B2 determination period, the switch (3a) remains on the H side and the switch (3b> is switched to the H side. Then, vx becomes -v1N+V*
/ 2 + V */ 4, and the second bit (B2) is determined in the same way as the MSH determination depending on the sign of vx. That is, Vx is 3V. If it is higher than /4, Vx is negative and B2 is determined to be r1, and V. If is lower than 3vll/4, v8 becomes positive and B2 becomes 0.

On the other hand, if the MSB is determined to be "0", in the subsequent B2 determination period, the switch (3a) is switched to the L side, and the switch (3b) is switched to the H side. Therefore, Vx is -V
IN+ V */ 4 Tonari, Ko・(7) V x
(7) B2 is determined depending on whether it is positive or negative. Hereinafter, the third bit (
B3) and LSB are determined in the same manner as B2. Therefore, by switching each switch (3a) to (3e) in sequence, vx is brought close to the ground potential, and the final switch (
The states 3a> to (3e) are digital data D. u. It will represent r. Therefore, the control logic (5) summarizes the MSB-LSB obtained serially in each determination period,
4-bit digital data D. (Output as 1?

Such a charge redistribution type A/D converter is, for example, IE
E E J. Solid State Circuit
ts, Vol. SC-LO, Na6, 'A
ll-MOS Charge Redistribution
ionAnalog-to-Digital Conv
The detailed explanation is given in ``Ersion Techniques-Part 1''.

(c) Problems to be Solved by the Invention In the A/D converter as described above, comparison of potentials is performed in the differential amplifier (6) in the range of -v,/2 to v,/2. Therefore, in order to operate the differential amplifier (6), two power supplies are required, one for the first side and one for the first side. A/ like this
D converters are usually integrated into ICs, and the need for multiple power sources is an obstacle when integrated into ICs. It is also possible to operate the differential amplifier (6) with a single power supply, but since the input range of the differential amplifier (6) is 1/2 of that in the case of two single-source operation, the input range of the analog signal is limited. There is a problem in that the input range is reduced to 1/2.Therefore, an object of the present invention is to provide an A/D converter that can be operated with a single power supply without reducing the input range of analog signals.

(2) Means for solving the problems The present invention has been made to solve the above problems,
A capacitor array in which a plurality of binary weighted capacitors are arranged in parallel, and a first reference potential is applied to the first electrode side of the capacitor array, and an analog signal value to be digitally converted is applied to the second electrode of the capacitor array. means for applying the first reference potential to the second electrode side of the capacitor array; means for providing a second reference potential or a third low potential reference potential, a comparison circuit for comparing the potential on the first electrode side with the first reference potential, and digital data based on the comparison result of the comparison circuit. and a control circuit for switching and controlling the supply of each reference potential from each of the means to the capacitor array. (*) Effect According to the present invention, the second reference potential is changed from the third reference potential to the first reference potential which is the intermediate potential between the second reference potential and the third reference potential. By setting the second reference potential to the power supply potential and the third reference potential to the ground potential, the comparison circuit can be operated with a single power supply, and the analog signal value The comparison range is from ground potential to power supply potential. (F) Embodiment An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of the A/D converter of the present invention, showing the case of a 4-bit configuration. The capacitor array (10) is composed of four capacitors (10a) to (10d) with capacities of 4C, 2C, C, and C, the first electrodes of which are commonly connected, and a switch (11) to this F-th electrode. 1/2 voltage (V
*/2) is applied. Each capacitor (10a) to (1
The second electrode of 0c) is connected to the changeover switches (13a) to (13a), respectively.
13c), and these changeover switches (13a) to
(13c) is connected to the selector switch (14),
The other side is connected to the changeover switch (15>).The second electrode of the fundensor (13d) is directly connected to the changeover switch (14>).The changeover switch <14> is connected to the analog signals VIN, v l/2 and is applied, and one of them is supplied to the capacitor via the changeover switches (13a) to (13c).VR is applied to one of the changeover switches (15>), and the other is grounded. Each of these switches (13a) to (13c) (14>(15) and (11) has a control logic (16) with the same configuration as in FIG.
) The switching is controlled according to the switching control signal SC from ).

The first electrode side of the capacitor array (10) is a differential amplifier (17)
It is connected to the inverting input side of , and its potential v8 is compared with 2, /2 applied to the non-inverting input side. Therefore, if the potential ■ on the F-th electrode side of the capacitor array <10> is lower than ■II/2, the output of the differential amplifier (17>) is "1", and if it is higher, it is "0".
, becomes. The control logic (16) is the same as the control logic (5) in FIG. 3, and its explanation will be omitted. Next, we will explain the operation of the circuit. FIG. 2 is a timing diagram of the switch operation of FIG. 1.

The operation of each switch (13a) to (13c), (14), (15), and (l1) is the same as in the case of FIG. 3, using switching control signals SC+ to SCs7! l” I J (7) 8 H
side, rO”, it is switched to the L side, and the switching control signal SC
．． Suppose that it is activated when is "1".

During the sampling period, the switching control signal SC, ~SC, becomes r1, and the switch (11) turns on and each switch (
13a) to (13c) are switched to the H side, ■, /2 and VIN are applied to each capacitor (10a) to (10d), and 4C is applied to each capacitor (10a) to (10d), respectively.
(VIN VR/2), 2C (V+N v./2),
C(VsN-Vl/2), c(VIN-V
ll/2) No! Load is accumulated. Subsequently, during the MSB determination period, the switch (11) is turned off, the switch (U) is switched to the L side, and the capacitor array (1
0> to the second electrode. /2 is applied. During this period, the switch (11) is turned off and the first electrode side of the capacitor array (10) is in a bloating state, so the amount of charge accumulated in the capacitor array (10) during the sampling period is retained. is each capacitor (10a) to (10
d) Bi-distribution salertame,■! is vll/2+(Vl/2
-VIN). Then, V8 is compared with v,/2 to determine the MSB. That is, if v,N is higher than v3/2, V. liV. /2, the output of the differential amplifier (17) becomes 11'', and the control logic (l5)
determines the MSB as “1,” and conversely, if V,,l is lower than V./2, then v! becomes higher than vl/2, and the output of the differential amplifier (17) becomes rO, and the MSB is determined to be 1″0″. ? The switching control signal SC becomes "1" when the MSB is determined to be "1", and becomes "0," when the MSB becomes "0".
becomes. Until this MSB is determined, the company switching control signal S
Either is fine for C6. (Period indicated by a broken line in FIG. 2) Next, in the B2 determination period, the switch (13a) is switched to the L side, and if the MSB is "1", the capacitor (10a) is switched to the L side.
) is applied to the second electrode of the capacitor (10a), and if the MSB is "0", the second electrode of the capacitor (10a) is connected to the ground.
S B h" I J (7) TokiVthaVt/
2 + (V */ 2 +V */ 4 V I
N), and the second bit (B2) is determined from the output of the differential amplifier (17).
*/ 4 If it is higher, v8 is v. /2, the output of the differential amplifier (l7) becomes "1", and B2 becomes "1".
”, ■, H is 3V. If it is lower than /4, v8 will be higher than v, /2 and the output of the differential amplifier (17) will be "
0'' and B2 is determined to be ``0''. On the other hand, MSB
When is rO'', vx is v*/2 + (v+t/
4 VIN), and VIN becomes V. If it is higher than /4, v8 will be lower than V■/2 and B2 will be 11'', and conversely VI
N is V. If it is lower than /4, Vx is higher than v,/2 and B2 is determined to be "0".

The switching control signal SCI indicates that B2 is "1" according to the determination of B2.
”, it will be maintained at “11” after the next B3 judgment period, and B
If 2 is 10, it is maintained at 0.

Also in the B3 judgment period and the LSB judgment period, the switch (13a) (13c) is the switch (13c) in the B2 judgment period.
2a), the third bit (B3) and LSB
is determined. In other words, when the MSB is r1, Nihaconden? (10b) (10c) The magnitude of V and v1/2 is determined by alternately applying vR/2 and V to the second electrode, and when the MSB is rO, the capacitor (10b)
By applying v,/2 and the ground potential alternately to (10c),
The magnitude of x and v wi / 2 is determined. Therefore,
Switch each switch (10a) to (10c) in order to v8
V. /2, each final switch (10a) ~
The states (10c) and (15) are digital data D. I
This will represent each pit of Jr.

In this type of A/D converter, it takes five steps (in the case of 4 pits) to obtain one digital data, so it is more difficult to use than a series or series/parallel type A/D converter. Although the conversion speed is slower, the circuit configuration is much simpler than a series type, so the circuit scale can be significantly reduced, and the number of bits can be increased by adding a capacitor and a changeover switch, making it possible to increase the number of bits. Can be easily converted into bits.

(G) Effects of the Invention According to the present invention, since the comparison operation of the differential amplifier can be performed in the range from the ground potential to the reference potential, it is possible to operate with a single power supply, and the differential amplifier The input current range is sufficient and the reduction in the dynamic range of the circuit is prevented.
E I can do it.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of the A/D converter of the present invention, Figure 2 is an operation timing diagram of Figure 1, Figure 3 is a circuit diagram of a conventional A/D converter, and Figure 4 is the same as Figure 3. This is an operation timing diagram. (1), (lo)...capacitance array, (la)~
(le), (10a) to (10d)... capacitor, (2). (11)...Switch, (3a) ~(
3e), (4), (13a) ~ (13c)
, (14), <15)...changeover switch, (
5) , (16)...control logic, (6) (17
)...Differential amplifier.

Claims (2)

[Claims] (1) A capacitor array in which a plurality of binary-weighted capacitors are arranged in parallel, and a first reference potential is applied to the first electrode side of this capacitor array, and an analog signal value to be digitally converted is transferred to the capacitor. means for applying the first reference potential to the second electrode side of the array; and means for applying the first reference potential to the second electrode side of each capacitor of the capacitor array. means for providing a second reference potential with a higher potential or a third reference potential with a lower potential; a comparison circuit for comparing the potential on the first electrode side with the first reference potential; and a comparison result of the comparison circuit. a control circuit that creates digital data based on the data and switches and controls the supply of each reference potential from each of the means to the capacitor array; After applying an analog signal value and accumulating a charge amount corresponding to the analog signal value in the capacitor array, the first electrode side was brought into a floating state, and the first reference potential was applied to the second electrode side. When the potential on the first electrode side is lower than the first reference potential, the second reference potential is applied, and if the potential is higher than the first reference potential, the third reference potential is alternately applied to the capacitor array. An A/D converter characterized in that it sequentially supplies data to each capacitor. (2) The A/D converter according to claim 1, wherein the first reference potential is an intermediate potential between the second reference potential and the third reference potential.