JPH0345580B2 - - Google Patents

Description

[Brief explanation of drawings]

Figure 1 is an explanation of PLA, Figures 2 and 3 are product term memory patterns, Figures 4 and 5 are sum term memory patterns, and Figure 6 is a block diagram of the present invention. Write circuit, 2 is input register, 3 is
4 is a product term memory group, 5 is an AND circuit, 6 is a sum term memory group, 7 is an OR circuit, 8 is an output register, and 9 is a control section.

Claims (1)

[Claims] 1. An input register for storing input data from the outside, an IC register for storing an IC number from the outside, and one or more product term memories,
One or more sum term memories, an AND circuit that performs AND on the same product term line, an OR circuit that performs AND on the same sum term line, and the output result of the sum term line. controls the output register that sets the corresponding bit when is true, the input register, the product term memory, the sum term memory, and the output register.
It consists of a control unit that stores the number of blocks to be processed for each IC type, and a write circuit that writes product term and sum term patterns to the product term memory and sum term memory. The term memory selects the type of IC based on the output of the IC register, and at the location of the block number of that IC specified by the control unit, the output of the input register to the product term memory is the product term in that block. A true signal is output for the product term line that is part of the product term in that block, and a false signal is output for the product term line that is not part of the product term in that block. The circuit outputs the logical product of the same product term lines for the output of each product term memory, and the sum term memory selects the type of IC based on the output of the IC register, and then outputs the logical product from the control unit. At the specified block number of the IC, the output of the AND circuit to the sum term memory outputs a true signal for the sum term line that is part of the sum term in that block. , and a false signal is output for the sum term line that is not part of the sum term in that block, and the OR circuit outputs the same sum term line for the output of each sum term memory. The output register sets and outputs the bit corresponding to the sum term line for which the output result of the logical sum circuit is true. First, input data from the outside is set in the input register, and after resetting all the bits of the output register, the block numbers are output in order, and when the number of blocks stored in the control unit is completed. , a dynamic system characterized by generating a stop signal externally.
P.L.A. DETAILED DESCRIPTION OF THE INVENTION The present invention provides a programmable logic array (PLA).
This relates to dynamic PLA for simulating the logic circuits to be written or manufactured before writing patterns on the chip or manufacturing custom LSIs. Elements used in logic devices are becoming larger year by year, and are increasingly being made into PLA or custom LSI. In such a device,
When a logic circuit error is discovered in a PLA or custom LSI, the damage is much greater than in conventional logic devices. This is because the circuits inside the PLA or custom LSI cannot be modified and must be remanufactured. Therefore, before writing to PLA or manufacturing a custom LSI, it is necessary to thoroughly test the logic circuit that is to be implemented therein. Traditionally, this inspection was performed using software simulation, but as the logical scale increases,
Software simulation is no longer able to perform sufficient tests in a short amount of time. Therefore, in recent years there has been a demand for alternatives to software simulation. An object of the present invention is to realize a simulation of a combinational logic circuit using hardware in response to such demands. Generally, a combinational logic circuit can be represented by a product-sum term. For example, it can be expressed as follows. O1=i _{3 4} + _{1 2 3} +i _{2 3} i ₄ +i ₁ i ₂ i ₃ O2=i _{2 3} i ₄ + ₁ i ₃ + _{1 2 4} O3=+i ₁ i ₄ +i _{2 3} O4= _{1 2 3} + ₁ i _3This combinational logic circuit is
Let it be expressed as shown in the figure. Before describing the structure and operation of Dynamic PLA,
Let me briefly explain its principle. Here, for the sake of simplicity, a dynamic PLA that simulates one combinational logic circuit will be described.
In dynamic PLA, processing is performed in units of blocks. In Figure 1, it is divided into two blocks. Processing is block 1, block 2
It is done in the following order. In each block, the results for the product term line are determined, and then the results for the sum term line are determined. The method for finding it is as follows. Now, suppose that the input data is (i ₁ i ₂ i ₃ i ₄ )=(0010). At this time, the processing for the product term line in block 1 is performed as follows. Block 1 contains 4 for i _{3 4} and _{1 2 3} and i _{2 3} i ₄ and i ₁ i ₂ i ₃ .
There are two product term lines. In order to obtain the values for these four product term lines, the input data is either left as is or divided into several pieces. Here, it is assumed that it is divided into two parts.
That is, assume that it is divided into (i ₁ i ₂ )=(00) and (i ₃ i ₄ )=(10). It can be checked whether the divided input data is a partial product term for the product term of the product term line. That is, it is checked whether the divided input data satisfies the conditions for making the product term true. Now, for the first product term (i _{3 4} ), (i ₁ i ₂ )=(00) is a partial product term, and (i ₃ i ₄ )=(10) is also a partial product term. For the second product term ( _{1 2 3} ), (i ₁ i ₂ ) = (00) is a partial product term, but (i ₃ i ₄ ) = (10)
is not a partial product term. For the third product term (i _{2 3} i ₄ ), both (i ₁ i ₂ )=(00) and (i ₃ i ₄ )=(10) are not partial product terms. (i ₁ i ₂ ) = (00) for the fourth product term (i ₁ i ₂ i ₃ )
is not a partial product term, but (i ₃ i ₄ )=(10) is a partial product term. Next, the logical product of each partial product term is determined for each product term line. That is, for the product term line, if all the partial product terms for the divided input data are true, then true is given, and otherwise, false is given. In this case, it is true for the first product term line, and false for the second, third, and fourth product term lines. Next, processing for the sum term line in block 1 is performed as follows. There are four product term lines, and these four
The product term line can be left as is or divided into several parts. Here, it is assumed that it is divided into two parts. now,
The output of the product term line is (P ₁ P ₂ P ₃ P ₄ ) = (1000), but this changes to (P ₁ P ₂ ) = (10) and (P ₃ P ₄ ) = (00). Suppose it is divided. It is checked whether the divided product term line is a partial sum term for the sum term of the sum term line. That is, the output of the divided product term line is
It is checked whether the conditions for making the sum term true are met. Now, the first sum term (i _{3 4} + _{1 2}
i ₃ +i _{2 3} i ₄ ), (P ₁ P ₂ )=(10) is a partial sum term, and (P ₃ P ₄ )=(00) is not a partial sum term. For the second sum term (i _{2 3} i ₄ ), (P ₁ P ₂ )=(10) and (P ₃ P ₄ )=
Both (00) are not partial sum terms. For the third sum term (none), (P ₁ P ₂ ) = (10) and (P ₃ P ₄ ) = (00)
Of course, is not a partial sum term. Fourth sum term ( _{1 2 3} )
, both (P ₁ P ₂ )=(10) and (P ₃ P ₄ )=(00) are not partial sum terms. Next, for each sum term line,
The logical sum of each partial sum term is determined. That is, for the sum term line, if at least one partial sum term for the output of the divided product term line is true, then true is given, and otherwise, false is given. In this case, it is true for the first summation line, and false for the second, third, and fourth summation lines. The output of the sum term line is sent to an output register. It is assumed that the output register is reset before starting the simulation. For summation lines whose output is true, the corresponding bit in the output register is set. The same processing as block 1 is performed on block 2, and when all of the processing is completed, the contents of the output register are output to the outside as output data. The computation of partial product terms in each block is performed using memory. In each block, for example, a 4-bit simultaneous output memory is used to process four product term lines. In the above example, the four outputs are 1st to 4th for block 1.
It is used to obtain the value of the partial product term for the product term line, and in block 2, the value of the partial product term for the fifth to eighth product term lines. (Alternatively, two or four 2-bit simultaneous output or 1-bit output devices are used in parallel.) Figures 2 and 3 show, as an example, the product for calculating the partial product term of the combinational logic circuit described above. FIG. 3 is a diagram showing the contents of a term memory. Second
In the figure and FIG. 3, when block number 1 is selected, the outputs are P ₁ , P ₂ , P ₃ , and P ₄ ;
When , the outputs are P ₅ , P ₆ , P ₇ , and P ₈ . FIG. 2 shows divided input data (i ₁ i ₂ ), and the block number and divided input data are given as inputs. In the previous example, block number 1,
Give i ₁ =0 and i ₂ =0. As a result, partial product terms 1100 for the first to fourth product term lines are output. FIG. 3 shows divided input data (i ₃ i ₄ ), and the block number and divided input data are similarly given as inputs. In the previous example, block number 2, i ₃ =1, and i ₄ =0 are given. As a result, the partial product terms for the first to fourth product term lines output 1001. The two outputs are ANDed to give a value for the product term line. That is, give 1000 as described above. The computation of the partial sum term in each block is still performed using memory. Since there are four sum term lines, a memory that can output 4 bits simultaneously is used, for example. (Or use two or four 2-bit simultaneous output or 1-bit output in parallel.) Figures 4 and 5 are examples of the summation for calculating the partial sum term of the combinational logic circuit described above. FIG. 3 is a diagram showing the contents of a term memory. FIG. 4 shows the output (P ₁ P ₂ ) of the divided product term line, and the input is the block number and the divided product term line.
In the previous example, block number 1, P ₁ =1, and P ₂ =0 are given. As a result, 1000 partial sum terms for the first to fourth sum term lines are output. FIG. 5 shows the output (P ₃ P ₄ ) of the divided product term line, and the block number and the divided product term line are given as inputs. In the previous example, block number 1, P ₃ = 0, P ₄ =
Give 0. As a result, the partial sum term 0000 for the first to fourth product term lines is output. These two outputs are logically ORed to give a value for the sum term line. That is, give 1000 as described above. So far, we have described the case of simulating one combinational logic circuit, but by giving the numbers of the combinational logic circuits to the product term memory and the sum term memory, it is possible to simulate a plurality of combinational logic circuits. The dynamic PLA of the present invention includes an input register for storing input data from the outside, an IC register for storing a number from the outside, and 1
one or more product term memories, one or more sum term memories, an AND circuit that performs logical AND on the same product term line, and a logical OR that performs logical AND on the same sum term line. A circuit, an output register that sets a corresponding bit when the output result of the sum term line is true, a control unit that controls the input register, the product term memory, the sum term memory, and the output register, and the product term memory and the sum term line. It is composed of a write circuit for writing patterns of product terms and sum terms to memory. Product term memory is IC
The type of IC is selected by the output of the register, and at the location of the block number of that IC specified by the control unit, the output of the input register to the product term memory forms the part of the product term in that block. Outputs the true signal for the product term line that is
Also, a false signal is output for a product term line that does not form part of the product term in that block. The AND circuit outputs the AND of the same product term line for the output of each product term memory. The sum term memory selects the type of IC by the output of the IC register,
Then, at the location of the block number of the IC specified by the control unit, the output of the AND circuit to the sum term memory is true for the sum term line forming the sum term part of that block. Outputs the signal of
Also, a false signal is output for the sum term line that does not form part of the sum term in that block. The OR circuit outputs the OR of the same sum term line for the output of each product term memory. The output register sets the bit corresponding to the sum term line for which the output result of the OR circuit is true. Further, when the control section receives a start signal from the outside, it sets the input data from the outside into the input register, further resets all the bits of the output register, and then outputs the block numbers in order. When the number of blocks stored in the control section is completed, a stop signal is generated externally. Next, the present invention will be explained in detail using the figures.
FIG. 6 is a block diagram of the present invention. In the figure, 1 is a write circuit, 2 is an input register, and 3 is a write circuit.
IC register, 4 is a product term memory group consisting of two product term memories, 5 is an AND circuit, 6 is a sum term memory group consisting of two sum term memories, 7 is an OR circuit, 8
is an output register, and 9 is a control section. The write circuit 1 writes the patterns shown in FIGS. 2 to 5 into the product term memory group 4 and the sum term memory group 6. That is, in the product term memory group 4, the pattern shown in FIG. 2 is applied to the product term memory inputting i ₁ i ₂ .
For the summation memory whose input is i ₃ i ₄ , the third
Write the pattern shown in the figure. In the sum term memory group 6, the pattern shown in Figure 4 is applied to the sum term memory inputting P _1,5 P _2,6, and the pattern shown in Figure 4 is applied to the sum term memory inputting P _3,7 P _4,8 . 5, write the pattern shown in FIG. When the simulation of the combinational logic circuit starts, a START signal is given to the control unit 9, input data is given to the input register 2, and an IC number is given to the IC register 3 from the outside. In response to this, the control section 9 resets the output register 8 and instructs the input register 2 to store the input data and the IC register 3 to store the IC number. The input register 2 receives this, stores the input data, and outputs the contents to the product term memory group 4. Next, the control section 9 outputs block number 1 to the product term memory group 4 and the sum term memory group 6. In the product term memory group 4, the address of each product term memory in the product term memory group 4 is selected based on the IC number, input data, and block number, and the contents thereof are output. The output is sent to the AND circuit 5,
A partial product term is determined for each identical product term line. The result here becomes the input to the summation memory group 6. In the sum term memory group 6, the address of each sum term memory in the sum term memory group 6 is selected based on the IC number, the output of the AND circuit 5, and the block number, and the contents thereof are output. The output is sent to the OR circuit 7,
The sum of partial sum terms is calculated for each same sum term line. The result here becomes an input to the output register 8. The output register 8 sets a bit corresponding to the sum term line for which the output of the OR circuit 7 is true. When this process is completed, the control section 9 outputs block number 2. Then, the same processing as in block number 1 is performed. When the processing for block number 2 is completed, the control unit 9 issues a STOP signal to the outside to notify that the simulation has ended. In Fig. 6, we have explained the dynamic PLA for combinational logic circuits, types, and combinational logic circuits each with 4 input bits, 4 output bits, and 8 product term lines. It can also be realized for combinational logic circuits, input data, output data, and product term lines with arbitrary lengths. The simulation time at that time is determined by how many blocks it is divided into. The output register provides an output for a given input, but if this output does not match the data in the inspection specification, it can be said that there is an error in the logic of the custom LSI. In this case, the custom
Correct the LSI logic circuit, write the resulting bit pattern into the product term memory and sum term memory again, and run the simulation again. Only when no errors are discovered can the custom LSI be manufactured. This greatly reduces the man-hours, costs, and time required to create a correct custom LSI.