JPH0344185A - Playing device for information recording medium - Google Patents

Abstract

PURPOSE:To avoid longitudinal fluctuation of a reproduced pattern due to count correction by adjusting a time axis of a demodulated video signal based on a phase difference on the time axis position represented between a field discrimination signal and a readout field signal. CONSTITUTION:A flip-flop 71a generates a lock detection output when a field discrimination signal is at a low level at the trailing of a readout field and generates a non-lock detection output when the signal is at a high level and supplies the output to a control input of a relay switch 71f and an inverter 71g. The relay switch 71f relays an output of a buffer amplifier 71e to an adder 72 in response to the non-lock detection output to increase an error of a spindle servo loop thereby changing the position of the demodulated video signal on the time axis. When the time axis of the demodulated video signal is adjusted and the lock state is reached, the relay switch 71f is opened to cause the usual spindle servo state, a write enable signal is fed to the memory to allow the write to the memory. Thus, the count correction is not required and fluctuation of the pattern is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an information recording medium playing device for playing an information recording medium such as a video disc or a videotape.

BACKGROUND ART Such an information recording medium performance device is equipped with a memory that stores one field or one frame of a video signal, and selects the writing mode or reading mode to play still images,
There are some that enable a variety of trick plays, such as frame-by-frame forwarding and multi-speed playback that allows you to freely select the playback speed.

FIG. 6 shows an example of a video disc player having such a function, in which a disc 1 on which signals carrying video information are recorded is rotationally driven by a spindle motor 2. As shown in FIG. As the disk 1 rotates, signals recorded on the disk 1 are read by the pickup 3. The RF signal output from the pickup 3 is an FM signal:
The signal is supplied to a demodulation circuit 5 consisting of a JB unit or the like. The video signal is demodulated by this demodulation circuit 5 and supplied to an A/D (analog-to-digital) converter 6 and a synchronization separation circuit 7. In the synchronization separation circuit 7, the horizontal synchronization signal and the vertical synchronization signal V in the video signal are separated. The horizontal synchronization signal is supplied to a PLL circuit 8 that generates a write clock, a phase comparison circuit 9 that controls the rotation of the spindle motor 2, and a memory controller 50. The vertical synchronization signal V is supplied to the memory controller 50.

In the phase comparison circuit 9, the phase of the demodulated horizontal synchronization signal H is compared with the reference horizontal synchronization signal H supplied from the memory controller 50, and a level signal is formed according to the phase difference between the two signals.

This level signal is supplied to the spindle motor 2 via the servo amplifier 10 as a spindle error signal, and the rotational speed of the disk 1 is controlled.

The PLL circuit 8 is constituted by a phase-locked loop consisting of, for example, a phase comparator circuit, a vCO, and a frequency divider, and is phase-locked to a horizontal synchronization signal. is generated and sent to the A/D converter 6 and IH line memory 1.
Supply to 1.

The A/D converter 6 samples the video signal in accordance with the timing signal, converts the obtained sample value into digital data, and supplies the digital data to the line memory 11.

The line memory 11 has a capacity G that can store data for one line, for example, and writes the output data of the A/D converter in accordance with the timing signal 4fsc that follows the time axis fluctuation of the video signal. The stored data is output in response to a read signal with a constant frequency of 4 fsc supplied from the controller 50. Therefore, the line memory 20 makes fine adjustments to the time axis fluctuations and absorbs jitter.

Data read from line memory 11 is supplied to field memories 12 and 13. The field memories 12 and 13 each have a storage capacity equivalent to one field, and write and read data in response to various control signals supplied from the memory controller 50. By using memory, not only CAV disks but also C
Trick plays are also possible when playing LV discs.

Memory usage modes include a field memory mode using only the memory 12 and a frame memory mode using the memories 12 and 13. For example, for still image playback, a frame memory mode is used to store one frame of a video signal and read it out to prevent deterioration in playback image quality.

The data read from the field memory 12 or 13 is converted into an analog signal by a D/A (digital◆analog) converter 14, and a synchronization signal supplied from the memory controller 50 is superimposed in an adder 15 to create a composite video signal. The signal is reproduced and supplied to a television receiver (not shown).

The memory controller 50 includes, for example, a write signal generation circuit 51 and a write address counter 5, as shown in FIG.
2, a latch 53, a read signal generation circuit 54, a read address counter 55, a count correction circuit 56, and the like.

The write signal generation circuit 51 has a field detection section for performing memory address control for storing video signals to be stored field by field or frame by frame. The field detection section determines whether the video signal supplied to the memory is an odd field or an even field based on the horizontal synchronization signal and vertical synchronization signal (2) separated from the demodulated video signal, and determines whether the video signal supplied to the memory is an odd field or an even field, as shown in FIG. A field discrimination signal Fw which is at a high level in an odd field and a low level in an even field is generated and is supplied to a write address counter 52 and a latch 53. In addition, the write signal generation circuit 51
divides the reference signal 4fsc, which has a frequency four times that of the color subcarrier from the crystal oscillator built into the readout signal generation circuit 52, to generate an H signal with a horizontal period, and responds to a write command from the outside. Then, the 4 fsc signal and the H signal are supplied to the write address counter 52.

The write address counter 52 consists of an odd field address counter and an even field address counter.

The odd field address counter is the 1H of the video signal.
-263H Specifies the storage address of each pixel of the odd field image formed by 263H. The even field address counter specifies the storage address of the pixel of the even field image formed by 264H to 525H of the video signal.

In the frame memory mode, the cumulative value of the odd field address counter is supplied to the memory 12, and the cumulative value of the even field counter is supplied to the memory 13.

The odd field address counter starts integrating the H signal and the 4fSC signal in response to the arrival of the odd field start position Wl of the field discrimination signal FW shown in FIG. 8(A), and calculates the integrated value of both the H signal and the 4fsc signal. specifies the two-dimensional address position on the memory 12 where the pixel data is to be stored. The even field address counter starts integrating the H signal and the 4fsc signal in response to the arrival of the even field start position W2 of the field discrimination signal FW shown in FIG. 7(A), and calculates the integrated value of both the H signal and the 4fsc signal. specifies the two-dimensional address position on the memory 13 where the pixel data is to be stored.

In this way, in the frame memory mode, 263H of the video signal (first field) is stored in the memory 12.
262H of video signals (second field) are stored in the memory 13.

On the other hand, in the field memory mode, the odd field address counter and memory 12 are exclusively used.

At this time, the odd field address counter restarts the integration of the H signal and the 4fSc signal in response to the arrival of the odd field start position Wl and the even field start position W2 of the field discrimination signal FW.
A two-dimensional address position on the memory where pixel data is to be stored is specified by both integrated values of the signals.

In this way, in the field memory mode, 263H and 262H of video signals are alternately stored in the memory 12.

The read signal generation circuit 54 generates a signal from a built-in crystal oscillator.
The fsc signal is frequency-divided to generate an H signal with a horizontal period, a V signal with a vertical period, an equivalent pulse, a read field signal FR, etc. Then, the H signal and 4fsc signal for specifying the read address are sent to the read address counter 55, and the synchronization signal consisting of the H signal, ■ signal, and equivalent pulses for generating a new composite video signal is sent to the adder 15.
Phase comparator circuit 9 converts H signal for spindle servo
Then, a read field signal FR representing odd and even fields of a composite video signal newly generated from the video signal read from the memory is counted by a correction circuit 56.
and the read address counter 55. The read field signal is a signal that has a high level when the composite video signal to be formed at the output end of the adder 15 is an odd field, and a low level when it is an even field, as shown in FIG. 8(B). .

The read address counter 55 consists of an odd field address counter and an even field address counter, and operates in the same manner as the write address counter 52.

That is, in the frame memory mode, the integrated value of the odd field address counter is supplied to the memory 12, and the integrated value of fXi of the even field counter 13 is supplied to the memory 13.

The odd field address counter starts integrating the H signal and the 4fsc signal in response to the arrival of the odd field start position R1 of the read field signal FR shown in FIG. 8(B), and calculates the integrated value of both the H signal and the 4fsc signal. specifies the two-dimensional address position of the pixel data to be read from the memory. The even field counter is shown in Figure 8 (
In response to the arrival of the even field start position R2 of the read field signal FR shown in B), integration of the H signal and 4fsC signal is started, and the pixel data to be read out from the memory is Specify a two-dimensional address position.

Thus, in frame memory mode, memory 12
263H of the video signal are read from the memory 13, and 262H of the video signal are read from the memory 13.

In field memory mode, the odd field address counter and memory 12 are used exclusively. At this time, the odd field address counter receives an H signal and a 4 field address counter in response to the arrival of the odd field start position R1 and the even field start position R2 of the read field signal FR.
The integration of the fsc signal is resumed, and 2 of the pixel data to be read from the memory is
Specifies a dimensional address location.

In this way, in the field memory mode, 263H and 262H of video signals are alternately read out from the memory 12.

The count correction circuit 56 compares the current read field signal FR with the contents of the latch circuit 53 that holds whether the last field written to the memory is an odd field or an even field. It is determined whether the field types (odd and even fields) of the composite video signal to be formed at the output end of the memory match the field types of the video signal read out from the memory. When the types of both fields match, the original composite video signal is correctly formed, so no correction is made to the read address counter 55. If the types of both fields do not match, the integrated value of the read address counter is increased or decreased by an amount equivalent to IH.

This is done by, for example, inserting an even field video signal read from memory into an odd field of a composite video signal to be newly generated to form a composite video signal, which is then supplied to a television receiver to display the image. This is because when the image is played back, it is played back as an image with the frame order shifted. To prevent this, if the types of both fields do not match, read address counter 5
The integrated value of 5 is increased or decreased by the IH value to properly arrange the reproduction line order on the television screen.

In other words, as shown in FIG. 9(A), a general television receiver forms one frame (one screen) with odd fields shown by solid lines and even fields shown by broken lines. If the field of the generated video signal and the field of the generated composite signal do not match, the lines to be displayed of the video signal will be shifted as shown in FIG. 6(B), resulting in odd field lines A and B.

C and even field lines A', B'C' are not displayed in the correct order.

Therefore, in such a case, the integrated value of the read counter 55 is corrected to correspond to IH so that each line is displayed in the correct order as shown in FIG. 9(C).

In such a configuration, when a still image is to be reproduced, the field determination signal Wl is output in the presence of a write command.

After writing the first field of the video signal to the memory 12 and the second field to the memory 13 in response to the arrival of W2, writing to the memory is prohibited by the WE double signal described later, and the read field is written in the presence of a read command. One frame of the video signal is repeatedly read out from the memories 12 and 13 in response to the arrival of the signals R1 and R2.

When performing multi-speed playback, in addition to the above-mentioned still image playback operation, the pickup is made to perform track jumps of information reading points at predetermined intervals, reads one field of a new video signal, and writes it to the memory. The contents of memory are updated sequentially. In this way, the composite video signal reproduced from the memory has the same content as the original video signal played frame by frame, thereby realizing image reproduction at the desired performance speed.

By the way, if the field of the video signal written in the memory and the field of the newly generated composite video signal do not match, the count correction circuit 56 described above operates to adjust the playback order of lines on the TV screen. However, when the count correction circuit 56 operates, the reproduced image moves vertically by one line as shown in FIG. 9(C).

Therefore, if field mismatches occur frequently when performing multi-speed playback, etc., the reproduced image will fluctuate in the vertical direction.
This may be difficult for TV viewers to view.

The invention! Summary [Object of the Invention] Therefore, an object of the present invention is to provide an information recording medium performance device that can suppress fluctuations in a reproduced image that may occur when reading image data from a memory and generating a composite video signal.

[Structure of the Invention] In order to achieve the above object, the present invention includes a driving means for driving an information recording medium on which a recording signal carrying video information is recorded;
demodulating means for reading the recorded signal from the information recording medium and demodulating the video signal; synchronizing signal separating means for separating a synchronizing signal from the demodulated video signal; and a phase difference between the synchronizing signal and a reference signal of a predetermined frequency. drive control means for supplying a signal to the drive means; signal generation means for generating a write timing signal based on the synchronization signal; and storing the demodulated video signal in a memory in synchronization with the write timing signal. In the information recording medium performance apparatus, the information recording medium performance apparatus includes a writing means for generating a readout timing signal, a readout timing signal generation means for generating a readout timing signal, and a readout means for reading out the demodulated video signal written in the memory based on the readout timing signal. ll of the odd and even fields of the demodulated video signal to be written to memory! field discriminating means for generating a field discriminating signal representing a position on the time axis of the odd and even fields of the demodulated video signal to be read from the memory based on the read timing signal; read field signal generating means for generating a signal; and a) time axis adjustment for adjusting the time axis of the demodulated video signal based on the phase difference between the positions on the time axis of the field discrimination signal and the read field signal. The configuration includes means.

[Operation of the Invention] According to the information recording medium performance device configured as described above, the write field of the demodulated video signal written in the memory is odd-even, and the read field of the video signal to be read from the memory and generated is odd-even. If they do not match, the time and peak of the demodulated video signal are adjusted so that the write field and the read field are even or odd.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIG. Components in the device shown in FIG. 1 that correspond to those in the device shown in FIG. 6 are designated by the same reference numerals, and explanations of these portions will be omitted.

In this embodiment, a phase comparison circuit 71, an adder 72, and a lock detector 73 are added.

In FIG. 1, a field discrimination signal FW and a read field signal FR are supplied to a phase comparator 71 from a memory controller 50a. The phase comparator 71 compares, for example, the rising position or falling position of the field discrimination signal FW with the rising position or falling position of the read field signal FR, and adds a level state phase difference signal corresponding to the time difference between them. is supplied to one input terminal of the device 72. The other input end and output end of the adder 72 are connected to the output end of the phase comparison circuit 9 and the input end of the servo amplifier 10, respectively.
superimposes the phase difference signal on the phase difference output of the phase comparison circuit 9. The servo amplifier 10 accelerates the spindle motor 2 according to the phase difference signal and adjusts the time axis of the demodulated video signal. When the comparison result of the phase difference is a predetermined value within one field, the phase comparison circuit 71 ideally detects the first field of the field discrimination signal FW as shown in FIGS. 8(A) and 8(B). When the read field signal FR rises at approximately 1/2 field position, the level of the phase difference signal is set to O. When the level of the state phase difference signal reaches approximately O, the lock detector 73 detects this and generates a high-level lock detection signal. This lock detection signal is supplied to the memory controller 50a.

FIG. 2 shows an example of the configuration of the memory controller 50a, and parts corresponding to those of the memory controller 50 shown in FIG. 7 are given the same reference numerals, and a description of these parts will be omitted.

The memory controller 50a has an AND gate 74, but does not have a latch 53 or a count correction circuit 56.

The other configurations are similar to the memory controller 50.

The lock detection signal is supplied to one input terminal of the AND gate 74. The write enable signal WE is supplied from the write signal generation circuit 51 to the other input terminal of the AND gate 74, and the output of this AND gate is supplied to the memories 12 and 13. Therefore, the write enable signal WE that allows writing to the memory is supplied to each memory after lock detection, so the video signal is not written to the memory until the write field and read field match. It is done rarely. The other configuration of this embodiment is similar to the device shown in FIG.

Figure 3 (A) shows a case where the time axis of the field ill signal is ahead of the time axis of the read field signal. In such a case, the spindle motor is decelerated to reduce the phase difference between the two signals. The accuracy is adjusted so that the value is greater than or equal to 1H and less than I■ (field). This is because if the phase difference is within this range, there will be no practical problem.

Furthermore, FIG. 3(B) shows a case where the time axis of the field discrimination signal lags behind the time axis of the read field signal, and in such a case, the spindle motor is accelerated to change the position of both signals. J8u so that the phase difference is greater than or equal to IH and less than 1V (field).

FIG. 4 shows a configuration example of the phase comparison circuit 71 and the lock detection circuit 73. The operation of this configuration example will be explained with reference to FIG.

In FIG. 4, a field discrimination signal as shown in FIG. 5(A) is supplied to the D input terminal of the D flip-flop 71a and the clock input terminal of the D flip-flop 71c. Fifth
The read field signal as shown in FIG. 3B is supplied to the clock input terminal of the D flip-flop 71a and the tri-input terminal of the monostable multi-channel 71b. The monostable multi 71b responds to the falling edge of the read field signal as shown in FIG.
) generates a high-level pulse for the duration of D
It is supplied to the D input terminal of the flip-flop 71c. The D flip-flop 71c makes the Q output high level when the fall of the field discrimination signal is within (1/2) V from the fall of the read field signal as shown in FIG. 5(D).

This Q output is supplied to the comparison input terminal of the level comparator 71d. A predetermined voltage is applied to the reference input terminal of the level comparator 71d, and when the Q output is at a high level, a positive voltage is generated to drive the subsequent spindle motor 2.
When the Q output is at a low level, a negative voltage is generated to decelerate the spindle motor 2. The voltage output of the level comparator 71d as shown in FIG. 5(E) is supplied to the adder 72 suppressed in the spindle servo loop via the buffer amplifier 71e and the relay switch 71f. Circuits 71b to 71f correspond to phase comparison circuit 71.

The flip-flop 71a plays the role of a lock detector 73, and outputs a lock detection output when the field discrimination signal is at a low level at the falling edge of the read field as shown in FIG. A lock detection output is generated and supplied to the control input of the relay switch 71f and the inverter 71g. The relay switch 71f relays the output of the buffer amplifier 71e to the adder 72 in response to the non-lock detection output, increases the error in the spindle servo loop, and changes the position of the demodulated video signal on the time axis. The output of inverter 71g is supplied to AND gate 74, which prevents the WE multiplication signal from being supplied to the memory in the unlocked state.

When the inter-axis axis of the demodulated video signal is adjusted to the locked state, the relay switch 71f is opened to enter the normal spindle servo state, the WE double signal is supplied to the memory, and writing to the memory is permitted.

In this way, the feed of the video signal written into the memory in the frame memory mode and the field memory mode matches the field of the video signal read out from the memory, making it unnecessary to correct the read address count as in conventional devices. , the screen shake caused by the count correction is eliminated.

Although the description has been made regarding a device that plays a disc on which a video signal is recorded, the present invention is also applicable to a VTR or the like that plays a tape on which a video signal is recorded.

As described in detail, in the information recording medium performance device of the present invention, the video signal demodulated from the information recording medium is temporarily stored in the memory, and when performing various trick plays etc., the video signal is stored in the memory. The time axis of the input video signal is adjusted so that the types of fields written into the memory (odd fields and even fields) match the odd-even fields of the video signal read out from the memory and generated. There is no need to correct the reading count as in the conventional case, and there is no vertical shaking of the television playback screen caused by the count correction, which is preferable.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration example of the memory controller 50a shown in FIG. 1, and FIGS. 3(A) and (B) are FIG. 4, a diagram for explaining the operation of the embodiment, shows the phase comparator circuit 7.
1 and a block diagram showing a configuration example of the lock detector 73, FIG. 5 is a diagram for explaining the operation of each circuit shown in FIG. 4, FIG. 6 is a block diagram showing a conventional example, and FIG. 6 is a block diagram showing a configuration example of the memory controller 50 shown in FIG. 6, FIG. 8 is a diagram for explaining a conventional example, and FIG. 9 is a reproduced image 1 in a television receiver. ! FIG. 2 is a diagram for explaining an example. Explanation of symbols of main parts 9.71... Phase comparator circuit 72... Adder 73... Lock detector

Claims (3)

[Claims] (1) Driving means for driving an information recording medium on which a recording signal carrying video information is recorded; demodulation means for reading the recording signal from the information recording medium and demodulating the video signal; and a synchronization signal from the demodulated video signal. a synchronization signal separating means for separating the synchronization signal and a reference signal of a predetermined frequency; a drive control means for supplying the drive means with a phase difference signal between the synchronization signal and a reference signal of a predetermined frequency; and a signal generation means for generating a write timing signal based on the synchronization signal. means for storing the demodulated video signal in the memory in synchronization with the write timing signal; read timing signal generating means for generating a read timing signal; writing in the memory based on the read timing signal; an information recording medium performance device for reading out a demodulated video signal, the information recording medium performance device comprising: reading means for reading out a demodulated video signal written in the memory; means, read field signal generating means for generating read field signals representing positions on the time axis of odd and even fields of the demodulated video signal to be read from the memory based on the read timing signal; the field discrimination signal; An information recording medium performance device characterized by comprising a time axis adjustment means for adjusting the time axis of the demodulated video signal based on a phase difference between the positions on the time axis represented by the read field signals. (2) The field discrimination signal has a level corresponding to the existence period of the odd and even fields, and the read field signal has a level corresponding to the period during which the odd and even fields are read, and the time axis The adjusting means includes a phase difference detection circuit that detects a phase difference between the field discrimination signal and the read field signal to obtain a difference signal, and an addition circuit that superimposes the difference signal on the phase difference signal. The information recording medium performance device according to claim 1. (3) The phase difference detection circuit sets the level of the phase difference signal to zero when the phase difference is a predetermined value within one field, and the memory stores one field of the demodulated video signal. The information recording medium performance device according to claim 1.