JPH0340959B2 - - Google Patents
Info
- Publication number
- JPH0340959B2 JPH0340959B2 JP23796384A JP23796384A JPH0340959B2 JP H0340959 B2 JPH0340959 B2 JP H0340959B2 JP 23796384 A JP23796384 A JP 23796384A JP 23796384 A JP23796384 A JP 23796384A JP H0340959 B2 JPH0340959 B2 JP H0340959B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- impurity concentration
- etching
- layer
- protective film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005530 etching Methods 0.000 claims description 55
- 239000012535 impurity Substances 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 44
- 230000001681 protective effect Effects 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 24
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 17
- 229910052804 chromium Inorganic materials 0.000 claims description 16
- 239000011651 chromium Substances 0.000 claims description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 14
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 10
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 229910001020 Au alloy Inorganic materials 0.000 claims description 4
- 239000003353 gold alloy Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 239000012808 vapor phase Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 23
- 229910052710 silicon Inorganic materials 0.000 description 23
- 239000010703 silicon Substances 0.000 description 23
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 10
- 239000010931 gold Substances 0.000 description 10
- 229910052737 gold Inorganic materials 0.000 description 10
- 235000012431 wafers Nutrition 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 230000035945 sensitivity Effects 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- XWROUVVQGRRRMF-UHFFFAOYSA-N F.O[N+]([O-])=O Chemical compound F.O[N+]([O-])=O XWROUVVQGRRRMF-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910000623 nickel–chromium alloy Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 230000002463 transducing effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H01L29/84—
Landscapes
- Measuring Fluid Pressure (AREA)
- Pressure Sensors (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は半導体圧力センサの感圧ダイヤフラム
を凹状に形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a method for forming a pressure-sensitive diaphragm of a semiconductor pressure sensor into a concave shape.
圧力センサは各産業分野で広く使用されている
基本的なセンサの一つであり、最近は半導体IC
技術を応用した拡散形半導体圧力センサが盛に用
いられるようになつている。
Pressure sensors are one of the basic sensors widely used in various industrial fields, and recently semiconductor ICs
Diffusion-type semiconductor pressure sensors based on this technology are now being widely used.
半導体圧力センサはシリコンなどの半導体にひ
ずみを加えると金属に比べて100倍程度の大きな
抵抗変化を生ずることを利用して、圧力を受けて
ひずみを生ずる起わい体そのものをシリコン単結
晶板からつくり、これに不純物を拡散し、ストレ
ンゲージを形成したものであり、ストレンゲージ
抵抗の形成されたシリコン単結晶板の裏面を凹形
にくり抜いて薄くなつた部分がダイヤフラムとな
るので、このダイヤフラムとストレンゲージが完
全に一体となつて圧力−ひずみ変換が行なわれ
る。すなわち圧力が印加されるとダイヤフラムが
変形してゲージ抵抗にひずみが発生し、このため
ゲージにはピエゾ抵抗効果による大きな抵抗変化
が起こり、圧力に比例したブリツジ出力が得られ
るのである。 Semiconductor pressure sensors take advantage of the fact that applying strain to a semiconductor such as silicon causes a change in resistance that is approximately 100 times greater than that of a metal.The semiconductor pressure sensor uses a silicon single crystal plate to create the flexible body that generates strain when subjected to pressure. A strain gauge is formed by diffusing impurities into this, and the back surface of the silicon single crystal plate on which the strain gauge resistor is formed is hollowed out in a concave shape, and the thinned part becomes the diaphragm. The gauges are fully integrated to perform pressure-strain conversion. That is, when pressure is applied, the diaphragm deforms and strain occurs in the gauge resistance, which causes a large resistance change in the gauge due to the piezoresistive effect, resulting in a bridge output proportional to the pressure.
このような半導体圧力センサの起わい部の形成
方法は一般に次のようにして行なわれる。まず第
２図に断面図で示したようにシリコン基板１の一
方の表面に基板１と逆導電型のひずみゲージ２を
形成し、この面と反対側の基板１表面の起わい部
となる部分を除く個所に例えばクロムの第１の保
護膜３と金の第２の保護膜４との積層保護膜を設
け、この積層保護膜をマスクとして硝酸−弗酸の
混合エツチング液を用いてシリコン基板１をエツ
チングする。第３図はそのエツチングの模様を示
したものであり、エツチング液５を入れた容器６
の中に上記のようにしたシリコン基板１を浸積エ
ツチングすることにより起わい部７を形成するこ
とができる。ただし、このエツチング過程は１枚
のシリコンウエハから多数個の圧力変換素子が得
られるように行なわれるが、第２図、第３図では
説明の便宜上ただ１個のチツプとして表わしてあ
る。 A method for forming the raised portion of such a semiconductor pressure sensor is generally performed as follows. First, as shown in the cross-sectional view in FIG. 2, a strain gauge 2 of a conductivity type opposite to that of the substrate 1 is formed on one surface of the silicon substrate 1, and a portion of the surface of the substrate 1 opposite to this surface becomes the ridge. A laminated protective film of, for example, a first protective film 3 of chromium and a second protective film 4 of gold is provided in the areas other than the silicon substrate. Etch 1. Figure 3 shows the etching pattern, and shows the container 6 containing the etching solution 5.
The raised portion 7 can be formed by immersion etching the silicon substrate 1 as described above. Although this etching process is carried out so that a large number of pressure transducing elements can be obtained from one silicon wafer, they are shown as only one chip in FIGS. 2 and 3 for convenience of explanation.
しかしながら、このエツチング方法によれば、
シリコンウエハの中央部分と周辺部分とではエツ
チング速度が異なるため、起わい部７に関しても
中央部分と周辺部分との板厚が異なることから圧
力変換素子と感度がばらつき、また複数枚のシリ
コンウエハを同時にエツチング処理する際には、
ウエハ間のばらつきも発生するので全体として素
子の感度のばらつきを小さく抑えることは困難で
ある。 However, according to this etching method,
Since the etching speed is different between the central part and the peripheral part of the silicon wafer, the thickness of the raised part 7 is also different between the central part and the peripheral part, so the sensitivity of the pressure transducer varies, and it is difficult to process multiple silicon wafers. When etching at the same time,
Since variations also occur between wafers, it is difficult to suppress variations in sensitivity of the elements as a whole.
一方上記とは異なるエツチング方法として第４
図のごとく電気化学的にエツチングする方法も知
られている。第４図はこの方法を説明するための
概念図であり、第２図、第３図と共通部分を同一
符号で表わしてある。第４図においてまず被エツ
チング素子として不純物を高濃度に添加したシリ
コン基板１ａに低不純物濃度層８をエピタキシア
ル生長させ、この低不純物濃度層８にひずみゲー
ジ２を設け、次いでひずみゲージ２を設けたのと
反対側のシリコン基板１ａの面で所定の領域に例
えばクロムの第１層保護膜３と金の第２層保護膜
４からなる２層のエツチングマスクを被着したも
のが用いられる。クロムは金と下地シリコン基板
１ａとの密着性を増す役割をもつ。このものを容
器６内の硝酸−弗酸混合液５中において直流電源
９に接続したシリコン基板１ａの所定部分をエツ
チングし、不純物濃度境界面１１まで進行したと
きエツチングを停止させるストツプエツチングを
行うことにより、所望の凹部を形成し、起わい部
として均一な厚さを得ようとするものである。な
お第４図においてシリコン基板１ａのエツチング
により除去される部分を点線で表わしてある。 On the other hand, there is a fourth etching method different from the above.
A method of electrochemical etching as shown in the figure is also known. FIG. 4 is a conceptual diagram for explaining this method, and parts common to those in FIGS. 2 and 3 are indicated by the same reference numerals. In FIG. 4, first, a low impurity concentration layer 8 is epitaxially grown on a silicon substrate 1a doped with impurities at a high concentration as an element to be etched, a strain gauge 2 is provided on this low impurity concentration layer 8, and then a strain gauge 2 is provided. A two-layer etching mask consisting of, for example, a first protective film 3 of chromium and a second protective film 4 of gold is used in a predetermined region on the opposite side of the silicon substrate 1a. Chromium has the role of increasing the adhesion between gold and the underlying silicon substrate 1a. A predetermined portion of the silicon substrate 1a connected to the DC power source 9 is etched in the nitric acid-hydrofluoric acid mixture 5 in the container 6, and stop etching is performed to stop the etching when the etching reaches the impurity concentration interface 11. By doing so, it is intended to form a desired concave portion and obtain a uniform thickness as a raised portion. In FIG. 4, the portion of the silicon substrate 1a that is removed by etching is indicated by a dotted line.
しかし、この電気化学的エツチング方法は凹部
形成に際して、シリコン基板１ａとこれに対向配
置される白金陰電極１０との間に直流電圧が印加
され第１層クロム３−第２層金４の積層保護膜が
正の電極となるため、第１層クロム膜３が溶解し
てシリコン基板１ａから剥離し、マスク効果を発
揮することができなくなり、その結果所望の凹部
以外の領域までエツチングされてしまうという欠
点がある。 However, in this electrochemical etching method, when forming the recesses, a DC voltage is applied between the silicon substrate 1a and the platinum cathode 10 placed opposite thereto, thereby protecting the laminated layers of the first layer chromium 3 and the second layer gold 4. Since the film becomes a positive electrode, the first layer chromium film 3 dissolves and peels off from the silicon substrate 1a, making it impossible to exert a masking effect, and as a result, areas other than the desired recesses are etched. There are drawbacks.
これに対してエツチングマスクとしてクロム−
金からなる金属積層膜の代りに酸化膜（SiO2）
１層のみとする方法もあるが、酸化膜の厚さ約
1μｍのときエツチングに対するマスク効果は１
時間程度しか保つことができず、電気化学的なス
トツプエツチング法により感圧ダイヤフラムが必
要とする数百μｍの凹部を形成するためには、２
時間以上かかるので酸化膜をマスクとして用いる
ことは適切な手段とは言えない。 In contrast, chrome is used as an etching mask.
Oxide film (SiO 2 ) instead of metal laminated film made of gold
There is also a method of using only one layer, but the thickness of the oxide film is approx.
At 1μm, the mask effect against etching is 1
In order to form a recess of several hundred micrometers required for a pressure-sensitive diaphragm using an electrochemical stop etching method, it is necessary to
Since it takes a long time, using an oxide film as a mask is not an appropriate method.
なお、このような電気化学的なストツプエツチ
ング法は、高不純物濃度の半導体基板とこの基板
に設けられた低不純物濃度層とではエツチング速
度が著しく異なることを利用したものであり、不
純物濃度とエツチング速度の関係を第５図の線図
に示したが、第５図からわかるように例えば不純
物濃度が1018／c.c.の領域と1015／c.c.以下の領域で
はエツチング速度に１桁以上の差があり、したが
つて低不純物濃度層がエツチングのストツパとな
つて均一な板厚の起わい部が得られるのである。 Note that this electrochemical stop etching method takes advantage of the fact that the etching rate is significantly different between a semiconductor substrate with a high impurity concentration and a layer with a low impurity concentration provided on this substrate. The relationship between etching rates is shown in the diagram in Figure 5. As can be seen from Figure 5, for example, there is a difference of more than one digit in etching rate between a region where the impurity concentration is 10 18 /cc and a region where it is less than 10 15 /cc. Therefore, the low impurity concentration layer acts as an etching stopper, and a ridge portion with a uniform plate thickness is obtained.
以上のように、半導体基板の不純物濃度差を利
用した電気化学的なストツプエツチング法は圧力
変換素子起わい部を形成するために有効な方法で
あるが凹部を形成する際の適切な材料が見出され
ていない。 As mentioned above, the electrochemical stop etching method that utilizes the difference in impurity concentration in the semiconductor substrate is an effective method for forming the raised portion of the pressure transducer element, but it is difficult to use the appropriate material for forming the recessed portion. Not discovered.
本発明は上述の点に鑑みてなされたものであ
り、その目的は半導体圧力変換素子起わい部の凹
形状を形成するために、電気化学的なストツプエ
ツチングを行なうに当り、エツチングマスクの密
着性がよく、凹部形成中にマスクが基板から剥離
することなく、起わい部が均一な厚さを有し、圧
力感度のばらつきの小さい圧力変換素子を得るこ
とができる起わい部の形成方法を提供することに
ある。
The present invention has been made in view of the above points, and its purpose is to improve the adhesion of an etching mask when performing electrochemical stop etching to form a concave shape at the protrusion of a semiconductor pressure transducer element. The present invention provides a method for forming ridges that can obtain a pressure transducer element with good properties, a mask that does not peel off from the substrate during the formation of the depressions, a ridge that has a uniform thickness, and a small variation in pressure sensitivity. It is about providing.
本発明は不純物を高濃度に添加した単結晶シリ
コン基板の片面に低不純物濃度層を気相生長さ
せ、低不純物濃度層にひずみゲージを形成し、高
不純物濃度の基板のひずみゲージ形成面と反対側
の面から電気化学的にストツプエツチングして凹
部を形成するときに、高不純物濃度基板上に設け
るエツチングマスクとして第１層酸化膜（SiO2）
と第２層のニツケルおよびクロムを含有した全膜
とからなる二層マスクを用いることにより、マス
ク自体の溶解や基板からの剥離などをなくし、基
板の不純物濃度境界面でエツチングを停止し、均
一な厚さを有する起わい部が得られるようにした
ものである。
In the present invention, a low impurity concentration layer is grown in a vapor phase on one side of a single crystal silicon substrate doped with a high impurity concentration, a strain gauge is formed in the low impurity concentration layer, and the strain gauge is formed on the opposite side of the substrate with a high impurity concentration. A first layer oxide film (SiO 2 ) is used as an etching mask provided on a high impurity concentration substrate when electrochemical stop etching is performed to form a recess from the side surface.
By using a two-layer mask consisting of a second layer of nickel and a full film containing chromium, the mask itself is prevented from dissolving or peeling off from the substrate, and etching is stopped at the impurity concentration interface of the substrate, resulting in uniform etching. In this embodiment, a raised portion having a certain thickness can be obtained.
以下本発明を実施例に基づき説明する。 The present invention will be explained below based on examples.
再び第４図を参照して本発明を説明するが、本
発明が従来の方法と異なる点は、従来エツチング
マスクとしてシリコン基板１ａに近い方から例え
ばクロムの第１層保護膜３とこの上に金の第２層
保護膜４を被着していたのに対し、本発明では第
１層保護膜３に酸化膜（SiO2）、第２層保護膜４
にニツケルとクロムを含む金膜を用いて二層積層
膜としていることである。 The present invention will be explained again with reference to FIG. 4. The difference between the present invention and the conventional method is that a conventional etching mask is used in which a first layer protective film 3 of chromium, for example, and a first layer protective film 3 of chromium are etched thereon from the side closer to the silicon substrate 1a. Whereas the second layer protective film 4 of gold was deposited, in the present invention, an oxide film (SiO 2 ) is applied to the first layer protective film 3 and a second layer protective film 4 is deposited.
A two-layer laminated film is formed using a gold film containing nickel and chromium.
本発明を第４図により素子構成から述べると、
まず有効なピエゾ抵抗効果が得られる結晶方位を
有し、例えば1019／c.c.以上の砒素もしくは1018／
c.c.以上のアンチモンを含むN+型高濃度結晶シリ
コン基板１ａの片面に最終的に形成される起わい
部の板厚ｔだけ1015／c.c.以下の燐をドーピングし
たｎ型低不純物濃度層８をエピタキシアル生長さ
せ、この低不純物濃度層８にひずみゲージ２を形
成し、次いでひずみゲージ２とは反対側のシリコ
ン基板１ａの所定の領域に第１層保護膜３として
熱酸化などにより電気的絶縁性を有する酸化膜を
設け、この上にニツケルクロム合金と金をソース
とする蒸着を行い第２層保護膜４としてニツケル
およびクロムを総量で14〜30重量％含有する金合
金膜を被着させたものとする。金にニツケルとク
ロムを含有させることにより耐エツチング性を向
上させることができる。このとき膜厚は第１層３
の酸化膜は0.2〜1.0μｍであり、第２層４のニツ
ケルおよびクロムを含む金合金の膜厚は0.2〜
0.5μｍである。 The present invention will be described from the element configuration with reference to FIG.
First, it has a crystal orientation that provides an effective piezoresistance effect, such as arsenic of 10 19 /cc or more or 10 18 /cc or more.
An n-type low impurity concentration layer 8 doped with phosphorus of 10 15 /cc or less is formed on one side of the N + type high-concentration crystalline silicon substrate 1a containing antimony of cc or more by the thickness t of the raised portion finally formed. A strain gauge 2 is formed in this low impurity concentration layer 8 by epitaxial growth, and then a first layer protective film 3 is formed on a predetermined region of the silicon substrate 1a on the opposite side of the strain gauge 2 for electrical insulation by thermal oxidation or the like. A gold alloy film containing a total of 14 to 30% by weight of nickel and chromium is deposited as the second layer protective film 4 by vapor deposition using a nickel-chromium alloy and gold as sources. shall be Etching resistance can be improved by incorporating nickel and chromium into gold. At this time, the film thickness is the first layer 3
The thickness of the oxide film of the second layer 4 is 0.2 to 1.0 μm, and the thickness of the gold alloy containing nickel and chromium of the second layer 4 is 0.2 to 1.0 μm.
It is 0.5 μm.
このように準備のできたシリコン基板１ａを弗
酸と純水を１：９の比率に混合したエツチング液
５の入つた容器６に沈め、エツチング液中で直流
電源９により高不純物濃度基板１ａを陽極、白金
１０を陰極として数Ｖの直流電圧を印加し、基板
１ａの所定領域を除去するが、このときエツチン
グの停止は、第５図の不純物濃度とエツチング速
度の関係線図からわかるように不純物濃度境界面
で行なわれるから、はじめに設定したｔの厚さを
もつ低不純物濃度層８が起わい部の厚さとして残
るので高い精度が確保される。またこのエツチン
グ過程においては高不純物濃度基板１ａと第２層
保護膜４の金属膜とは第１層保護膜３の酸化膜に
より電気的に絶縁された状態にあるから、例えば
２時間以上の長いエツチング時間に対しても高不
純物濃度基板１ａの所望の凹部のみがエツチング
され、その他の部分は完全にエツチングから保護
することができる。 The silicon substrate 1a thus prepared is immersed in a container 6 containing an etching solution 5 containing hydrofluoric acid and pure water at a ratio of 1:9, and the high impurity concentration substrate 1a is anodized in the etching solution using a DC power source 9. , a DC voltage of several volts is applied using platinum 10 as a cathode to remove a predetermined region of the substrate 1a. At this time, etching stops when the impurity concentration and etching rate as shown in the graph of the relationship between impurity concentration and etching rate in FIG. Since this is carried out at the concentration boundary surface, the low impurity concentration layer 8 having the initially set thickness t remains as the thickness of the raised portion, ensuring high accuracy. In addition, in this etching process, the high impurity concentration substrate 1a and the metal film of the second layer protective film 4 are electrically insulated by the oxide film of the first layer protective film 3, so the etching process takes a long time, for example, 2 hours or more. Even with respect to the etching time, only the desired concave portions of the high impurity concentration substrate 1a are etched, and the other portions can be completely protected from etching.
このようなエツチング保護膜はピンホールなど
がなく下地との密着性に優れ、凹部成形過程にお
ける剥離もなく、保護膜自体が溶解するという現
象もみられない。 Such an etching protective film has no pinholes and has excellent adhesion to the base, does not peel off during the process of forming the recesses, and does not exhibit the phenomenon of the protective film itself dissolving.
なお電気科学的なストツプエツチングに供する
圧力検出素子の構成は上記実施例に示したものに
限られることなく、実施例とは異なる半導体基板
を用いてもよく、起わい部側の変形として第１図
ａ〜ｃに示す断面図のようにすることができる。
第１図ａ〜ｃが第２図〜第４図と共通する部分は
同一符号を用いて表わしエツチング除去される部
分を点線で記入してある。 Note that the configuration of the pressure detection element used for electrochemical stopping is not limited to that shown in the above embodiment, and a semiconductor substrate different from that in the embodiment may be used. It can be made as shown in the cross-sectional views shown in FIGS. 1a to 1c.
Portions in FIGS. 1a to 1c that are common to FIGS. 2 to 4 are designated by the same reference numerals, and portions to be removed by etching are indicated by dotted lines.
第１図ａは1018／c.c.以上のボロンを含むP+型高
不純物濃度シリコン基板１ｂの片面に1015／c.c.以
下の燐をドーピングしたｎ型低不純物濃度層８ａ
を積層し、このｎ型低不純物濃度層８ａにひずみ
ゲージ２を形成した二層積層ウエハとしたもので
ある。 FIG. 1a shows an n-type low impurity concentration layer 8a doped with phosphorus of 10 15 /cc or less on one side of a P + type high impurity concentration silicon substrate 1b containing boron of 10 18 /cc or more.
This is a two-layer laminated wafer in which the strain gauges 2 are formed on the n-type low impurity concentration layer 8a.
第１図ｂは1019／c.c.以上の砒素または1018／c.c.
以上のアンチモチンを含むN+型高不純物濃度シ
リコン基板１ａの片面に1015／c.c.以下のボロンを
ドーピングしたＰ型低不純物濃度層８ｂを設けさ
らにその上に1015／c.c.以下の燐をドーピングした
ｎ型低不純物濃度層８ｃを積層し、このｎ型低不
純物濃度層８ｃにひずみゲージ２を形成した三相
積層ウエハとしたものである。 Figure 1b shows arsenic of 10 19 /cc or more or 10 18 /cc
A P-type low impurity concentration layer 8b doped with boron of 10 15 /cc or less was provided on one side of the N + type high impurity concentration silicon substrate 1a containing antimothine, and further doped with phosphorus of 10 15 /cc or less. This is a three-phase laminated wafer in which an n-type low impurity concentration layer 8c is laminated and a strain gauge 2 is formed on the n-type low impurity concentration layer 8c.
第１図ｃは1019／c.c.以上の砒素または1018／c.c.
以上のアンチモンを含むN+型不純物濃度シリコ
ン基板１ａの片面に1015／c.c.以下のボロンをドー
ピングしたＰ型低不純物濃度層８ｂを設け、その
上にP+高不純物濃度層８ｄ、さらにその上に
1015／c.c.以下の燐をドーピングしたｎ型低不純物
濃度層８ｅを順次積層しｎ型低不純物濃度層８ｅ
にひずみゲージ２を形成した四層積層ウエハであ
る。 Figure 1 c is 10 19 /cc or more arsenic or 10 18 /cc
A P - type low impurity concentration layer 8b doped with boron of 10 15 /cc or less is provided on one side of the N + type impurity concentration silicon substrate 1a containing the above antimony, and a P + high impurity concentration layer 8d is formed on top of the layer 8b. to
N-type low impurity concentration layers 8e doped with phosphorus of 10 15 /cc or less are sequentially laminated to form n-type low impurity concentration layers 8e.
This is a four-layer laminated wafer on which strain gauges 2 are formed.
以上第１図ａ〜ｃの被エツチング素子の保護膜
３，４についてはいずれも前述した実施例の場合
と同様である。 The protective films 3 and 4 of the elements to be etched shown in FIGS. 1a to 1c are the same as in the embodiment described above.
はじめに説明したように、半導体圧力変換素子
の起わい部を形成する際に、従来高不純物濃度半
導体基板の片面に設けた低不純物濃度層とは反対
面の非エツチング面にクロムと金の二層金属保護
膜を被着した後、エツチング液中で基板を陽極、
白金を陰極として直流電圧を印加してエツチング
の進行を不純物濃度境界面で停止することによ
り、凹部を形成していたので、クロム保護膜の剥
離や溶解などに起因する起わい部の厚さの不均一
を生じ圧力変換素子の感度のばらつきが大きかつ
たのに対し、本発明によれば実施例で述べたごと
く、非エツチング面を被覆する保護膜としてシリ
コン酸化膜およびニツケルとクロムとを含む金合
金膜からなる二層保護膜を用いたために、電気化
学的ストツプエツチングの進行中においてもこの
エツチング保護膜は良好な密着性と長時間にわた
る十分な耐エツチング性を保持し、保護膜自体の
剥離もしくは溶解などを生ずることなく、その結
果、形成された起わい部は寸法的にばらつきが５
％以下という高い精度をもつようになるので、圧
力変換素子の出力感度のばらつきも小さくするこ
とに成功したものである。
As explained in the introduction, when forming the raised portion of a semiconductor pressure transducer element, two layers of chromium and gold are deposited on the non-etched surface opposite to the low impurity concentration layer that was conventionally provided on one side of the high impurity concentration semiconductor substrate. After depositing the metal protective film, the substrate is placed in an etching solution as an anode.
The recesses were formed by applying a DC voltage using platinum as the cathode and stopping the etching process at the impurity concentration interface, so the thickness of the recesses due to peeling or dissolution of the chromium protective film could be reduced. In contrast, according to the present invention, as described in the embodiment, a silicon oxide film, nickel, and chromium are included as a protective film covering the non-etched surface. Because a two-layer protective film made of a gold alloy film is used, this etching protective film maintains good adhesion and sufficient long-term etching resistance even during electrochemical stop etching, and the protective film itself As a result, the formed ridges have dimensional variations of 5.
Since it has a high accuracy of less than %, it has also succeeded in reducing variations in the output sensitivity of the pressure transducer element.
第１図はそれぞれ本発明に基づくエツチングに
適用可能な被エツチング素子のそれぞれ異なる例
を示す断面図、第２図は従来の被エツチング素子
の断面図、第３図は従来の浸漬エツチング法の概
念図、第４図は電気化学的ストツプエツチング法
の概念図、第５図は基板の不純物濃度とエツチン
グ速度との関係を示す線図である。
１ａ……高不純物濃度シリコン基板、２……ひ
ずみゲージ、３……第１層保護膜、４……第２層
保護膜、５……エツチング液、７……起わい部、
８……低不純物濃度層、９……直流電源、１０…
…白金電極、１１……不純物濃度境界面。
FIG. 1 is a sectional view showing different examples of elements to be etched that can be applied to etching according to the present invention, FIG. 2 is a sectional view of a conventional element to be etched, and FIG. 3 is a concept of a conventional immersion etching method. 4 is a conceptual diagram of the electrochemical stop etching method, and FIG. 5 is a diagram showing the relationship between the impurity concentration of the substrate and the etching rate. 1a... High impurity concentration silicon substrate, 2... Strain gauge, 3... First layer protective film, 4... Second layer protective film, 5... Etching solution, 7... Raised portion,
8...Low impurity concentration layer, 9...DC power supply, 10...
...Platinum electrode, 11... Impurity concentration interface.
Claims (1)
コン基板の一表面に低不純物濃度層を気相成長さ
せ、低不純物濃度層にひずみゲージを形成し、基
板他面の所定の非エツチング面に二層保護膜を設
けた後、基板をエツチング液に浸漬して基板を陽
極、白金を陰極として直流電圧を印加してエツチ
ングし、基板の不純物濃度境界面でエツチングの
進行を停止することにより、基板に凹部を形成す
る方法において、前記保護膜を基板に被着したシ
リコン酸化膜と該酸化膜上に被着したニツケルお
よびクロムを含む金合金膜とからなる二層保護膜
とすることを特徴とする半導体圧力変換素子起わ
い部の形成方法。1. A low impurity concentration layer is grown in vapor phase on one surface of a single-crystal silicon substrate of one conductivity type containing a high concentration of impurities, a strain gauge is formed in the low impurity concentration layer, and a strain gauge is grown on a predetermined non-etched surface of the other surface of the substrate. After providing the two-layer protective film, the substrate is immersed in an etching solution and etched by applying a DC voltage with the substrate as an anode and platinum as a cathode, and the progress of etching is stopped at the impurity concentration interface of the substrate. A method for forming a recess in a substrate, characterized in that the protective film is a two-layer protective film consisting of a silicon oxide film deposited on the substrate and a gold alloy film containing nickel and chromium deposited on the oxide film. A method for forming a raised portion of a semiconductor pressure transducer element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23796384A JPS61116879A (en) | 1984-11-12 | 1984-11-12 | Method of forming semiconductor pressure converter strain portion |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23796384A JPS61116879A (en) | 1984-11-12 | 1984-11-12 | Method of forming semiconductor pressure converter strain portion |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61116879A JPS61116879A (en) | 1986-06-04 |
| JPH0340959B2 true JPH0340959B2 (en) | 1991-06-20 |
Family
ID=17023057
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23796384A Granted JPS61116879A (en) | 1984-11-12 | 1984-11-12 | Method of forming semiconductor pressure converter strain portion |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61116879A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009116286A1 (en) | 2008-03-18 | 2009-09-24 | 国立大学法人山口大学 | Flocculent yeast and method for production thereof |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2514210B2 (en) * | 1987-07-23 | 1996-07-10 | 日産自動車株式会社 | Method for etching semiconductor substrate |
| US5352048A (en) * | 1988-12-23 | 1994-10-04 | Canon Kabushiki Kaisha | Ink sheet cassette and recording apparatus capable of loading the ink sheet cassette |
-
1984
- 1984-11-12 JP JP23796384A patent/JPS61116879A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009116286A1 (en) | 2008-03-18 | 2009-09-24 | 国立大学法人山口大学 | Flocculent yeast and method for production thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61116879A (en) | 1986-06-04 |
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