JPH033239B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a frequency control device suitable for electronic musical instruments that generates data for expressing frequencies, and particularly to one that controls frequencies using a digital method. Conventionally, various proposals have been made for musical tone generators using digital systems. Among these, digital data of a sine wave or a musical sound waveform is stored in memory, and this is read out sequentially to create a continuous musical sound waveform, which is then multiplied by envelope data corresponding to an envelope signal. hand,
There is a device in which a musical tone signal from the rise to the fall of a sound is formed by changing the amplitude value. In order to change the frequency of the generated waveform, it is sufficient to skip over a predetermined number of samples and read each sample of the digital data, instead of reading each sample sequentially. If the jump number is J, the frequency can be set in direct proportion to J. Instructions on how to generate such signals were published in 1969 by THE MIT
The book “The Technology” published by PRESS
of Computer Music", pages 134 to 138. Also, the magazine IEEE Trans.on Audio
and Electroacoustics, Volume 19, No. 1, 48-58,
1971 Document A Digital Frequeney Synthesizer”
shows the specific configuration. A more specific and practical system based on these known examples is described in Japanese Patent Application Laid-Open No. 58-65493. For these musical tone synthesis methods, it is necessary to generate and supply the jump number J. The present invention relates to a method for generating and supplying a jumping number J, and is particularly devised to efficiently generate various frequencies. Next, the relationship between the method of the present invention and the conventional example will be described. Conventionally, music synthesizers generate a key voltage V _K corresponding to each key on the keyboard, and then superimpose a frequency setting voltage V _F and a vibrato voltage V _V on this voltage to obtain V ₁ = (V _K + V _F + V _V ), and through the exponential converter we get V ₀ = K ₁ exp (V _K + V _F + V _V ), and the voltage V ₀
determines the oscillation frequency of the voltage controlled oscillator (VCO). When the voltage V _F is 0V, the key voltage
A frequency determined by V _K , that is, a frequency corresponding to the musical scale (261.625 Hz for C ₃ ) is generated. Normal key voltage V _K is 1V per octave
is considered standard. When 1V is added as voltage V _F , the frequency rises by one octave and 513.25Hz is generated.
This hits C ₄ as well as the second harmonic of C ₃ . If a voltage other than 1V is applied as the voltage V _F , arbitrary harmonic components such as the third and fourth harmonic components can be obtained. The vibrato voltage V _V modulates the frequency up and down around each of the above frequencies, but what is important here is that even if V _K and V _F have various values, the rate of frequency fluctuation is , the pitch fluctuation remains constant if V _V is constant.
Japanese Patent Laid-Open No. 1981-81824 is known as a method in which such a method is replaced with digital calculation. However, such conventional devices have drawbacks such as being unstable because they are made of analog circuits, and requiring a large number of highly accurate digital arithmetic units. Furthermore, as shown in Japanese Patent Application Laid-open No. 74298/1983, some digital processing methods handle frequency information on a cent scale, but they cannot handle non-harmonic components. The present invention corresponds to a musical sound waveform generation method or apparatus that generates a frequency proportional to a frequency control value, and provides the following features:
The present invention relates to a device for calculating frequency control values, and in particular, it is capable of obtaining frequency control values for generating musical tones having non-integer harmonics of the fundamental frequency. For this purpose, we define the fundamental pitch frequency and positive harmonic frequency by the number of cents, and furthermore, by newly introducing the number of cents difference between the non-integer harmonic and the positive harmonic, we This allows for flexible expression. In addition, as a second purpose, by focusing on the basic principle of the 12-average ratio of the scale, the middle digit of the cent address is given special treatment, making it possible to perform rational calculations. In order to achieve the above object, the present invention provides pitch information corresponding to the pitch frequency of the fundamental tone of a musical tone to be generated consisting of a fundamental tone and harmonics; positive harmonic information regarding the harmonic order of the musical tone; Inputting non-harmonic information representing an amount of deviation from an integral multiple of the frequency, dividing at least one octave interval into a plurality of intervals having predetermined cent intervals at equal intervals,
Allocate an address on the cent scale to the boundary of the above section, give the pitch information in the form of a cent address, output the positive harmonic frequency information as a cent address in the form of a difference from the pitch information, and Non-harmonic information is provided in the form of a non-harmonic difference cent address corresponding to the deviation, and a cent address of the pitch information, a difference cent address corresponding to the positive harmonic frequency information, and a non-harmonic difference cent address are provided. The system adds the addresses to obtain a sum cent address, and adds the converter to convert the sum cent address to a frequency control value that is directly proportional to the frequency to obtain a frequency control value. A storage means for storing wave number information and non-harmonic information, at least one bus line for information transmission coupled to the storage means, an arithmetic unit connected to the bus line, and a calculation result thereof stored. The configuration includes a storage means, a device for outputting the calculation result to the bus line, and the converter. FIG. 1 is a block diagram of an electronic musical instrument employing the frequency control device of the present invention. 1 is a keyboard section, 2 is an operation section consisting of a tone tablet switch, a vibrato effect on/off switch, a volume for setting the depth of the vibrato effect, etc., and 3 is a central processing unit (CPU), which is used in computers etc. 4 is a read/write storage device (random access memory, usually
5 is a read-only storage device (read-only memory, usually called RM) in which a program that determines the operation of the CPU 3 is stored; 6 is a
A ROM 7 stores envelope parameters among parameters for synthesizing timbres, and a ROM 7 stores data related to frequencies among parameters for synthesizing timbres. 8 is a frequency control device of the present invention, 9 is the above-mentioned sine wave generator, 10 is an envelope data generator, 1
1 is a multiplier that multiplies the sine wave and envelope data; 12 is a time slot control device that adds predetermined results of time-division multiplexed multiplication results or replaces them with the order of time-division multiplexing; time division multiplexed phase modulator, 14
is a digital-to-analog converter, and 15 and 16 are electroacoustic transducers. Keyboard section 1, operation section 2, CPU 3, RAM 4,
ROM5, ROM7, frequency control device 8, and envelope data generator 10 are coupled by a data bus, an address bus, and a control line.
The method of coupling data buses, address buses, and control lines in this manner is a well-known method for configuring minicomputers and microcomputers. Eight to 16 data buses are used, and data is transmitted and received on these bus lines not in one direction but in multiple directions in a time-division manner.
A plurality of address buses, for example 16, are prepared, and normally the CPU 3 outputs the address code, and other parts receive the address code. Control lines are usually memory request lines (),
An I/request line (IRQ), a read line (), a write line (), etc. are used. indicates reading and writing memory,
IRQ indicates the retrieval of the contents of the input/output device (I/), indicates the timing to read data from the memory or I/, and indicates the timing to write data to the memory or I/.
An example of a device using such a control line is the microprocessor Z80 manufactured by Zilog. Next, the operation of the electronic musical instrument shown in FIG. 1 will be described. The keyboard section 1 is configured such that a plurality of key switches are divided into a plurality of groups and the N-FF states of the key switches in the group can be sent to the data bus all at once. For example, for a 5-octave keyboard
The 61 keys are divided into 11 groups: 10 groups of 6 keys (half an octave) and 1 group of only 1 key, and one address code is assigned to each group. An address code indicating one of the above groups arrives on the address line,
When IRQ is applied, the keyboard section 1 decodes the address code and outputs 6-bit or 1-bit data indicating N-FF of the key switch in the corresponding group to the data bus. These can be constructed using decoders, bus drivers and some gate circuits. Of the operation section 2, the tablet switch is connected to the keyboard section 1.
A similar configuration can be taken. Regarding the setting state of the volume, the voltage output from the volume is converted into a digital code by an analog-to-digital converter, and this is read out using an address code and a control line IRQ. The CPU 3 reads the instruction code from the address of the RM5 corresponding to the code of the internal program counter, decodes it, and performs arithmetic operations.
It performs tasks such as reading and writing logical operation data and jumping instructions by changing the contents of the program counter. The steps for these tasks are RM
It is written in 5. First, the CPU 3 reads a command for importing data of the keyboard section 1 from the ROM 5, and imports codes indicating N-FF of each key of the keyboard section 1 for each group. Then, the pressed key code is assigned to a finite channel of the musical tone generator. Next, the CPU 3 sequentially reads a group of instructions from the RM 5 for importing data from the operation section 2, decodes them, outputs the address code and control signal IRQ corresponding to the operation section 2, and outputs the corresponding address code and control signal IRQ to the data bus. Output the code that expresses the switch and volume status of part 2,
Load into CPU3. Then, the CPU 3 knows which tone of musical tone signal should be synthesized. Now that it has become clear which channel of the musical tone generation section should generate which tone at which frequency, the CPU 3 selects the desired tone from the ROM 7 which stores data regarding the frequency of each tone. It outputs an address code storing frequency parameters and a control signal, reads the desired frequency parameters onto the data bus, takes them into the CPU 3, and writes them into the frequency control device 8. In order to write, the CPU 3 outputs the address code corresponding to the data register provided inside the frequency control device 8, and at the same time outputs the address code to the data register provided inside the frequency control device 8.
When ORQ and are output, data representing the frequency parameter being output on the data bus at the rising edge of the signal is written into the data register. Next, timbre parameters representing the content of the timbre to be output are read from the RM 6 and written into a register inside the envelope generator 10. Next, when a sound output command is given to both the frequency control device 8 and the envelope generator 10, the frequency control device 8 gives the jump number J to the sine wave generator 9, and the envelope generator 10 generates envelope data. . The sine wave data output from the sine wave generator 9 and the envelope data are multiplied to give an envelope to the sine wave. The sine wave data and envelope data are generated by being time-division multiplexed, respectively. Time division multiplexing is performed, for example, by 160 multiplexing, allocating 20 sine waves per channel, and providing 8 channels. Normally, one musical tone is synthesized by combining 20 sine waves.
Therefore, as known from the Fourier series formula, 20 sine wave data are added.
Data addition between time slots for this purpose is performed by the time slot converter 12. The time slot converter adds predetermined data from among the sine wave data strings modulated with envelope data, which are time-division multiplexed and input into 160 time slots, to reduce the number of time slots, or The time slots are exchanged like the time division multiplex converter described in Japanese Patent Publication No. 58-103244. The time-division multiplexing phase converter 13 performs multiple types of modulation simultaneously by time-division multiplexing, like the "digital musical tone modulation device" described in Japanese Patent Application Laid-Open No. 58-83894. The output of the time division multiplexing phase modulation device 13 is converted to an analog-to-digital converter 14.
The signals are converted into analog signals and outputted from electroacoustic transducers 15 and 16. Although not shown in FIG. 1, the time slot converter 12 and the time division multiplex phase modulation device 13 are also connected to the CPU 3 via address buses, data buses, and control lines, and are controlled by the operating section 2. The time slot conversion and modulation conditions can be changed and set in response to the settings of the timbre and modulation effect that are performed at the same time. In the frequency control of the present invention, first, the note octave of each key, the frequency of each harmonic, etc. are arranged on a cent scale and processed. The note and octave position of the fundamental wave of the musical tone to be output, the position of harmonics relative to the fundamental wave, the relative shift of non-harmonics, etc. are expressed in cents, and the cent address can be added or subtracted on the cent scale. Then, the cent address for the cent value of the actual frequency component is obtained, and this is subjected to exponential conversion. In order to digitize the system and find the jump number J for a large number of spectra, consideration is given to quantizing and handling one octave on the cent scale and performing arithmetic processing by time division multiplexing. Also, the timing is considered so that the calculated J is appropriately transferred to the sine wave generator 9. The present invention relates to a frequency control device 8 as a part of an electronic musical instrument as shown in FIG. It is. One embodiment is shown in FIG. The frequency control device in Fig. 2 includes a data bus DB,
address bus ADR, control line IRQ and
It is connected to the CPU 3 through the WR and chip select line CS, receives frequency parameters, decodes the code of the address bus ADR with the microcomputer interface circuit (MIF) 25, and writes it to the internal register group. A plurality of necessary J _i are calculated through a mechanism for calculating the jump number J, and are supplied to the sine wave generator 9 through the buffer memory 29 and octave shifter 30. First, the constituent elements will be explained. 21 is a program counter (PC) that supplies timing pulses, and 22 is a timing that extracts logic from timing pulses to create necessary address codes, or receives control flag (FLG) signals to create control signals. A pulse generator (TPG), 23 is a sequencer (SEQ) consisting of an RM, which is read out by timing pulses and control signals, and stores the contents and procedures of arithmetic operations and logical operations, which will be described later.24 is a sequencer The contents are decoded and the address code, output command signal (OC1~12), write command signal (0~
3) It is an instruction decoder that outputs an operation command signal (P code), etc. 25 is the microcomputer interface circuit (MIF) described earlier.
26 is an arithmetic unit (ALU) that performs addition, subtraction, and comparison between two inputs, the A bus and the B bus, outputs the operation result to the C bus, and records the sign, upper bit, etc. of the operation result. Output as FLG.
FLG is supplied to TPG22. 27 is the working register (WREG)
It consists of two words of memory, WREG1 and WREG2, and accepts input from the C bus and supplies output to the B bus. AD2 selects one of the two words and writes it at the rising edge of 1, and provides an output when C8 is "H". 28 is a RAM consisting of 160 words x 15 bits, which receives input from the C bus and supplies output to the D bus. The 160 words are divided into 8 channels of 20 words each, and any one word within the 20 words can be converted into a 5-bit address code.
Specified by AD1, any one of the 8 channels
Select the channel with the 3-bit address code AD4, and write the data on the C bus at the rising edge of AD4. The output remains on the D bus. However, the upper five bits of the output are supplied to the buffer memory 29. Buffer memory 29 is 160 words x
17-bit RAM, C bus data and RAM2
The upper 5 bits of 8 are accepted as input. 160
The words are divided into 8 channels of 20 words each, and one word out of the 20 words is used as an address code.
Select with AD3, select one of the 8 channels with address code AD4, write input data at the rising edge of 3, and output when OC9 is "H". The output of buffer memory 29 is supplied to octave shifter 30. Based on the code of the upper 5 bits of the buffer memory 29, the lower data is bit-shifted by a predetermined number of bits and output. This output is transferred to a register corresponding to a predetermined address among the registers provided inside the sine wave generator 9 and storing the jump number. 33 is the note octave register (ND
(n)) to get the latest note octave data,
It is accepted from the CPU 3 via the data bus DB and output to the A bus when necessary. MRW write
In step 2, reading is performed in OC2. 34 is a note octave register (ND(n-1)) which receives the previous note octave data from the CPU 3 via the data bus DB, and outputs it to the B bus when necessary. It also receives and stores intermediate processing data from the B bus. Write data from DB with 3, write from B bus with 0, and output to B bus with C3. 35
is a harmonic data memory (HMD), which is composed of 64 words x 13 bits RM.
Which of the 64 words is selected is determined by a 6-bit code output from the partial number memory 36. The partial number memory 36 is
Data bus DB with 20 words x 6 bits RAM
Accept input from. Select 1 word out of 20 words with address code AD1 and write at the rising edge of 4. The output is always supplied to harmonic data memory 35. The output of the harmonic data memory is output to the A bus when C4 is "H". 37 is non-harmonic memory (INH),
It consists of 20 words x 6 bits RAM.
1 word out of 20 words is address code AD
1 is selected, data bus is selected at the rising edge of 5.
DB data is written and output to the A bus when C5 is "H". Reference numeral 38 denotes an exponent conversion table (EXP) composed of RM. The D bus is input, and when C6 is "H", its contents are output to the A bus. 39 is a differential exponent conversion table (DEXP), which is composed of RM, takes the D bus as input, and when C6 is “H”, stores the stored contents in B.
Output to bus. The contents of these two tables will be described later. 40 is a gate which inputs the D bus and outputs to the B bus when C7 is "H". 32 is a portamento register (PRT) which accepts a code representing portamento speed from the data bus and stores it at the rising edge of 1. 31 is a portamento data converter, which generates frequency increase/decrease data based on the contents of the portamento register 32, and when C1 is "H"
Output to the A bus when . The same contents as the normal portamento register 32 are output. 42 is a vibrato data generator that generates a code representing a vibrato waveform, and C10 is set to "H".
When VIB(n) is connected to B bus, C11 is “H”
When VIB(n) is connected to the A bus, C12 is “H”
When , VIB (n-1) is output to the B bus. VIB
(n) represents the current vibrato data,
VIB(n-1) represents the previous vibrato data. 41 is status flip-flop (SFF)
Then, the data on the data bus DB is stored at the rising edge of 6, and the contents are supplied to the TPG 22. The TPG 22 generates an interrupt signal when the frequency control device requests new data from the external CPU 3;
The interrupt vector code indicating the interrupt contents is sent to the data bus.
Output on DB. When the output command signals C1 to C12 are "L", the outputs of the memories and registers corresponding to them become high impedance and A
We are trying not to have any impact on buses or B buses. <Data Structure> Next, the data structure before and after the index conversion mechanism C for frequency control performed in the present invention will be described. One octave has a frequency ratio of 1:2. As a number directly proportional to the frequency, the jumping number J
is defined as follows. Assume that the memory that stores one waveform of a sound source consists of ²¹⁸ words (samples). Set the sample readout frequency to _c
If KHz is used, the frequency of the output waveform will be _c /2 ¹⁸ Hz when all samples are read out one sample at a time.
This corresponds to the jump number J=1. Generally, the frequency for the jump number J can be expressed as F= _c /2 ¹⁸ × J ... (1). In the present invention, one octave is quantized on the cent scale, and the calculated frequency value expressed on the cent scale is converted into an interlaced number directly proportional to the frequency by exponential conversion. The method of index conversion will be described next. One octave is expressed in cents,
It will be 1200 cents. The ratio of the two frequencies _A and F _B is as follows in cent scale CE. CE (cent) = 1200log ₂ (F _A /F _B ) …(2) If the jump numbers of frequencies _A and F _B are J _A and J _B , Let J _B correspond to C on the equal-tempered 12 chromatic scale,
And if its value is 2048 and J _A is expressed as J, then becomes. If this is written for the range of CE = 0 to 1200 (cents), it will look like Figure 3 A. Equation (5) is a curved line, which can be approximated by a broken line as follows. If you divide CE (0-1200) into 12 equal parts, you will get 100 cent intervals. This corresponds to the chromatic scale of 12 equal temperaments. Divide the 100 cents into 8 equal parts, making them 12.5 cents apart. Doing this will result in 12 x 8 = 96 points. Let J be _J for these 96 points CE _i =12.5×i (i=0 to L-1, L=96). Between i and i+1, further divide 12.5 cents into 8 equal parts. CE _i,j = 12.5i + 12.5/8j ...(7) (i = 0 ~ L-1, L = 96 j = 0 ~ M-1, M = 8) CE _i,j of equation (7) ( For j=1 to 7), linearly interpolated values are used. That is, J _i,j becomes the following formula. In general J _c : Number of jumps at the reference point L: Number of divisions in one octave M: Number of divisions within the linear interpolation section i = 0, 1, 2, ...L-1 j = 0, 1, 2, ...M- 1. As mentioned earlier, if L=96 and M=8
The 1200 cent interval is quantized into 768 points at intervals of 1.5625 cents. The error will be less than ±0.78125 cents. Assign addresses to these 768 points.
Let this be the cent address. Next, a method for calculating J _i,j in equation (8) will be explained. According to FIG. 3, J is represented by 2048 to 4096 in binary 12 bits for one octave. Figure 3B shows the range of CE=0 to 100 (cents) in detail. 100 cents is divided equally into 12.5 cents. Equation (8) is It can be expressed as Express i as a binary coded 96-decimal number. Since 96 = 4 x 3 x 8, the upper digits can be represented by two binary digits, the middle digit by a binary coded ternary number, and the lower part by three binary digits. The middle bit only needs to be 2 bits, so the total is 7 bits. j is represented by three binary digits and is the lower order of i.
In other words, 96 x 8 = 768 points within 1200 cents is the 4th point.
It can be represented by 10-bit codes _N3 to _N0 and _S5 to _S0 in Figure A. This code is called a cent address, of which N ₁ and N ₀ are expressed in binary coded ternary notation. For such a value of (i, j), J _i,p
Prepare 96 values for EXP38 in Figure 2. 96 addresses, each 12 bits, 96 x 12
= 1152-bit ROM. This J _i,p corresponds to the first term of equation (10). Next, as a difference, it is a part of the second term of (10). Prepare in DEXP39 in Figure 2. Since the maximum value of DJ _i,j is DJ _{95 .7} =25.784 when i=95 and j=7, DJ _i,j can be expressed as a 5-bit binary number.
Furthermore, there are 96×8=768 (i, j). Therefore, 768 St. Addresses, 786 x 5 =
It becomes RM of 3840 bits. The cent address input to the ROM of the EXP38 is the 7 bits {N ₃ to N ₀ , S ₅ to _{S 3 }} in FIG. N ₀ , S ₅
~S ₀ } 10-bit code. EXP
By adding the outputs of 38 and DEXP39, the equation (10) becomes
J _i,j is displayed as a 12-digit binary number. FIG. 4A represents a binary number or extended cent address representing a quantized pitch on a cent scale. O ₄ , O ₃ , O ₂ , O ₁ , O ₀
represents an octave. N ₃ , N ₂ , N ₁ , and N ₀ represent each note of the 12 equal-tempered chromatic scale within one octave. Among these, (N ₁ , N ₀ ) is binary digit 3
Represents the base numbers (0,0), (0,1), and (1,0); (1,1) does not occur. Therefore, (N ₃ ,
N ₂ , N ₁ , N ₀ ) are decimal numbers. In Figure 5 (N ₃
~N ₀ ) and the musical scale. S ₅ , S ₄ , S ₃ , S ₂ ,
S ₁ and S ₀ are 6-bit binary numbers that represent each pitch of the semitone interval divided into 64 equal parts. 1 octave is 1200
Since a semitone is a cent and a semitone is 100 cents, {S ₅ ~
S ₀ } represents a 100 cent interval at 1.5625 set intervals. FIG. 4B shows the data format of ND(n), where the lower 4 bits indicate a note and the upper 4 bits indicate an octave. ND(n) corresponds to the fundamental frequency ₁ of the musical tone with the specified octave and note. Figure 4C shows harmonic data representing the ratio of the frequency _k of each harmonic component included in a harmonic musical tone to the fundamental frequency ₁ in cents.
HMD _k . HMD _k = 1200log ₂ ( _k / ₁ ) ... (12) (k = 1, 2, 3, ..., 64) expressed in binary. (H ₁₂ ~ _{H 0} )
Using 13 bits, the accuracy is ±0.78125 cents,
2 ⁸ = up to 256th harmonic can be achieved. {H ₇ , H ₆ } are expressed in binary coded ternary numbers like {N ₁ , N ₀ }. FIG. 4D is a format of inharmonicity data INH representing non-harmonicity. INH
_is expressed as _a deviation of several cents from the HMD data in FIG. FIG. 4E expresses transient or steady fluctuations such as vibrato and glide on a cent scale. If the range of fluctuation is within ±100 cents, it can be represented by a 7-bit code {V ₆ to V ₀ }. Of these, _V6 becomes the sign bit. The procedure for determining the desired jump number J from the data shown in FIG. 4 will be explained. first,
Each symbol shall have the following meaning. (1) ND(n): The pitch frequency for note octave data (pitch information) at time n, expressed in cents address. (2) HMD _k : The cents expression of the kth positive harmonic frequency relative to the fundamental frequency. Once expressed in binary (positive harmonic difference cent address) HMD _k = 1200log ₂ ( _k / ₁ ), _k = k ₁ (k = 1
，
2, 3..., 64) ...(13) (3) INH _k : Cent display with a frequency shift from the k-th positive harmonic frequency, and expressed in binary (non-harmonic difference cent address) . If _k = k ₁ + d _k , then INH _k = 1200log ₂ (k ₁ + dk/k ₁ )...(14) Basically, however, when INH _k exceeds 100 cents, INH _k below 100 cents is used for handling purposes. To find , do the following. INH _k+p = 1200log ₂ k ₁ + p ₁ + (d _k − p ₁ )/k ₁ +
p ₁ ...(15) (p = 0, 1, 2, 3, ..., and d _k −p ₁
0) That is, it is shifted by d _k from the k-th harmonic, but it means that it is seen as shifted by (d _k −p ₁ ) from the (k+p)-th harmonic. (4) VIB(n): Displays the frequency deviation due to vibrato and glide at time n in cents,
and expressed in binary. (Modulation cent address) From the above variables, the cent display of the frequency of the k-th harmonic, that is, the cent address, can be determined with the symbol LGJ
Expressed as (i, j), LGJ _i,j = ND (n) + VIB (n) + HMD _k +
INH _k ……(16) becomes. LGJ _i,j has the data format shown in FIG. 4A. Among these, {N ₃ , N ₂ , N ₁ , N ₀ , S ₅ ,
The 7 bits of S ₄ , S ₃ } are in 96-decimal notation and represent i in equation (10). Similarly, the three bits {S ₂ , S ₁ , S ₀ } represent j. These codes can be converted to the EXP38 mentioned above.
By giving the address data of the exponent conversion table of DEXP39 and the differential exponent conversion table, exponent conversion can be performed according to equation (10). This is expressed by the following formula. J ^* _i,j = EXP [LGJ _i,p ] + DEXP [LGJ _i,j ]
...(17) From Figure 3A, the exponent conversion table has a range of only one octave. J ^* _i,j indicates a value within this range. If the range exceeds an octave, J ^* _i,j may be bit-shifted according to the octave data {O ₄ , O ₃ , O ₂ , O ₁ , O ₀ } shown in FIG. 4A. For example, when {O ₄ -O ₁ }=(00011), it is sufficient to shift 3 bits upward. As for how many bits to shift, use the sine wave generator 9
All you have to do is match it to the bit position. The above describes the data structure and the number of jumps J based on it.
The calculation procedure has been clarified. Although it is possible to realize a configuration in which equations (16), (17), and (18) are executed all at once, the embodiment of the present invention (Fig. 2)
Now, let's do it step by step. Various methods can be considered to execute equations (16), (17), and (18) step by step. Table 1 shows the procedure according to the configuration shown in FIG. 2 described above.

[Table] In Table 1, of instruction groups A, B, and C, A
and B show the procedure for calculating the jump number J for 8 channels and 20 spectra in each channel. Instruction group A is instructions 4 to 7, instruction group is instruction 8.
It consists of ~11. The content of each command is indicated by the command content. For example, instruction 4 is ND(n)
and VIB(n), and write the working register
This means storing in WREG2. Instruction 5 reads the contents of working register WREG2 and harmonic data HMD(I), adds them, and stores them in WREG2. Instruction 6 is WREG
2 contents and inharmonicity data INH(I)
are added and stored in register LGJ (K, I). Instruction 7 uses the contents of register LGJ (K, I) as an address code and converts it to an exponent conversion table.
It is applied to EXP 38 and differential index conversion table DEXP 39, and the respective outputs are added and stored in buffer memory BUF (K, I) 29. Here, I
represents a processing time slot (PTS), which will be described later, and also represents the spectrum number in each channel. I=1, 2, ..., 20. K is channel time slot (CHS)
It represents. K=1, 2, ..., 8.
CHS will be discussed later. Regarding instruction group B, the meaning of the operation contents can be similarly read from Table 1. Δ in instruction 8 is set to zero. Command group A is executed when note octave data ND(n) is changed,
After that, instruction group B is executed. In instruction group B, ND(n), HMD(I), and INH() do not change, so these calculations are not performed and the previous value L is used.
VIB by subtracting VIB (n-1) from GJ (K, I)
Perform calculations on the new value of (n) and perform exponential conversion. Note octave data ND
When (n) is updated, the program returns to instruction group A and then executes instruction group B again. In Table 1, ITS is an instruction time slot, and there are ITS1 to ITS4, and instructions 0, 4, and 8 are ITS
1 is executed. Also shown are write lines, write pulses, and output control lines that are activated when each instruction is executed. To execute the above instructions, the program counter 21, timing pulse generator 22, sequencer 23, and instruction decoder shown in FIG. 24 needs to work. less than,
Explain timing. FIG. 6 is a diagram showing the timing of the embodiment of FIG. FIG. 6A shows a sample arrangement of sinusoidal waveforms, and the sampling period of one sinusoidal waveform is 20 μs. FIG. 6B is an enlarged view of 20 μs, in which there are 8×20=160 time slots and 160 samples.
Each sample is processed in 125 μs steps. Channel 1 (CH1) has 20 samples.
The same applies to CH2 to CH8. On the other hand, Fig. 6C shows A
This is the timing to calculate the jump number J in synchronization with . Channel time slots CHS 1 to 8 are provided in units of 160 μs.
In CHS1, J calculation for channel 1 is performed,
Corresponding channel J calculations are performed in the following order. J calculation for each channel is repeated at a cycle of 160×8=1280 μs (1.28 ms). FIG. 6D shows the inside of each channel time slot CHS, and as an example, CHS1 is enlarged.
In CHS1, there are processing time slots PTS 1 to 32 in units of 5 μs. PTS(I), I
=1 to 20, calculate the jump number that determines the frequencies corresponding to 20 spectra (sine waveforms) in channel 1. And the first half of PTS21
At 2.5 μs, the 20 calculated values of J are
As shown in Figure F, the signal is transferred to the sine wave generator 9 (Figure 1) in steps of 125 ns. The timing of this transfer differs for CHS1 to CHS8. For example, in CHS8, it is executed in the latter half of PST24. Figure 6E is
This is an enlarged view of the contents of each processing time slot PTS1 to PTS20. PTS1 to 20 are respectively
It is divided into four parts: instruction time slots ITS1 to ITS4. Each is 1.25μs long. In these instruction time slots, the first
The instructions in the table are executed. Between PTS1 and 20,
In the embodiment of FIG. 2, calculations are performed centered on the ALU 26. Between PTS21 and 32,
New data is written mainly to the MIF 25 in FIG. 2 via the data bus DB, and VIB(n) and VIB(n-1) data are updated. There are various methods for creating the timing shown in FIG. FIG. 7 and FIG. 8 show an example. Figure 7 shows a timing counter, and 51 is a 14-stage counter with CK as input.
Output P ₀ to P ₁₃ . P ₀ to P ₂ perform binary coded quinary counting, and P ₃ to P ₁₃ perform binary counting.
{P ₅ , P ₄ } are codes representing instruction time slots ITS1 to ITS4, 5 bits of {P ₁₀ to P ₆ } are codes representing processing time slots PTS 1 to 32, {P ₁₃ ,
P ₁₂ , P ₁₁ } is the channel time slot CHS
It corresponds to a 3-bit code representing 1 to 8. The counter 52 is a 20-decimal counter consisting of five stages.
Output {Q ₄ , Q ₃ , Q ₂ , Q ₁ , Q ₀ }. Counters 51 and 52 are synchronized. counters 51 and 5
From the output of 2, the timing pulse shown in Figure 8 is obtained.
Created inside TPG22. CK is 125ns
(8MHz) frequency. _P1 , _P2 , ₃ , ₄ ,
₅ , ITS1-4, 1-4 are obtained. The ITS1-4 signals are the base signals for producing the output command signals OC1-12 in FIG.
WRC1~4 are write command signals 0~
This is the signal that creates WR3. Figure 9 shows the address codes AD3 and AD4 added to the buffer memory 29 and the output command signal C.
9. This is an example of a circuit that generates the write command signal 3. Address code AD4 is {P ₁₃ , P ₁₂ , P ₁₁ },
In AD3, either {P ₁₀ to P ₁₆ ) or {Q ₄ to _{Q 0} } is selected by the selector 69. 3 is a processing time slot created by the AND gate 70 with invert input and the OR gate 71 with invert input.
4 corresponding to ITS4 in PTS1-20
It is. And gate 60, 61, 62, 63
detects {P ₁₀ , P ₉ , P ₈ }={1,0,1}.
This corresponds to PTS21-24. At this time, the selector 69 selects _Q4 to _Q0 . EXR gates 64, 65, and 66 perform a match determination between {P ₇ , P ₆ , P ₅ } and {P ₁₃ , P ₁₂ , P ₁₁ }. The AND gate 67 selects the half section of the PTS that matches the CHS number among the PTS21 to 24, and outputs OC9 when the output is "H". Therefore, to summarize, in PTS1-20, in ITS4, AD4
and AD3 designate K and I, respectively, output 3 at ITS4, and write instruction 7 or 11 in Table 1 to buffer memory 29 (BUF (K, I)). CHS between PTS21 and 24=K
C9 becomes “H” for 2.5μs corresponding to
The contents of I=1 to 20 of BUF (K, I) are output according to address codes AD4 and AD3. FIG. 10 shows an example of the format of the instruction code stored in the sequencer 23 in FIG. 2-bit P code for operation,
It consists of a 3-bit destination code that indicates the data transfer or storage destination, a 3-bit source 1 code that indicates the register from which the data is taken out, and a 4-bit source 2 code. The meaning of each code is shown in FIGS. 10B-E. The P code specifies the function of the ALU 26. The operations of the 12 instructions shown in Table 1 are expressed by the instruction codes shown in FIG. Figure 10 E ZER
O wants to output ZER to the A bus. Based on the instruction code in Figure 10 and the CHS, PTS, ITS, write line, output control line, etc. in Table 1, using the same idea as illustrated in Figure 9,
The instruction decoder 24 and circuits that generate necessary control signals and timing pulses can be designed. FIG. 11 shows the timing of execution switching between instruction groups A and B in Table 1. From the top, channel time slot, operation execution, J transfer, interrupt pulse, data transfer, and KN flag are shown. Operation A or B is the processing time slot
PTS 1 to 20 (Figure 6) are executed 20 times.
At the end of the 20th time, the interrupt pulse is as shown in Figure 2.
The TPG 22 outputs the signal to the CPU 3 shown in FIG.
At this time, at the same time, CHS8 is used as an interrupt vector.
A code {P ₁₃ , P ₁₂ , P ₁₁ } indicating this is output to the data bus DB in FIG. The CPU 3 reads this interrupt vector {P ₁₃ , P ₁₂ , P ₁₁ } and executes the next
If it knows that CHS is 1 and the pitch to be played on channel 1 is changing, data transfer is performed. Data transfer is performed from the data bus of the CPU 3 to the data bus DB shown in FIG. and,
Predetermined data is written to ND(n) 33, PN36, INH37 and status FF41.
In particular, the KN flag flip-flop (FF) included in the status FF is set. The KN flag indicates that the pitch of the sound corresponding to CHS1 has been changed. When the KN flag is “1”, instruction group A is read and CHS1
executed between. When the execution is finished, an interrupt pulse is generated again and an interrupt vector indicating CHS1 is output. At the same time, KN flag FF is reset.
Interrupt pulse and interrupt vector {P ₁₃ , P ₁₂ , P ₁₁ }
In response to this, the CPU 3 determines whether or not the previous pitch will remain the same in the next CHS 2, and data transfer will not be performed if the same pitch should be produced. Therefore K
The ON flag remains "0". At this time,
Instruction group B is executed 20 times. The instruction group A is a program that calculates J based on new ND(n) data, and the instruction group B is a program that corrects only changes in vibrato data with respect to the previous J. The reading and switching of instruction groups A and B are performed by reading out and switching instructions corresponding to instruction time slots _ITS1 to ITS4 within the time period in which the processing time slot codes {P10 to _P6 } of the counter 51 in FIG. 7 indicate PTS1 to PTS20. This can be done by reading out groups A and B, selecting one using the KN flag, and outputting it. In the embodiment of FIG. 2, the amount of data to be transferred from the CPU 3 to the frequency control device of the present invention is N
OD(n) 1 word, PN 20 words, INH
20 words, 1 word for status FF, 1 word for PRT
A total of 43 words is sufficient. In the above description, one vibrato data generator 42 is common to eight channels. In case of glide effect, glide data GL(n,k)
and GL(n-1,k), (k=1,2,...,8) are provided independently for each channel, and each CHS1
By outputting the respective data corresponding to 8, an independent glide can be applied to each channel. In the above explanation, as the buffer memory 29,
Although 160 words have been prepared, one transfer is performed in units of 20 words, so 20 words may be prepared. Regarding the partial number memory 36 and harmonic data memory 35 in FIG. 2, the former may have 13 bits per word, and the latter may have 6 bits per word. The maximum harmonic order is set to 64, but when increasing it, the number of words in the partial number memory must be increased to 64, and 1 of the harmonic data must be increased.
Just increase the number of words from 6 bits. Although the harmonic data may be transferred directly from the CPU 3, the amount of data to be transferred can be smaller in the embodiment shown in FIG. Further, in the embodiment of the present invention, it is possible to omit some of the many harmonic orders to generate a skip number J that is a toothless frequency control value. In addition, partial number memory 3
Although we explained that a different partial number is given to the 20-word RAM of 6, the same partial number can be stored in any plural words, and non-harmonic memory 3
When writing slightly different INH data to 7,
The generation of two or more frequency components of very close frequency becomes possible. In other words, a chorus effect can be obtained. Among keyboard instruments, the pitch of the piano tends to be lower in the low range and higher in the high range compared to the range of the keyboard, and the frequency ratio of one octave is not exactly 1:2. This phenomenon can be called pitch extend. To do this, an RM is provided to generate this shift, and this RM is accessed by the data of ND(n) to output the amount of shift corresponding to the note octave, and this amount is used as the difference address.
It may be added by ALU26. Further, the above deviation can also be included in the data written to the non-harmonic memory 37. It goes without saying that in order to generate a musical tone that does not have non-harmonic properties, it is sufficient to write a zero value as the INH frequency. In the above explanation, part of the data is displayed in binary coded ternary notation. Alternatively, display in binary coded 12 decimal notation, binary coded hexadecimal, etc. is also possible. It is also possible to obtain octave data by displaying and calculating data in complete binary representation, and then converting it into binary and ternary numbers for higher-order digits, including the note data part. good. For this purpose, a binary-ternary conversion ROM may be provided. In the embodiment shown in FIG. 2, there is only one register for ND(n). These registers and
If the number of RAMs is provided for 8 channels, the calculation procedure can be reduced to only group A. As described above, there is a relationship between the configuration and the calculation procedure, and there are various types other than those in this embodiment, but a description thereof will be omitted. In the above explanation, the procedure and configuration are described for calculating the jump number J for sine wave synthesis, but it can also be used for frequency control of a waveform generator that reads waveforms other than sine waves. For example, instead of 20 harmonic components, J is 1 for one waveform.
Even when only one is generated, an optimal configuration can be achieved using the same concept as above. <Portamento Effect> In the embodiment shown in FIG. 2, the number of jumps J can be gradually changed in response to the portamento effect. In the embodiment shown in FIG. 2, portamento is applied only to one channel, that is, CHS1. First of all, as mentioned earlier, in portamento mode,
This note octave data is ND(n)3
3, the previous note octave data is ND
(n-1)34. At the same time, portamento speed and key press interval ND(n) - ND
The data representing the increment corresponding to (n-1) is PRT
32. This data is stored as is or after some transformation in the portamento converter. Instruction group C in Table 1 determines whether portamento is increased or decreased. Instruction O adds an increment Δ to the previous ND(n-1). Instruction 1 compares and determines whether the result has reached, exactly matched, or exceeded the target value ND(n). CP is Compare
This is the meaning of As a result of this comparison, ALU26 is
Set its internal flag FLG. As the flag FLG of the ALU 26, a zero flag Z and a sign flag S are provided. These flags are attached to a normal adder/subtractor, and the zero flag Z is a flip-flop that becomes "1" when all bits of the operation result are "0" and becomes "0" otherwise.The sign flag S is a flip-flop. , is composed of a flip-flop which becomes "1" when the most significant bit of the operation result is "1" and becomes "0" otherwise. Based on the comparison result of instruction 1 and ΔS representing the sign of the increment Δ, instruction 2
or 3 is executed. Instruction 2 adds Δ to the current note octave data ND(n-1) and converts it into new note octave data N.
Store as D(n-1). Instruction 3 converts the final goal ND(n) to a new ND(n-1)
Store as . With the above instruction group C, in the portamento effect, by adding the increment Δ, the pitch is set to the target note octave data N.
A set of commands B that determines whether D(n) has not been reached, exactly, or exceeds the target value, and increases the frequency on the cent scale of the fundamental wave and harmonics by an increment Δ based on the result. , or execute a group of instructions A that performs calculations at the destination point based on the target value ND(n). FIG. 12 shows which of the instructions 0 to 11 will be executed depending on the combination of three flags ΔS, Z, and S. command 0
and 1 are executed every time. Depending on the flags Z, S and ΔS, which are the operation results of instruction 1, it is determined whether instruction 3 and instruction group A (instructions 4 to 7) are executed and instruction 2 and instruction group B (instructions 8 to 11) are executed. It is classified into cases in which it is executed. The former case is a case where the target value ND(n) is exactly reached or exceeded by accumulating the increments Δ. The latter is a case where the target value ND(n) is not yet reached even after accumulating the increments Δ. FIG. 13 is a timing chart in portamento mode. In the processing time slot PTS in which the operation is performed, instruction group C is executed in PTS32, and instruction groups A and B are executed in PTS1-20. An interrupt pulse is generated at the end of PTS20 or the beginning of PTS21 and is sent to CPU3 in Figure 1.
Request new data. At this time, the CHS code {P ₁₃ , P ₁₂ , P ₁₁ } is output to the data bus DB as an interrupt vector, and CPU3
You can also find out what the next CHS is. If the key has been changed and it is time to move to a new note octave, CPU 3 will write the new ND(n), the previous N
A group of data of OD(n-1), PN, and INH and status flag data are transferred. The status data includes a KN flag, and the KN flag FF is set to "1". In portamento mode, arithmetic processing can be performed regardless of this KN flag. First, in PTS32 of CHS8 immediately before CHS1, instructions 0 to 3 of instruction group C are
Execute. However, execution of one of instructions 2 and 3 is ignored due to the flags ΔS, Z, and S shown in FIG. Thereafter, instruction group A or B is executed in PTS1 to PTS20 of CHS1 according to the status of the flags. When reading instruction group C, PTS is 32, that is, processing time slot code {P ₁₀ to P ₆ } is {111111}.
At the timing when the address code indicating instructions 0 to 3 is
In addition to M, instructions 0 to 3 may be read. In order to ignore one of instructions 2 and 3, the read instruction output may be gated according to the codes of flags ΔS, Z, and S. Regarding the selection of instruction groups A and B, the 2 bits of the lower address code for reading instruction groups A and B are selected by {P ₅ , P ₄ } at the timing when the processing time slot codes {P ₁₀ to P ₆ } indicate 0 to 19. cause it to occur,
By specifying the upper 2 bits of the address code that distinguishes instruction groups A and B by a combination of flags ΔS, Z, and S, and adding a 4-bit address, instructions 4 to 7 and 8 to 11 in instruction RM are may be read out selectively. FIG. 14 shows an example of an adder in the ALU 26 that performs operations on data having the data structure shown in FIG. Since N ₁ and N ₀ are binary coded ternary numbers, the carry C _s from the lower S ₅ and the N ₁ on the A bus,
With N ₀ and N ₁ , N ₀ on the B bus as inputs, the outputs N ₁ , N ₀ on the C bus and carry C _N to the higher order are determined as shown in the truth table in FIG. 14A. B is an example of hardware. 80 is S ₅ on A bus and B bus
~S Binary adder inputting 6 bits of ₀ , 82 is A
A binary adder 81 which receives O ₅ to _{O 0} , N ₃ , and N ₂ on the bus and the B bus as input is a read-only memory (POM) having a truth table pattern. C _s is a carry of the binary adder 80, and C _N is a carry output from the ROM 81. Subtractors and comparators can also be constructed using a similar idea. Vibrato data generator 42 in FIG.
may be something like a digital sine wave generator. For example, the RM may be read from a ROM that stores the waveform of the vibrato signal and written to the register at the timing when the VIB(n) and VIB(n-1) are updated. The octave shifter 30 has a buffer memory 29
By adding multiple sets of codes obtained by shifting the output of 1 bit to the required bit to the respective gates, one set of these gates is converted to {O ₄ , O ₃ ,
The selection may be made using the code O ₂ , O ₁ , O ₀ }. In this example, the octave code has 5 bits, so 2 ⁵ = 32 different octaves can be taken, but the frequency range that humans can hear is from 20KHz to
As 20Hz, it is 10 ³ times 10 octaves, so
There are about 10 possibilities for bit shift. In this case, the MSB O ₄ may be omitted. In Figure 4, the data are 15 from O ₄ to S ₀ .
I thought it would be possible to handle bits. It goes without saying that when the data length is 15 bits or less as shown in FIGS. 4B to 4E, the extra bits above and below the bits may be arranged as "0"s. For negative numbers,
It depends on which display is used, such as 2's complement display or 1's complement display, but in the latter case, "1" is output to the topmost bit and "0" is output to the other bits, and in the former case, "1" is output to all upper bits. All you have to do is output it.
In the case of one's complement, the sign bit V ₆ in Figure 4E
should be used as the top level. As mentioned above, in the embodiment shown in FIG.
The jump number J is calculated by calculating each data in the format explained with the drawings in a step-by-step manner. Portamento mode (13th
To switch between the normal mode (Figure 11) and the normal mode (Figure 11), enter the status FF in Figure 2.
Prepare the RMAL/PRTAMETO mode bit, and send "1" to this bit from CPU3 to set it to normal mode, and send "0" to portamento mode, and change the instruction reading according to the mode bit. . Note that in the normal mode, zero is written in the PRT32 (FIG. 2). Make sure that Δ becomes zero. FIG. 15 is another example of index conversion. 3
8 stores J _i,p in EXP38, which is the same as in FIG.
39-1 is a differential ROM having addresses for 7 bits {N ₃ to S ₃ }, and stores differential values (J _i+1,0 −J _i,0 ) of 96 index sample values. The output is 5
It's bit. 39-2 is a simplified multiplication RM for outputting an interpolated value of the difference value according to the three bits {S ₂ , S ₁ , S ₀ }. That is,
(J _i-1,0 −J _i,0 )×j/8 is stored. This will increase the quantization error a little, but the memory size will change from 768 x 5 = 3840 bits to 96 x 5 + 2 ^{5 + 3} x
5 = 1760 bits. In FIG. 3A above, one octave is assigned to 2048 to 4095. Therefore, it is 12 bits. In this case, the 12 equal temperament notes will be within an error of ±0.78125 cents. However, at low frequencies, the bits are shifted according to the octave code, and it is also conceivable that the bits are shifted to the lower side. At this time, the lower 12 bits are truncated, sometimes resulting in 8 to 9 bits. At this time, the above error increases. For 9 bits, 3
Since it has been bit shifted, the error is 8 times or ±6.25 cents. However, as is well known, in 9 bits, 239, 253, 268, 284, 301,
For the combination of 12 numbers 319, 338, 358, 379, 402, 451, the error from 12 equal temperament is less than ±12 cents. Therefore, if C is 253×8=2024 and 239×16=3824 is B instead of 2048, conversion from a cent address to an skip number with the highest accuracy can be achieved using 12 bits. As described above, the present invention includes a storage means for storing pitch information, non-harmonic information of positive harmonic frequency information,
at least one bus line coupled to the storage means for transmitting the stored information; an arithmetic unit connected to the bus line for performing operations such as addition and subtraction; a storage means for storing the operation results; The device is equipped with a device for outputting to the bus line, and the arithmetic unit is used multiple times in a time-sharing manner to calculate each piece of information.
It has the characteristics of high efficiency in the use of arithmetic units, the ability to share a bus as a signal transmission line, and the ability to have a repeating structure centered around RAM and ROM, allowing for a small chip size when integrated into an integrated circuit. In particular, since the configuration is such that non-harmonic frequencies are treated as difference cent values from positive harmonic frequencies,
It becomes easier to set the tone quality of musical tones, and it becomes easier to set and generate tones such as bells and bells, which were not possible before. Also, according to the 12 average rate, the calculation of the scale is 2
Since it is a multiple base calculation of Evolution 3, it has the effect of being able to be configured with an efficient calculation circuit.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a digital electronic musical instrument to which the present invention is applied, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of an index conversion table, and Fig. 4 is a diagram of the above embodiment. FIG. 5 is a diagram showing an example of the data format used in the above embodiment, FIG. 6 is a diagram showing an operation timing chart of the above embodiment, and FIG. 7 is a diagram showing a counter for timing pulse generation. 8 is a diagram showing a timing pulse chart, FIG. 9 is a diagram showing a decoder, FIG. 10 is a diagram showing an example of an instruction code format, and FIG. 11 is a general timing chart in normal mode. , FIG. 12 is a diagram showing the instruction execution pattern in portamento mode, FIG. 13 is a diagram showing the global operation timing chart in portamento mode, FIG. 14 is a diagram explaining the operation of the adder, and FIG. 15 is an exponent diagram. It is a figure which shows an example of a conversion table. 1...Keyboard section, 2...Operation section, 3...CPU,
4...RAM, 5...RM, 6...Envelope parameter ROM, 7...Frequency parameter
ROM, 8... Frequency control device, 9... Sine wave generator, 10... Envelope data generator, 11
... Multiplier, 12 ... Time slot control device,
13...Phase modulator, 14...Digital-to-analog converter, 21...Program counter, 22...
...Timing pulse generator, 23...Sequencer, 24...Instruction decoder, 25...Microcomputer interface circuit, 26...Arithmetic unit, 27...Working register, 28...RAM, 29...Buffer memory, 30... …octave shifter, 31
... Portamento data converter, 32 ... Portamento register, 33, 34 ... Note octave register, 35 ... Harmonic data memory, 36 ... Partial number memory, 37 ... Non-harmonic memory, 38 ... Exponential conversion table, 39
...Difference index conversion table, 40...Gate, 4
1...Status flip-flop, 42...Vibrato data generator.

Claims (1)

[Claims] 1. Pitch information corresponding to the pitch frequency of the fundamental tone of a musical tone to be generated consisting of a fundamental tone and harmonics; positive harmonic frequency information regarding the harmonic order of the musical tone; Inputs non-harmonic information representing the amount of deviation from an integral multiple of the frequency, divides one octave interval into multiple intervals with predetermined cent intervals, and assigns addresses on the cent scale to the boundaries of the intervals. , the pitch information is given in the form of a cent address, the positive harmonic frequency information is output as a cent address in the form of a difference from the cent address corresponding to the fundamental frequency of the harmonic, and the non-harmonic information is It is given in the form of a non-harmonic difference cent address corresponding to the above deviation, and the cent address of the pitch information, the difference cent address corresponding to the positive harmonic frequency information, and the non-harmonic difference cent address are added. In addition to a converter that obtains a sum cent address and converts the sum cent address into a frequency control value that is directly proportional to the frequency, it also obtains a frequency control value, and the above-mentioned pitch information, positive harmonic number information, and non-harmonic storage means for storing wave information; at least one bus line for transmitting information coupled to the storage means;
A frequency control device comprising: an arithmetic unit connected to the bus line; storage means for storing the arithmetic results; a device for outputting the arithmetic results to the bus line; and the converter. 2. In the statement of claim 1, the storage means for pitch information, the storage means for positive harmonic frequency information, the storage means for non-harmonic information, and the storage means for calculation results are arranged in accordance with the number of sound generation channels. a frequency control device, wherein each of the storage means is coupled to at least one bus line, an arithmetic unit is coupled to the bus line, and the arithmetic operations of each of the information are performed by time division multiplexing in the arithmetic unit. Device. 3 In the description of claim 1, the middle digit of the cent address is binary coded decimal, binary coded 6
A frequency control device that displays in one of decimal, binary or ternary format, and uses the middle part of an arithmetic unit to perform calculations corresponding to the above display. 4 In the statement of claim 1, the cent address is expressed in binary, the arithmetic unit is a binary arithmetic unit, and the middle of the cent address of the calculation result is expressed in binary.
A converter that converts into one of decimal, binary coded hexadecimal, or binary coded ternary code is used to separate the code into an octave code and a note code, and the note code is added to the converter and its output is bit-shifted using the octave code. A frequency control device obtained by obtaining a frequency control device. 5. In the description of claim 1, the converter has at least a first memory that stores frequency control values corresponding to L cent addresses at M intervals among the number of cent addresses (L×M) within one octave interval. and a second storage device storing an interpolated value based on the difference value between adjacent frequency control values among the L frequency control values, and a cent address is added to the first and second storage devices to store both. A frequency control device that obtains a frequency control value corresponding to the above interval by adding the outputs of the device using an arithmetic unit. 6 In the description of claim 5, the second
The storage device includes a third storage device that stores the difference value between adjacent frequency control values, and a fourth storage device that receives the output of the third storage device and a predetermined lower bit of the cent address as input. Consisting of the above 4th
A frequency control device characterized in that the output of the storage device becomes the output of the second storage device.