JPH03293761A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the speed and electrical reliability of a Bi-CMOS by forming the base area of a bipolar transistor and the low-concentration source and drain areas of an MISFET through different impurity introducing processes. CONSTITUTION:A bipolar transistor Q1 is formed by selectively introducing an n-type and p-type impurities into an n<->-type epitaxial layer 4 grown on a P<->-type semiconductor substrate 1. A p-channel MISFET 1 is constituted of a gate electrode 18A, high-concentration source and drain areas 34A, both of which are composed of p<+>-type semiconductor areas, and gate insulating film 13 and contains a high-concentration source and drain areas 24. In addition, side-wall spacers 25 are provided on the side wall of the electrode 18A. An n-channel MISFET 2 is provided on the main surface section of a p-type semiconductor area 6A and is constituted of a high-concentration source and drain areas 31A and the gate insulating film 13. Therefore, the speed and electrical reliability of this Bi-CMOS can be improved.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and in particular, a technique that is effective when applied to a method for manufacturing a semiconductor integrated circuit device having a bipolar transistor and a MISFET. It is related to.

[Conventional technology]

Bipolar transistor and complementary MISFET (hereinafter referred to as
A bipolar CMOS device (hereinafter referred to as a Bi-CMOS) is a bipolar CMOS device (hereinafter referred to as a Bi-CMOS
) is used. Bi-CMOS is described, for example, in Nikkei Electronics J. March 10, 1986 issue, pages 199 to 217, published by Nikkei McGraw-Hill.

The Bi-CMOS described in the above document forms an npn-type bipolar transistor, a p-channel MOS, and an n-channel MOS on a p-type semiconductor substrate, and is a static random access memory (static random access 9 memory).
Random Access Memory: Hereafter S
RAM). SR with Bi-CMOS
By configuring AM, high speed and low power consumption SR
AM can be configured.

In addition, npn type bipolar transistor and LD
A Bi-CMOS having a (Lightly Doped Drain) structure is disclosed in, for example, Japanese Patent Laid-Open No. 125165/1983.

In the Bi-CMOS disclosed in this publication,
The base region of the npn-type bibolar transistor and the low concentration source region and drain region of the LDD structure p-channel MOS are formed in the same ion implantation process, thereby reducing the number of manufacturing masks used. .

[Problem to be solved by the invention]

However, as a result of studying the above-mentioned prior art, the inventor found the following problems.

In the Bi-CMOS manufacturing method, it is important from the viewpoint of reducing process costs to make the process of forming a bipolar transistor and the process of forming a CMOS common. For example, Bi disclosed in the above publication
- In the CMOS manufacturing method, the number of manufacturing masks is reduced by forming the base region of the bipolar transistor, the low concentration source region and the drain region of the LDD structure MOS in the same ion implantation process. At the same time, the number of manufacturing steps is reduced.

On the other hand, in order to increase the speed of bipolar transistors, it is necessary to reduce the resistance of the base region. That is, it is necessary to increase the impurity concentration in the base region.

However, in the manufacturing method disclosed in the above publication, the base region, the low concentration source region, and the drain region are formed in the same ion implantation process, so that the speed of the bipolar transistor can be increased. Therefore, when the impurity concentration of the base region is increased, the impurity concentrations of the low concentration source and drain regions of MO5 are correspondingly increased, and the dielectric breakdown voltage of the MOS is lowered.

As a result, the electrical reliability of Bi-CMO8 decreases.

Conversely, if the impurity concentration of the low concentration source region and drain region is optimized so as to ensure the dielectric breakdown voltage of the MO8, the impurity concentration of the base region will be correspondingly lower. The resistance of this base region increases. As a result, the operating speed of the bipolar transistor decreases.

In this way, in the Bi-CMO8 manufacturing method, if the process of forming bipolar transistors and the process of forming CMO8 are made common, the process cost can be reduced, but it is possible to reduce the process cost by increasing the speed of Bi-CMO8 and It is not necessarily advantageous in terms of electrical reliability.

The object of the present invention is to use bipolar transistors and MISFE
In a method of manufacturing a semiconductor integrated circuit device having T,
The object of the present invention is to provide a technology that can increase speed and improve electrical reliability, as well as reduce process costs.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

(1) A method for manufacturing a semiconductor integrated circuit device having each of a bipolar transistor and an MI 5FET having low and high concentration source and drain regions of the same conductivity type as the base region of the bipolar transistor,
A step of forming a gate electrode of the MISFET, a step of forming the low-strength source region and a drain region in self-alignment with the gate electrode, and a step of forming a sidewall spacer on the sidewall of the gate electrode. and forming a base region of the bipolar transistor having a higher impurity concentration than the low concentration source region and drain region, and forming a semiconductor region having the same impurity concentration as the base region in a self-aligned manner with respect to the side wall spacer. and forming the highly doped source and drain regions in a self-aligned manner with respect to the sidewall spacers.

(2) The base region and the highly doped source and drain regions are formed by ion implantation.

(3) The base region is formed by an ion implantation method using lower energy than the highly doped source and drain regions.

(4) The base region is formed by introducing impurities without using a photoresist film.

(5) In a method for manufacturing a semiconductor integrated circuit device having each of a bipolar transistor and a MISFET having a low concentration source region and a high concentration source region and a drain region having the same conductivity type as a base region of the bipolar transistor, the gate of the MISFET is provided. By forming an electrode, forming a sidewall spacer on the sidewall of the gate electrode, and introducing impurities without using a mask, the base region of the bipolar transistor is formed, and the base region of the bipolar transistor is formed under the sidewall spacer. The method includes a step of forming a lightly doped source region and a drain region, and a step of forming the highly doped source region and drain region in a self-aligned manner with respect to the sidewall spacer.

(6) The impurity concentration of the low concentration source and drain regions formed under the sidewall spacer is as follows:
The impurity concentration is lower than the impurity concentration of the base region.

[For production]

According to the above-described means (1) to (6), the base region of the bipolar transistor and the low concentration source region and drain region of the MISFET are formed in different impurity introduction steps, so that the base region, The junction depth and impurity concentration of each of the low concentration source region and drain region can be optimized. This allows Bi-CMO
It is possible to increase the speed of S and improve electrical reliability.

Further, since the base region is formed after forming the sidewall spacer, the main surface of the semiconductor substrate (the main surface of the semiconductor substrate in the region where the base region is formed) that is generated when forming the sidewall spacer is Etching is not a problem. That is, if the base region is formed before the sidewall spacer is formed, the surface of the base region will be etched when the sidewall spacer is formed, making it impossible to control the base width with high accuracy. On the other hand, according to the above-described means, such problems are inevitably solved and the base width can be controlled with high precision. Therefore, it is possible to further increase the speed and improve the electrical reliability of the bipolar transistor.

Furthermore, since the low concentration source region and drain region, which have an impurity concentration lower than the base region, are masked (covered) with the sidewall spacer, in the impurity introduction step for forming the base region, Formation of a new impurity introduction mask (specifically, a photoresist film) can be omitted. That is, the base region can be formed without using a base impurity introduction mask. Therefore, it is possible to reduce the process cost of B1-CMOS. Note that an impurity introduction mask may be used for forming the base region if necessary. In this case, there is no need to process a highly accurate mask pattern.

C Embodiments of the Invention] Prior to a detailed description of the present invention, an outline of a Bi-CMOS-5RAM that has both high speed and low power consumption will be described as a preferred object to which the present invention is applied.

The configuration of Bi-CMOS-5RAM is, for example, 0qiu
e at al (U.S. Patent No. 4,713,796: D
ate of patent;December 15,
1987), peripheral circuits such as address circuits and timing circuits are constructed from B1-CMOS composite switching circuits, and memory cells are constructed from high-resistance load type flip-flop memory cells.

FIG. 2 (principal circuit diagram) shows a Bi-C to which the present invention is applied.
2 is an equivalent circuit diagram of a MOS-5RAM (7) peripheral circuit section 110 and a memory cell array section 120. FIG.

FIG. 2 shows word line driver circuits WDI, WD2, and WD3 of the peripheral circuit section 110 and memory cells 121 (MC11) and 121 (of the memory cell array section 120).
An example of the circuit configuration of MCI 2) is shown.

As shown in FIG. 2, the word line driver circuit M(W
D2) are bipolar transistors Q1, Q2, p-channel MISFET MI, n-channel MISFET M2,
M3 and a diode D1. The bipolar transistors Q1 and Q2 are totem-pole connected to perform push-pull operation. In addition, the second
In the figure, X1 to X3 indicate internal address signals.

The memory cell 121 is connected to the memory cell array section 12.
0, a plurality of them are arranged in a matrix in the row and column directions. Each memory cell 121 has a word I! for selecting a predetermined memory cell 121 from a plurality of memory cells 121. It is connected to W, data line, and D. As shown in FIG. 2 and FIG. 3 (plan view corresponding to FIG. 2), the plurality of word lines W1, W2... and the plurality of data IIAD1, Di, D2, D2... , are arranged orthogonally to each other. Although not shown, the complementary data line D is connected to a sense amplifier and an output circuit via a column switch.

The memory cell 121 mainly includes a pair of n-channel MISFETs MII and M whose respective outputs are cross-coupled.
12, these n-channel MI SFET MII, M
Load resistors R11 and R12 having a high resistance value of gigaohms or more are connected in series between the outputs of mD1.12 and the operating voltage (Vcc), and the complementary data mD1. D
The memory cell 121 is composed of n-channel MISFETs M13 and M14 as transfer switches connected between the outputs of the n-channel MISFETs MII and M12, that is, the memory cell 121 is composed of a flip-flop type holding circuit. ing.

FIG. 3 is a plan view partially showing the planar layout of the peripheral circuit section 110 and the memory cell array section 120. As shown in FIG. 3, the peripheral circuit section 1
10 are arranged along the periphery of the memory cell array section 120. The word line driver circuits WD1 to WD6 shown in FIGS. 2 and 3 are inverter circuits, and the fact that their output stage transistors are bipolar transistors is indicated by blacking out the output of the inverter logic symbol. .

FIG. 4 (a plan view showing the overall configuration) is a plan view of a Bi-CMO8-8RAM to which the present invention is applied.

As shown in Fig. 4D, Bi-CMO5-8RAM10
0 is formed on a single semiconductor substrate 200.

Most of the area of this semiconductor substrate 200 is occupied by the memory cell array section 120. Each memory cell array section 120 is divided and formed as a plurality of memory mats, and each divided memory cell array section 120
The peripheral circuit section 110 is arranged around the .

Furthermore, a plurality of terminal pads (ponding pads) 101 are arranged outside the peripheral circuit section 110 for input/output with an external interface.

The peripheral circuit section 110 mainly includes a word line decoder and driver section 111, a data line decoder and selection switch section 112, and a data line pull-up circuit section 113. Although not shown, the terminal pad 1
An input/output circuit (I10 circuit) corresponding to each terminal pad 101 is arranged between I10 and the peripheral circuit section 110. In this way, B
By using a logic circuit with an i-CMO5 configuration, S
It is possible to achieve high speed RAM and low power consumption at the same time.

[Example I] Next, the specific configuration of the peripheral circuit section 110 and memory cell array section 120 of the Bi-CMOS-5RAM of Example I of the present invention will be explained using FIG. 1 (a sectional view of the main part). do.

First, the configuration of the peripheral circuit section 110 will be explained.

As shown in FIG. 1, in the peripheral circuit section 110,
A bipolar transistor Q is provided on the p-type semiconductor substrate 1.
1. P-channel MISFET MI and n-channel MIS
FETM2 are provided respectively.

The bipolar transistor Q1 is mainly n.

The emitter region 43 is composed of a type semiconductor region, a base region 28A is composed of a P-type semiconductor region, and a collector region 5A is composed of an n-type semiconductor region (n-type well region). In other words, this bipolar transistor Q1
is a so-called vertical structure npn bipolar transistor.

Furthermore, this bipolar transistor Q1 includes, as a collector region, an n° type buried layer 2A consisting of an n° type semiconductor region for reducing collector series resistance, and an n° type semiconductor region for extracting collector current from the surface. It includes a collector pull-up area 12. In this collector pull-up region 12, an insulating film 26, an interlayer insulating film 35, 44, etc.
A collector electrode 45C is connected through the connection hole provided in the. A wiring 47 is connected to the collector electrode 45C through a connection hole provided in the glabellar insulating film 46.

An emitter extraction electrode 39 is connected to the surface of the emitter region 43 through a connection hole provided in the insulating film 26 and the interlayer insulating film 35. This emitter extraction electrode 39 is made of, for example, a polycrystalline silicon film.

In addition, the emitter electrode 45E is connected to the emitter extraction electrode 39 through a connection hole provided in the glabella insulating film 44.
is connected.

The base region 28A includes a base extraction layer (graft base layer) 34B made of a p' type semiconductor region for improving ohmic connection with the base electrode 45B. A base electrode 45B is connected to this base extraction layer 34B through a connection hole provided in the Mi film 26 and the interlayer insulating film 35.44.

Note that the bipolar transistor Q1 includes n-type impurities and p-type impurities, respectively, in the n-type epitaxial layer 4 made of single crystal silicon grown on the p-type semiconductor substrate 1, as will be described in detail later. It is formed by selectively introducing . Further, the bipolar transistor Q″,
is surrounded by an isolation region mainly consisting of a field insulating film 8, a p-type channel stopper region 7, a p-type semiconductor region (n-type well region) 6B, and a p°-type buried layer 3B, Other active elements (e.g. n-channel MISFET M2, P-channel MISFET M1)
etc.) and are electrically insulated.

The collector electrode 45C, emitter electrode 45E, base electrode 45B, and wiring 47 are each made of, for example, an aluminum film or an aluminum alloy film to which impurities such as copper (Cu) and silicon (Si) are added. .

The P-channel MISFET MI is provided on the main surface of the n-type semiconductor region (n-type well region) 5B formed in the n-type epitaxial layer 4. This P-channel MISFET MI mainly consists of a gate electrode 18A made of a laminated film of a polycrystalline silicon film 16A containing n-type impurities and a high melting point silicide metal film 16B, and a heavily doped source region and drain region made of P'-type semiconductor regions. 34A and a gate insulating film 13. This p channel M
The ISFETM1 further includes a low concentration source region and a drain region 24 made of a p-type semiconductor region having a lower impurity concentration than the high concentration source region and drain region 34A, and has a so-called LDD structure. Furthermore, the n
Between the type well region 5B and the p-type semiconductor substrate 1, there is an
A type buried layer 2B is provided.

The upper surface of the gate electrode 18A is covered with an insulating film 17. Furthermore, a sidewall spacer 25 made of, for example, a silicon oxide film is provided on the sidewall of the gate electrode 18A. This sidewall spacer 25 is provided to ensure a distance between the sidewall of the gate electrode 18A and the highly doped source and drain regions 34A. Further, the insulating film 26 and the glabella insulating film 3 are provided in the high concentration source region and drain region 34A.
The source electrode 45 is connected through the connection hole provided in 5.44.
S and drain electrode 45D are connected to each other. These source electrode 45S and drain electrode 45D are formed in the same process as the emitter electrode 45E, base electrode 45B, and collector electrode 45C, respectively.

The n-channel MISFET M2 is provided on the main surface of the p-type semiconductor region (n-type well region) 6A formed in the n-type epitaxial layer 4.

This n-channel MISFET M2 mainly includes a gate electrode 18B made of a laminated film of a polycrystalline silicon film 16A and a refractory metal silicide film 16B similar to the p-channel MISFET MI, a high concentration source region made of an n' type semiconductor region, and a high concentration source region made of an n' type semiconductor region. It is composed of a drain region 31A and a gate insulating film 13, respectively. Furthermore, this n-channel MISFET
M2 includes a low concentration source region and a drain region 21A made of n-type semiconductor regions, and has a so-called LDD structure. Further, a p-type buried layer 3A is provided between the n-type well region 6A and the p-type semiconductor substrate 1 to reduce the resistance value of the n-type well region 6A. In the source region and drain region 31A, the P
Similarly to the channel MISFET MI, the source electrode 45S
, and drain electrode 45D are connected to each other.

The p-channel MISFET MI and n-channel MIS
Each of the FETMs 2 has a pn junction formed by a double well structure (n-type well region 5B, n-type well region 6A), a field insulating film 8, and a channel stopper region 7.
electrically isolated from each other, and further includes the p-type buried layer 3.
By employing the A and n-type buried layers 2B, the latch-up phenomenon is prevented.

In this way, the peripheral circuit section 110 has B x -CM
It consists of an OS. In addition, in FIG. 1, the second
Bipolar transistor Q1, P channel MI S FETMI, and n
Although only the channel MISFET M2 is shown, the word line driver circuit WD1. It goes without saying that the WD3 and the like have the same structure as shown in FIG. Further, the Bi-CMO8 structure shown in FIG. 1 can be used to construct various circuits such as bipolar logic gates such as ECL and CMOS inverters.

Next, the memory cell array section! The configuration of 20 will be explained.

In the memory cell array section 120, memory cells (
n as a transfer switch that constitutes MCII)
A channel MISFET M13 and an n-channel MISFET M12 as a drive MO8FET are provided.

The n-channel MISFET M13 mainly has a gate electrode 1 made of a polycrystalline silicon film 16A and a high melting point metal silicide film 16B similar to the n-channel MISFET M2.
It is composed of a highly doped source region and a drain region 31B made of 8C, n'' type semiconductor regions, and a gate insulating film 13.Furthermore, this n-channel MISFET M13
includes a low concentration source region and a drain region 21B made of n-type semiconductor regions, and has a so-called LDD structure.

The n-channel MISFET M12 has a gate electrode 18D made of a polycrystalline silicon film 16A and a high melting point metal silicide film 16B, similar to the n-channel MISFET M13.
, a highly doped source region and a drain region made of n-type semiconductor regions (not shown), and a gate insulating film 13. Furthermore, this n-channel MISFET MI2
includes a low concentration source region and a drain region made of n-type semiconductor regions (not shown), and has a so-called LDD structure.

A high resistance load element (R11) 40A made of a polycrystalline silicon film is electrically connected to one of the source region and drain region 31B of the n-channel MISFET M13 through a contact hole provided in the insulating film 26 and the interlayer insulating film 35. It is connected to the. This connection is made via a wiring 40B formed by doping a high concentration of n-type impurity into a polycrystalline silicon film formed integrally with one end side of the polycrystalline silicon film constituting the high resistance load element 4OA. It is done. Also,
The wiring 40 is on the other end side of the high resistance load element 40A.
A wiring 40B formed in the same process as wiring 40B is formed.

A power supply voltage (Vcc) is connected to the wiring 40B on the other end side. Further, the source region and drain region 31B
A gate electrode 18D of the n-channel MISFET M12 is electrically connected to one side of the gate electrode 18D via a go-type semiconductor region 15. In this way, the n-channel MI SFET
The source region, drain region 31B, and n° type semiconductor region 15 of MI 3 constitute one storage node of the memory cell (MCII).

In addition, the other of the source region and drain region 31B of the n-channel MISFET M13 is coated with an aluminum film formed in the first layer wiring process or with copper (C
u) An electrode 45 made of an aluminum alloy film doped with impurities such as silicon (Si) is connected to the insulating film 261 through a connection hole provided in the interlayer insulating film 35.44. Further, the electrode 45 is disposed on the interlayer insulating film 44.
The word line shunt wiring 45 (
W 1 ), and the ground voltage Vss, which is the operating voltage of the circuit.
A power supply wiring 45 (Vss) for supplying power (for example, OV) is formed.

The electrode 45 connected to one of the high-concentration source region and drain region 31B is made of an aluminum film or an aluminum film formed in the second layer wiring formation step.
), a wiring 47 (data &! DI) made of an aluminum alloy film doped with impurities such as silicon (Si) is connected through a connection hole provided in the glabella insulating film 44.

Although an example has been shown in which the word line shunt wiring (Wl) is formed by the negative layer wiring 45 and the data &1 (DI) is formed by the second layer wiring 47, conversely, the data line (Wl) is formed by the second layer wiring 47.
Dl) may be formed by the first layer wiring 45, and the word line shunt wiring (Wl) may be formed by the second layer wiring 47.

In addition, in FIG. 1, only the n-channel MI SFET MI 2 and high-resistance load element R11 constituting the memory cell (MC11) are shown, but the n-channel MISFETs M13, M14 and the high-resistance load element shown in FIG. R1
2 also has a configuration similar to that shown in FIG.

Furthermore, the p-type well region 6A of the memory cell array section 120
The p-type buried layer 3A provided under the p-type semiconductor substrate 1 acts as a potential barrier for minority carriers generated in the p-type semiconductor substrate 1 by, for example, α rays. In other words, this p° type buried layer 3A has a function of preventing a so-called soft error in which minority carriers reach the storage node of a memory cell and destroy information.

Further, an @edge film 48 which is a final passivation film is provided on the upper layer of the wiring layer 47 formed in the step of forming the second layer wiring.

Next, a method for manufacturing the Bi-CMOS-3RAM shown in FIG. 1 will be described with reference to FIGS. 5 to 19 (cross-sectional views of main parts shown for each manufacturing process).

First, a P' type semiconductor substrate 1 made of single crystal silicon is prepared. The resistance value of this p-type semiconductor substrate 1 is, for example, about 8 to 12 [Ωanl].

Next, bipolar transistor Q1 and p-channel MI
In the formation region of SFETMI, n-type impurities are selectively introduced into the main surface of the p-type semiconductor substrate 1. In the introduction of this n-type impurity, for example, the impurity concentration is 1015
[Use about 2 atoms/■ of antimony (sb).

Next, the n-channel MISFETs M2, M13, and M1
In the formation region 2 and the element isolation region, n-type impurities are selectively introduced into the main surface portion of the P′ type semiconductor substrate 1. In the introduction of this P-type impurity, for example, boron (B) with an impurity concentration of about 10" [atoms/cm2
use.

Next, heat treatment is performed to diffuse each of the introduced n-type impurities and n-type impurities into the p-type semiconductor substrate 1, forming the n°-type buried layers 2A, 2B and the p-type buried layer 3A.
, 3B.

Next, an n-type epitaxial layer 4 is grown on the main surface of the p-type semiconductor substrate 1. This n-type epitaxial layer 4 is made of single crystal silicon.

The resistance value of this n° type epitaxial layer 4 is, for example, 3
It is about [Ω■]. This n-type epitaxial layer 4 is formed to have a thickness of, for example, about 1.2 [μm].

By growing this n-type epitaxial layer 4, the n-type impurities in the n-type buried layers 2A and 2B and the n-type impurities in the p-type buried layers 3A and 3B are converted to Since it diffuses into the lower part of the n-type epitaxial layer 4, the interface between the n-type epitaxial layer 4 and the p-type semiconductor substrate 1 is formed at the position indicated by the dashed line La, +1 in FIG. Also.

The upper surface of this n-type epitaxial layer 4 is formed at a position indicated by the dashed-dotted line . . . 2 in FIG.

Next, bipolar transistor Q1 and p-channel M
In the region forming I S F E T M 1,
An n-type impurity is selectively introduced into the main surface of the n-type epitaxial layer 4. In introducing this n-type impurity, for example, phosphorus (P) having an impurity concentration of about 10'' [atoms/an2] is introduced by an ion implantation method with an acceleration energy of about 120 to 130 [keV].

Next, the n-channel MISFET M2,M ], 3,M
In the 12 formation regions and isolation regions,
P-type impurities are selectively introduced into the main surface portion of the n~-type epitaxial layer 4. In introducing this n-type impurity, for example, boron fluoride (BF2) with an impurity concentration of about 10'' [atoms/ω2] is heated at 50 to 70 [keV].
It is introduced by ion implantation method with acceleration energy of about 100%. Further, when boron (B) is used as the P-type impurity, the acceleration energy is set to, for example, 10 to 14 [keV-
].

Next, a high-temperature thermal diffusion treatment is performed to stretch and spread the n-type impurity introduced into the n-type epitaxial layer 4 and the n-type impurity into the n-type epitaxial layer 4. , n-type semiconductor region (n-type well region) 5
A, 5B, and n-type semiconductor region (p-type well region) 6A
, 6B. This thermal diffusion treatment, for example,
Approximately 2
Perform for 00 minutes.

The n-type well region 5A is a bipolar transistor Q.
1 is used as an intrinsic collector area.

In addition, the p-type well I as an isolation region
The region 6B is the upper surface L'i of the n-type epitaxial layer 4.
, 12 downwardly, and is formed so as to be in contact with the upper surface of the P'' type buried layer 3B.

The n-type semiconductor regions 5A and 5B are electrically isolated from each other by the n-type semiconductor region 6B and the p-type buried layer 3B.

Next, a silicon oxide film 9 is formed on the main surface of the above-mentioned "type epitaxial layer 4. This silicon oxide film 9 is formed by, for example, thermally oxidizing the upper surface of the above-mentioned "type epitaxial layer 4".
It is formed with a film thickness of about 0 [nm].

Next, an oxidation-resistant mask such as a silicon nitride film is selectively formed on the n-type epitaxial layer 4 in the respective formation regions of the bipolar transistor Q1, p-channel MISFET M1, n-channel MISFET M13 and M12.

Next, the surfaces of the n-type well regions 5A and 5B are covered with, for example, a photoresist film, and boron fluoride (Bpz)
is introduced using a low acceleration energy ion implantation method. At this time, since boron (B) does not pass through the photoresist film and the oxidation-resistant mask, P-type impurities are selectively introduced into the inactive regions (isolation regions) of the P-type well regions 6A and 6B. , a channel stopper region 7 is formed. In this ion implantation step, for example, boron fluoride (BF2) having an impurity concentration of about 7×10 ” [atoms/c+n2] is introduced by an ion implantation method with an acceleration energy of about 40 [keV].

Next, the main surface of the n'' type epitaxial layer 4 exposed from the oxidation-resistant mask is thermally oxidized to form a field insulating film 8 made of a silicon oxide film. The field insulating film 8 and the channel stopper region 7 are formed by a steam oxidation method at a high temperature of about 500° C.] and have a film thickness of about 500 [ro++].
1, P channel MISFETMI, n channel MISF
Looking at the formation regions of ETMI3 and M12 in a plan view,
It is formed so as to surround the formation regions of these elements, and prevents the generation of parasitic channels etc. between the formation regions of each element. After forming the field insulating film 8, the oxidation-resistant mask is removed.

Through the above steps, Bi-CMO8-5 shown in FIG.
Semiconductor substrate 200 as a base on which RAM is to be formed
(The p-type semiconductor substrate 1 and the n-type epitaxial layer 4
) will be completed.

Next, a mask 10 is formed on the semiconductor substrate 200, in which a part of the formation region of the piebolad transistor Q1 is opened. This mask 10 is used as a mask when introducing impurities, and is formed of a photoresist film formed by, for example, photolithography. Thereafter, as shown in FIG. 6, using the mask 10 as a mask for impurity introduction, the silicon oxide film 9 is passed through the n-type well region S.
During A.

An n-type impurity 11 is introduced. In the introduction of this n-type impurity 11, the impurity concentration is, for example, 10゛5 to 10゛6 [a
About 2 toms/an of phosphorus (P), 80 [k
It is introduced using an ion implantation method with an acceleration energy of about eV.

After introducing this n-type impurity 11, the mask 10 is removed. Thereafter, for example, by performing heat treatment at a high temperature of about 1000[° C.] for about 30 minutes, the collector pull-up region 12 made of a d-type semiconductor region is formed so as to be in contact with the n°-type buried layer 2A. Form. Although not shown, after this, in order to completely remove the remaining oxidation-resistant mask, the silicon oxide film 9 on the active region is removed using a wet etching solution, and the film thickness is reduced to 30 [nm1].
A so-called sacrificial thermal oxide film of approximately 850 ['C] is formed using a steam oxidation method at a high temperature of approximately 850['C].

Next, the main surface portion of the n-type well region 5B in the formation region of the p-channel MISFET MI and the n-channel MISFET
2. Into the main surface of the p-type well region 6A in the region where M12 and M13 are formed, an impurity for adjusting the threshold voltage th is introduced. In the introduction of impurities for threshold voltage adjustment, for example, the impurity concentration is 2×1012 [atoms/an
"About 1 boron fluoride (BF2) at 60 [keV]
The impurity concentration is 3X 1011 [atoms/cm2].
A certain amount of phosphorus (P) is introduced by ion implantation with an acceleration energy of about 150 [KeV]. By introducing this impurity for threshold voltage adjustment, n-channel MI
The threshold voltage of each of SFETM2, M13, and M12 is adjusted to, for example, about 0.5 [V]. Also,
The threshold voltage of the p-channel MISFET MI is adjusted to about -0.5 [V], for example.

Next, the sacrificial thermal oxide film is removed to expose the main surfaces of the n-type well regions 5A, 5B and the p-type well regions 6A, 6B.

Next, a gate insulating film 1 is placed on the main surfaces of the exposed n-type well regions 5A, 5B and p-type well regions 6A, 6B.
form 3. This gate insulating film 13 is, for example, 80
It is formed by a steam oxidation method at a high temperature with a diameter of about 0 to 900 [C], and a film thickness of about 15 to 20 [C].

Next, using photolithography technology, the n-channel MI
An etching mask 14 made of a photoresist film is formed in which a part of the region where the SFET MI 3 is to be formed is opened. Next, using the etching mask 14, the gate insulating film 13 is partially removed by etching using, for example, a mixed solution of hydrofluoric acid and ammonium fluoride, and as shown in FIG. form. After this, the etching mask 14 is removed.

Next, a polycrystalline silicon film 16 is formed over the entire surface of the semiconductor substrate 200 including the gaiter m film 13 and the field insulating film 8.
Form A. This polycrystalline silicon film 16A is made of, for example, CV
The film is deposited using the D method to have a film thickness of about 100 to 150 [nm]. An n-type impurity, such as phosphorus (P), which reduces the resistance value, is introduced into the polycrystalline silicon film 16A by a thermal diffusion method.

Next, a high melting point metal silicide film 16B, for example, a WSi2 film, is formed on the polycrystalline silicon film 16A. This high melting point metal silicide film 16B is deposited by, for example, a CVD method or a sputtering method, and is formed to have a thickness of about 150 [nm]. This refractory metal silicide film 16B and the polycrystalline silicon film 16A are formed as a first layer gate wiring formation step in the manufacturing process.

Next, on the entire surface of the high melting point metal silicide film 16B,
An insulating film 17 is formed. This insulating film 17 is made of, for example, C
Formed with a silicon oxide film deposited by the VD method, with a thickness of 100 to 20
It is formed with a film thickness of about 0 [nm].

Next, the insulating film 17 and the high melting point metal silicide film 16B
, the polycrystalline silicon films 16A are sequentially etched into a predetermined shape to form the gate electrode 18 of the P-channel MISFET MI.
A, gate electrodes 18B, 18C, and 18D of n-channel MISFETs M2, M13, and M12 are formed, respectively. The gate electrode 18C becomes a part of the word line W1. The etching process uses an etching mask (photoresist film) formed by photolithography technology, and is performed using RI.
E (Reactive I on E thing)
This is done using anisotropic etching such as etching.

Next, high temperature heat treatment is performed to densify the high melting point metal silicide film 16B and to recover from etching damage. This heat treatment is performed at, for example, 900 [
℃] for about 30 minutes.

Further, the polycrystalline silicon film 1 constituting the gate electrode 18D
The n-type impurity introduced into 6A is transferred to the p
Heat is diffused into the main surface of the type well region 6A through the opening OPI, and as shown in FIG.
is formed. This n-type semiconductor region 15 and an n-channel MISFET that constitutes a memory cell
The gate electrode 18D of SFETMI2 is the opening ○P.
Connected directly through 1. The n° type semiconductor region 15
is the source region (31B) of the n-channel MISFET M13 to be formed later and the n-channel MISFET M1.
It is formed to electrically connect the second gate electrode 18D.

Next, bipolar transistor Q1 and p-channel MI
A mask 19 is formed to cover the formation region of SFETMI.

This mask 19 is formed of, for example, a photoresist film formed by photolithography technology. After this, the 9th
As shown in the figure, using the mask 19 as a mask for impurity introduction, an n-type impurity 20 is introduced into the main surface of the P-type well region 6A exposed from each of the gate electrodes 118B and 18C118D. In the introduction of this n-type impurity 20,
For example, if the impurity concentration is I x 1013 to 2 x 1
013 [atoms/an About 2 phosphorus (P), 5
It is introduced by an ion implantation method with an acceleration energy of about 0 [keV]. This n-type impurity 20 is the gate electrode 18
B, 18C118D are introduced in a self-aligned manner. Since this n-type impurity 20 is introduced at a relatively low impurity concentration, the n-channel MISFETs M2 and M13
, M12 can each have an LDD structure. By introducing this n-type impurity 20, the n-channel MISFETs M2, M13, and M12 consisting of n-type semiconductor regions
The respective low concentration source and drain regions 21A and 2
1B are formed. In addition, n-channel MI SF
The low concentration source and drain regions of ETMI 2 are
It is not shown in the figure for clarity. Further, the junction depth of each of the low concentration source and drain regions 21A and 21B is, for example, approximately 0.2 [μlI]. After this, the mask 19 is removed.

Next, bipolar transistor Q1 and n-ch MIS
A mask 22 is formed to cover the formation regions of each of FETM2, M13, and M12. This mask 22 is formed, for example, from a photoresist film formed by photolithography.

Next, as shown in FIG. 10, using the mask 22 as a mask for impurity introduction, a p-type impurity 23 is introduced into the main surface of the n-type well region 5B exposed from the gate electrode 18A, and the p-channel MISFET M1 A low concentration source region and drain region 24 are formed. This p-type impurity 23
In the introduction of, for example, boron fluoride (BF2) with an impurity concentration of about I x 10" to 2 x 10" [atoms/cI12] is introduced by an ion implantation method with an acceleration energy of about 40 [:keV]. . This p-type impurity 23 is introduced into the gate electrode 18A in a self-aligned manner. By forming the low concentration source and drain regions 24, the P-channel MISFE
The TMI can have an LDD structure. Further, the diffusion depth of each of the low concentration source region and drain region 24 is formed to be, for example, about 0.2 [μm]. After this, the mask 22 is removed.

Next, as shown in FIG. 11, the gate electrode 18A,
Sidewall spacers 25 are formed on each sidewall of 18B, 18C, and 18D. This sidewall spacer 25 is formed by depositing a silicon oxide film on the entire surface of the semiconductor substrate 200, and then performing anisotropic etching such as RIE by an amount corresponding to the thickness of the deposited silicon oxide film. . The silicon oxide film constituting this sidewall spacer 25 is formed, for example, by a CVD method using inorganic silane gas and nitrogen oxide gas as source gases. This silicon oxide film is formed to have a thickness of, for example, 300 to 400 [nm]. The gate length direction of this sidewall spacer 25 (
The length (in the channel length direction) is, for example, 250 to 300
[It is formed to a size of about 100 nm.

Further, due to the anisotropic etching, the gate electrode 1
A portion of the gate insulating film 13 exposed from each of 8A, 18B, and 18C118D and the bipolar transistor Q1
The gate insulating film 13 in the formation region is overetched and removed. At this time, the main surfaces of the n-type well region 5A and the p-type well region 6A, which are the underlying layers of the gate #4A edge film 13, are also etched by a small amount. After forming the sidewall spacers, inert gas (e.g. argon (
Heat treatment is performed in an Ar) gas atmosphere at a temperature of approximately 800°C.

By this heat treatment, the side wall spacer 25
At the same time, the silicon oxide film constituting the n-type well regions 5A, 5B is densified, the low-concentration source and drain regions 21A, 21B, and 24 are activated, and the silicon layer (main surface portions of the n-type well regions 5A, 5B) is removed by the overetching. , and the main surface portions of p-type well regions 6A and 6B).

Next, an insulating film 26 is formed on each of the surfaces of the n-type well region 5A and the p-type well region 6A exposed by the anisotropic etching to form the sidewall spacer 25. This insulating film 26 is formed of, for example, a silicon oxide film formed by a thermal oxidation method.

Next, as shown in FIG. 12, the n-type well region 5A is
P-type impurities 27 are introduced into the main surfaces of 5B and p-type well regions 6A and 6B.

In the introduction of this p-type impurity 27, for example, the impurity concentration is 3 x 1013 to 4 x 1013 [atoms/
am”) of boron (B) at 10 to 20 [keV]
It can be introduced by ion implantation method with acceleration energy of about
Alternatively, boron fluoride (BF2) is introduced by ion implantation with an acceleration energy of about 60 [KeV]. By introducing this p-type impurity 27, a base region 28A of bipolar transistor Q1 is formed. The junction depth of this base region 28A is, for example, 0.15 to 0.
It is formed as shallow as about 2 [μl]. The junction depth (X, ,
) are the highly doped source and drain regions 3 of the MISFET shown in FIG. 1 in the conventional Bi-CMO8.
It was formed deeper than the junction depth (X jKs, .) of 4A (p'), 31A (n''), and 31B (n').

Due to the proportional reduction side, the base region was becoming shallower, but the relationship was always x3I(s, HD>X,B+.However, the Bi-CM of this example
In O8, X jKs, i. By setting the relationship ≧xjB, the junction depth XjE of the base region 28A is further made shallower. Further, the p-type impurity 27 is a P-channel M
ISFET MI and n-channel MISFET M2, M2
It is also introduced into each formation region of S, and the p-type semiconductor region 28
B, 28C128D are temporarily formed. Therefore, in particular, part of the n-type low concentration source and drain regions 21A and 21B of the n-channel MISFETs M2 and M2S is inverted to the P-type. In addition, n channel M
A p-type semiconductor region is also formed in the formation region of ISFETM12, but it is not shown. However, since the sidewall spacer 25 substantially serves as a mask when introducing the P-type impurity 27, the n-channel MISFET M2
, M2S, M12 (alleviation of electric field concentration near the drain region) is substantially affected by the p-type impurity 27 in the low concentration source region and drain region 2LA, 21B under the side wall spacer 25. will not be introduced. Furthermore, the p-type semiconductor region 28C12 which is the inversion layer
Each of the 8Ds will be converted into an n-channel MISFET in a later process.
2. High concentration (
The n-channel MISFET M2.M2S, M
It does not affect the electrical characteristics of 12 in any way. Also,
The low concentration source region and drain region 24 of the n-channel MISFET MI also
2. Similarly to M2S and M12, the low concentration source region and drain region 24 under the sidewall spacer 25
Since the p-type impurity 27 is not introduced into the p-channel MISFET M1, there is no adverse effect on the electrical characteristics of the p-channel MISFET M1.

As described above, according to the present embodiment (2), the base region 28A of the bipolar transistor Q1 is formed by the step of introducing the impurity 27 without using a mask, so that the number of exposure masks for photolithography and the use of the exposure mask can be reduced. Since the process of forming a photoresist film on the conductor substrate 200 can be reduced, the process cost of a semiconductor integrated circuit device having a bipolar transistor can be reduced.

In addition, the base region 28A of the bipolar transistor Q1
By forming the low-concentration source region and drain region 24 of the p-channel MISFET MI in separate impurity introduction steps, the junction depths of the base region 28A, the low-concentration source region, and the drain region 24 can be reduced. In addition, the impurity concentration can be set to an optimum value, and the process cost does not increase due to the increase in the number of exposure masks due to the separate steps of introducing the impurities 23 and 27.

Therefore, the impurity concentration of the base region 28A of the bipolar transistor Q1 can be increased without increasing the process cost, so that the speed of the bipolar transistor Q1 can be increased, and the P-channel MISFET
Since the impurity concentration of the low concentration source region and drain region 24 of the MMI can be set as low as possible, L
The electrical reliability of the DD structure p-channel MISFET MI can be improved.

Furthermore, in the Bi-CMO 5 of Example I, after forming the sidewall spacer 25 when forming the CMO 5 with the LDD structure, the step of introducing the impurity 27 for forming the base region 28 of the bipolar transistor Q1 was performed. There is. Therefore, the silicon layer on the surface of the base region 28A (the surface of the n-type well region 5A) is shaved off by the over-etching process when forming the sidewall spacer 25, so that the effective base region 28A is
can prevent the impurity concentration from decreasing. Since the reduction in the impurity concentration of the base region 28A due to the over-etching becomes more noticeable as the base region 28A becomes shallower, the manufacturing method of this embodiment I is suitable for manufacturing Bi-CMOS having a base region with a shallower junction. It is very advantageous for

Further, according to the inventor's study, in the Bi-CMOS manufacturing process, the gate insulating film 13. Gate electrode 18
After forming each of A, 18B, and 18C118D, photolithography was used to form a film with a relatively low impurity concentration (
For example, even with ion implantation of 1013~[atoms/■2], the surface of the photoresist film is charged with a negative charge, and this negative charge flows into the predetermined gate electrodes 18A'-18B and 18C118D. The gate electrodes 18A, 18B, 18C, 18D
It has been found that there is a mechanism in which the gate insulating film 13 formed under the gate insulating film 13 is destroyed by electrostatic discharge. This phenomenon is well known in conventional devices when ions are implanted with high impurity concentrations (for example, around 10" to 10"[atoms/am"]), and various countermeasures such as modifying the layout pattern have been implemented. However, this phenomenon started to occur with low-concentration ion implantation equipment in devices with a diameter of 1.3 [μm] or later, and the scaling law requires that the thickness of the gate insulating film be reduced to approximately 5 μm.
[This became noticeable after it started to be formed below n+sl. This mechanism will be explained using FIG. 20 (a plan view of the main part) and FIG. 21 (a plan view of the main part taken along the line X--X in FIG. 20).

FIG. 20 shows an example of a planar layout of a semiconductor region having a relatively high impurity concentration, such as a base region 28A, of each of the n-channel MISFET M2, the p-channel MISFET MI, and the bipolar transistor Q1.

As shown in FIG. 20, a pattern of field insulating film 8 is formed on the semiconductor substrate 200 so as to surround the formation region of each element. Further, on the semiconductor substrate 200, an n-channel MISFET M2 consisting of a gate electrode 18B, a gate insulating film (not shown), a low concentration source region and a drain region 21A, and a gate electrode 18A are provided.
, a p-channel MISF consisting of a gate insulating film (not shown), a low concentration source region, and a drain region 24, respectively.
The ETM1 and the n-type well region 5A in which a diffusion layer such as the base region 28A is to be formed are arranged close to each other. Gate voltage 18 of the n-channel MrSFETM2
B and gate electrode 18A of p-channel MISFET MI
It is formed integrally with. In this way, when the element formation regions are laid out close to each other, for example, the P-type impurity 27 is introduced into the n-type well region 5A using a photoresist film PR formed by photolithography. When ions are implanted, the surface of the photoresist film PR is charged with a negative charge (e) as shown in FIG. 21, and the negative charge (θ)
For example, as shown by the arrow in FIG.
There is a problem that the gate insulating film 13 formed under A is damaged by electrostatic discharge.

In order to prevent such problems, the pattern of the gate electrode of the MISFET and the pattern of the diffusion layer such as the base region must be separated by taking into account the shift of the photoresist mask due to mask misalignment, etc. As a result, the degree of integration of the semiconductor integrated circuit device decreases. However, according to the present embodiment I, the base region 28
Since A is formed by ion implantation of the impurity 27 without using photolithography technology (without using photoresist film PR), there is no problem of electrostatic damage. Therefore, high integration of Bi-CMOS can be achieved, and the electrical reliability of MISFET can be improved.

Next, the method for manufacturing the BBl-CMOS-5RA of Example I will be explained.

After forming the base region 28A, the base region 28A of the bipolar transistor Q1 and the p-channel MISF are formed.
The ETMI formation region is covered with a mask 29 made of a photoresist film formed by photolithography. next,
As shown in FIG. 13, using this mask 29 as a mask for introducing impurities, an n-type impurity 30 is introduced into the p-type well region 6.
Introduce it to the main surface of A. This n-type impurity 30 is mainly
It is introduced in a self-aligned manner with respect to the gate electrodes 18B, 18C118D and the sidewall spacers 25. In the introduction of the n-type impurity 30, for example, the impurity concentration is 1o1S.
Arsenic (A s) of about IQ 1' [atoms/an 2] is introduced by an ion implantation method with an acceleration energy of about 80 [keV]. By introducing this n-type impurity 30, high-concentration source and drain regions 31A and 31B of the n-channel MISFETs M2, M13 and M12 are respectively formed on the main surface of the n-type well region 6A. After this, the mask 29 is removed.

By introducing the n-type impurity 30, the twelfth
P-type semiconductor region 28C128D which is an inversion layer shown in the figure
Since the p-type impurity therein is compensated, each of the P-type semiconductor regions 28C and 128D substantially disappears.

Next, a mask 32 is formed in which the formation region of the P-channel MISFET MI and a portion of the base region 28A of the bipolar transistor Q1 are opened. This mask 32 is formed, for example, from a photoresist film formed by photolithography technology. Thereafter, as shown in FIG. 14, using the mask 30 as a mask for impurity introduction, n-type impurities 33 are introduced into the main surfaces of each of the n-type well regions 5A and 5B. In the introduction of this n-type impurity 33, the impurity concentration is, for example, 101s to 101r'' [atoms/
boron fluoride (BFZ) of about 80[an 2]
It is introduced by an ion implantation method with an acceleration energy of about [keV]. By introducing this n-type impurity 33, high concentration source and drain regions 34A of the P-channel MISFET MI are formed, and a base extraction layer (graft base layer) 34B of the bipolar transistor Q1 is formed. After this, the mask 32 is removed.

Next, heat treatment is performed to recover damage caused by ion implantation and to activate each of the introduced n-type impurity 30 and P-type impurity 33. This heat treatment is performed, for example, at a temperature of about 850 to 900['C] for about 10 minutes. Note that the high concentration source region and drain region 31A are formed to have a junction depth of, for example, 0°2 to 0.25 [μm]. Also.

The high concentration source region, drain region 34A, and base extraction layer 34B have a thickness of, for example, 0.25 to 0°3 [μ
m]. By forming (activating) each of the highly doped source and drain regions 34A and 34B, an n-channel MISFE with an LDD structure is formed.
TM2, M13, M12, and P-channel MISFET
Each of the MIs is substantially completed.

Next, an interlayer insulating film 35 is formed over the entire main surface of the semiconductor substrate 200. Thereafter, a mask 36 is formed using a photoresist film formed by photolithography. Openings are formed in this mask 36 in the region where the emitter region (43) of the bipolar transistor Q1 is formed and the region to which the high resistance load element (R11) forming the memory cell is connected.

The interlayer insulating film 35 is formed of, for example, a silicon oxide film deposited by the CVD method, and is formed to have a thickness of about 200 to 300 [μm].

Next, as shown in FIG. 15, using the mask 36 as an etching mask, the interlayer insulating film 35 and the insulating film 26 under the glabellar insulating film 35 are sequentially etched to form openings ○P2 and ○P3, respectively. form.

This etching is performed, for example, by anisotropic etching such as RIE. After this, the mask 36 is removed.

Next, a polycrystalline silicon film 37 is formed on the interlayer insulating film 35 including each of the openings ○P2 and ○P3. This polycrystalline silicon film 37 is deposited by, for example, the CVD method, and
It is formed with a film thickness of about [nm].

Next, as shown in FIG. 16, a mask 38 made of a photoresist film is formed by photolithography.

This mask 38 includes the emitter extraction electrode (39) of the bipolar transistor Q1 and the high resistance load element (40A).
8 Next, using the mask 38 as an etching mask, the polycrystalline silicon film 37 exposed from this mask 38 is covered. Remove by etching. This etching is performed, for example, by anisotropic etching such as RIE. By performing this etching, the emitter extraction electrode 39, high resistance load element 4OA
and wiring 40B integrally formed with this high resistance load element 40A.

Next, a mask 41 that covers only the high resistance load element 40A
form ′. This mask 41 is formed, for example, from a photoresist film formed by photolithography.

Next, the mask 41 is used as a mask for introducing impurities,
The n-type impurity 42 is integrated into the wiring 4 with the emitter extraction electrode 39 and the high resistance load element 40A.
0B. In the introduction of this n-type impurity 42, the impurity concentration is, for example, 1 x 1015 to 2 x 10
” [About 2 atoms/an of arsenic (As),
It is introduced by ion implantation with an acceleration energy of about 80 [keV]. By introducing this n-type impurity 42, the resistance values of the emitter extraction electrode 39 and the wiring 40B are reduced. Also, n-channel MISFE
An ohmic connection can be made between one of the high concentration source region and drain region 31B of TM12 and the wiring 40B. After this, the mask 41 is removed.

Next, the bipolar transistor Q1 and MISFE
A glabellar insulating film 44 is formed over the entire surface of the semiconductor substrate 200 including the formation regions of TMI, M2, M13, and M12. This glabellar insulating film 44 is made of, for example, a silicon oxide film, EP
S G (Boron Phospho S 1
It is formed of a two-layered laminated film in which each of the LicateGlass films is sequentially laminated. The silicon oxide film below the interlayer insulating film 44 is deposited, for example, by a CVD method using silane gas and nitrogen oxide gas as source gases. This silicon oxide film is made of, for example, 1
The film thickness is approximately 00 to 150 [rtm]. The upper layer BPSG film is deposited, for example, by a CVD method.

This BPSG film has a thickness of, for example, 300 to 500 [nm]
Formed with a film thickness of This BPSG film is subjected to a densification process at a temperature of about 900 [''C] in a nitrogen gas atmosphere.

Next, using photolithography technology and etching technology, the interlayer insulating film 44, 35 and the insulating film 26 are selectively etched in order, and the collector lifting region 12,
Base extraction layer 34B, emitter extraction electrode 39, high concentration source region, drain region 34A, 31A, 31
Connecting holes THI reaching each of B are configured. This connection hole THI is formed, for example, by a combination of isotropic etching and anisotropic etching.

Formed in a tapered or stepped shape. Further, this connection hole THI may be formed only by anisotropic etching.

Next, 950 ['
A heat treatment is performed for about 10 minutes at a temperature of about C] to reflow and planarize the BPSG layer above the interlayer insulating film 14. The mixed gas at this time slightly oxidizes the interface in the connection hole THI, and phosphorus (P) diffused from the BPSG film.
and boron (B) from entering the interface of the connection hole THI. Further, by this heat treatment, the n-type impurity 42 introduced into the emitter extraction electrode 39 is driven-in diffused into the base region 28A through the opening OP2, and the bipolar transistor Q1 shown in FIG. The emitter region 42 is formed with a diffusion depth of, for example, about 0.1 [μm].

By forming this emitter region 42, bipolar transistor Q1 is completed.

Next, as shown in FIG. 18, a collector electrode 45C, a base electrode 45B, an emitter electrode 45E, which are electrically connected to the respective semiconductor regions through the connection hole TH1,
Source and drain electrodes 45S and 45D, an electrode 45, a wiring layer 45 (word shunt wiring Wl) and a wiring layer 45 (power supply wiring gVis) extending over the interlayer insulating film 44 are formed. Each of the electrode and wiring layer 45 is formed of an aluminum alloy film deposited by sputtering, for example, and has a thickness of 400 to 6 degrees. Furthermore, in order to reduce the contact resistance between the electrode 45 and each semiconductor region connected thereto, a platinum silicide film (PtSi film) is provided between the electrode 45 and each semiconductor region.
A silicide metal film such as the like may also be provided. Although not shown, the wiring 45 (word line shunt line Wl) is connected to the gate electrode (word line) of the n-channel MISFET MI3 through connection holes provided at predetermined intervals in the interlayer insulating film 44.35. By reducing the resistance value of the gate electrode (word line) 18C, the read speed of information stored in the memory cell 121 is improved. In other words, the word shunt wiring W1 is connected to the n-channel MISF
It extends along the extending direction of the gate electrode 18G of the ETM 13. FIG. 22 (main part plan view) shows an example of a plan view of the memory cell array section 120 of Example I. The word line shunt wiring W1 extends along the gate electrode 18C (W1) shown in FIG. Further, the cross section taken along the Y-Y line in FIG. 22 corresponds to the memory cell array section 120 in FIG. 13. It goes without saying that in FIG. 22, parts with the same reference numerals as those in FIG. 13 are manufactured in the same manufacturing process and have the same functions.

Further, in FIG. 22, the symbol C0NT indicates a connection portion between the gate electrode 18D and the n-type semiconductor region 15.

Next, the semiconductor substrate 200 including the electrode and wiring 45 is
A glabellar insulating film 46 is formed on the entire surface. This glabellar insulating film 46 is formed of a three-layer structure in which a silicon oxide film (deposited type insulating film), a silicon oxide film (painted type insulating film), and a silicon oxide film (deposited type insulating film) are laminated in sequence. There is.

The lower silicon oxide film is deposited, for example, by plasma CVD to have a thickness of about 150 to 250 nm.

The middle layer silicon oxide film is provided for the purpose of flattening the surface of the interlayer insulating film 46. This middle layer silicon oxide film is coated several times (2 to 5 times) using the SOG method (total 100 coats).
to 150 [apply to a film thickness of about nml], and then,
It is formed by performing a baking process (approximately 450 [°C]). Further, this middle layer silicon oxide film may be formed of, for example, polyimide resin.

The upper silicon oxide film has interlayer lI@! The membrane 46 is provided to increase the strength of the membrane as a whole. This upper layer silicon oxide film is made of, for example, tetraethoxysilane TEO5.
(Tetra Ethoxyl 0rtho 5ila
The film is deposited by a plasma CVD method using ne) to have a film thickness of approximately 500 to 700 nm.

Next, a connection hole TH2 is formed in the interlayer insulating film 46.

The connection hole TH2 is formed into a tapered or stepped shape by a combination of isotropic etching and anisotropic etching, similar to the connection hole THI.

Moreover, this connection hole TH2 may be formed only by anisotropic etching.

After forming the connection hole TH2, heat treatment is performed at a temperature of about 400 [° C.] for about 10 to 20 minutes in order to recover from the damage caused by etching.

Next, as shown in FIG. 19, a wiring 47 is formed extending over the interlayer insulating film 46 so as to be connected to the electrode and wiring 45 through the connection hole TH2. This wiring 47 is formed in the second layer wiring formation process. This wiring 47 is basically formed with the same structure as the electrode and wiring 145. That is, the wiring 47 is formed of an aluminum alloy film deposited by sputtering, for example, and has a thickness of about 800 to 1000 [r+m]. This wiring 47 is processed using photolithography and etching techniques after forming an aluminum alloy film.

After forming the wiring 47, heat treatment is performed to recover damage caused in the etching process for forming the wiring 47. Furthermore, by forming the wiring 47,
The electrode 4 is placed on one of the source region and drain region 31B of the n-channel MISFET M13 constituting the memory cell.
Data line 47 (D 1
＞ is formed. This data line D1 is connected to the word line Wl.
(gate electrode 18C and word shunt line Wl).

Next, as shown in FIG. 1, a passivation film 48 is formed over the entire surface of the semiconductor substrate 200, including on the wiring 47. This passivation film 48 is formed, for example, from a composite film in which a silane film, a silicon nitride film, and a resin film are laminated in sequence. The silane film below this passivation film is formed to have a thickness of, for example, about 600 nm.

The middle layer silicon nitride film is formed for the purpose of improving moisture resistance. The upper resin film is, for example, a polyimide resin film formed by a coating method, and is formed to have a film thickness of about 2 to 3 nm. By forming this resin film, the α-ray soft error withstand voltage of the Bi-0MO8-8RAM can be improved.

By carrying out the above steps, the Bi-CMOS-8 RAM 100 of the present embodiment (2) shown in FIG. 1 is completed.

As explained hereafter, according to the manufacturing method of Example I,
Base region 28A of bipolar transistor Q1, LD
Since the low concentration source region and drain region 24 of the D-structure p-channel MISFET M1 are formed by different impurity introduction processes, the base region 28A,
By setting the respective impurity concentrations of the low-concentration source region and drain region 24 to optimal values, it is possible to increase the speed of Bi-0MO8 and to improve electrical reliability.

Furthermore, since the base region 28A is formed after the sidewall spacer 25 is formed, etching of the semiconductor substrate surface (the surface of the semiconductor region 5A where the base is to be formed) that occurs when the sidewall spacer 25 is formed is a problem. Not. That is, if base region 2
If the formation of the sidewall spacer 8A precedes the formation of the sidewall spacer 25, the surface of the base region 25A will be etched when the sidewall spacer 25 is formed, making it impossible to control the base width with high precision. However, according to this embodiment I, such problems are inevitably solved,
High precision control of base width is possible. Therefore, it is possible to further increase the speed and reliability of the bipolar transistor Q1.

Furthermore, since the source and drain regions 21A, 21B, and 24, which have an impurity concentration lower than that of the base region 28A, are masked by the sidewall spacers 25, new impurities 27 are introduced to form the base region 28A. Formation of a mask for impurity introduction (specifically, a photoresist film) can be omitted. That is, the base region 28A can be formed without using a base impurity introduction mask. Therefore, Bi-CM
It is possible to reduce the O5 process cost. Note that an impurity introduction mask may be used to form the base region 28A if necessary. In this case, there is no need for highly accurate mask pattern processing.

[Embodiment 2] The manufacturing method of Embodiment 2 of the present invention is applicable to the case where the bipolar transistor Q1 is not required to have high speed and the junction depth between the emitter region 43 and the base region 28A may be deep. The p-channel MISFET shown in FIG.
This method omits the step of forming the mask 22 for forming the source region and drain region 24 with a low concentration of I and the step of introducing the p-type impurity 23. A part of the manufacturing process will be explained below.

In the manufacturing method of Example 2, n shown in FIG.
Channel MISFET M2. After the step of forming the low concentration source and drain regions 21A and 21B of M13 and M12, sidewall spacers 25. After each of the edge films 26 is formed, a p-type impurity 27 is introduced into the main surface of each of the n-type well regions 5A, 5B and the p-type well region 6A by ion implantation without using an impurity introduction mask. In this case, the former Me P-type impurity 27 is
A small amount is also diffused into the lower regions 21A and 21B of the sidewall spacers 25 of M2, M13, and M12, but in order to compensate for the reduction in the effective impurity concentration due to this diffusion,
The low concentration source region and drain region 21A, 21B
In addition, in the annealing process for activating the P-type impurity 27 and the n-type impurity (33) introduced in the subsequent process, boron (B) is used. Due to the difference in the diffusion rate between arsenic (As) and arsenic (As) (the diffusion rate of boron (B) is faster than that of arsenic (As)), the diffusion rate of boron (B) is higher than that of arsenic (As). Since the P-type impurity 27 is diffused until the n-channel MISFET M2, M2S, M12
becomes a so-called p-pocket structure. The p-channel M
Low concentration source region and drain region 2 of ISFETM1
8B is formed by the lateral diffusion of the P-type impurity 27, so the p-type impurity concentration is lower than that of the base region 28A of the bipolar transistor Q1 formed at the same time, and therefore the source region and drain region of the p-channel MISFET MI The electric field concentration at 28B can be sufficiently alleviated.

After that, as in Example I, the steps shown in FIGS.
In the process of performing the steps shown in Figure 9, the p-channel MISFE
The TMI essentially has an LDD structure, and the Bi of this embodiment
-CMO5-5RAM is completed.

As explained above, according to the present embodiment (2), process costs can be further reduced than in the above-mentioned embodiment I.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

For example, the present invention provides a pnp bipolar transistor and an M
The present invention can also be applied to a semiconductor integrated circuit device having an ISFET (specifically, an n-channel MISFET).

Further, the present invention provides Bi-CMO3-DRAM, Bi-C
It can also be applied to MO8, gate arrays, etc.

[Effects of the Invention] To briefly explain the effects obtained by the representative inventions disclosed in this application, in the method of manufacturing a semiconductor integrated circuit device having a bipolar transistor and a MISFET as described below, In addition to improving electrical reliability and electrical reliability, it is possible to reduce process costs.

[Brief explanation of drawings]

FIG. 1 shows Bi-CMO5 SRA of Example I of the present invention.
FIG. 2 is a sectional view of the main part of B i-CM OS/S to which the present invention is applied.
3 is a plan view corresponding to the circuit diagram shown in FIG. 2, and FIG. 4 is a Bi-CMO5 SRA to which the present invention is applied.
5 to 19 are plan views showing the overall configuration of the Bi-CMO shown in FIG. 1.
5-Cross-sectional views of essential parts showing each SRAM manufactured. FIG. 20 is a plan view of a main part for specifically explaining the effects of the present invention, FIG. 21 is a sectional view taken along the line X-X in FIG. 20, and FIG. 22 is a memory cell array section. FIG. 23 is a sectional view of a main part showing a part of the manufacturing process of Example 2 of the present invention. In the figure, 1...P-type semiconductor substrate, 2 A, 2 B...
・N゛ type buried layer, 3A, 3B ・P゛ type buried layer, 4...N-type epitaxial layer, 5A, 5B・
... N-type well region, 6A, 6B... N-type well region, 7... Channel stopper region, 8... Field insulating film, 12... Collector pull-up region, 13. Gate insulating film, 15. ...n-type semiconductor region, 16A...
・Polycrystalline silicon film, 16B...High melting point silicide metal film, 17...II! ! , lamina, 18A , 18B , 1
8C, 18D・Gate electrode, 21A, 21B...n-
type low concentration source region, drain region, 24...P- type low concentration source region. Drain region, 25・Side wall spacer, 26・
Insulating film, 31A, 31B...n type high concentration source region,
Drain region, 34A...p type high concentration source region,
Drain region, 34B/base extraction layer, 35, 44.
46...Interlayer insulating film, 39 Emitter extraction electrode,
40A/high resistance load element, 40B...wiring, 43...
Emitter region, 45... Electrode, 47 Wiring, 48...
This is the final passivation film.

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device having a bipolar transistor and a MISFET each having a low concentration source region and a high concentration source region and a drain region of the same conductivity type as the base region of the bipolar transistor. , a step of forming a gate electrode of the MISFET, a step of forming the low concentration source region and a drain region in self-alignment with the gate electrode, and a step of forming sidewall spacers on the sidewalls of the gate electrode. and forming a base region of the bipolar transistor having a higher impurity concentration than the low concentration source region and drain region, and forming a semiconductor region having the same impurity concentration as the base region in a self-aligned manner with respect to the sidewall spacer. 1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: forming the high-concentration source region and drain region in a self-aligned manner with respect to the sidewall spacer. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the base region and the highly doped source and drain regions are formed by an ion implantation method. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the base region is formed by an ion implantation method using lower energy than the highly doped source and drain regions. 4. Claim 1, wherein the base region is formed by introducing impurities without using a photoresist film.
A method for manufacturing a semiconductor integrated circuit device according to . 5. A method for manufacturing a semiconductor integrated circuit device having each of a bipolar transistor and a MISFET having low and high concentration source and drain regions of the same conductivity type as the base region of the bipolar transistor, wherein the gate electrode of the MISFET A step of forming a sidewall spacer on the sidewall of the gate electrode, and introducing impurities without using a mask form the base region of the bipolar transistor, and form the base region of the bipolar transistor under the sidewall spacer. A semiconductor integrated circuit device comprising: forming a high concentration source region and a drain region; and forming the high concentration source region and drain region in a self-aligned manner with respect to the sidewall spacer. manufacturing method. 6. The semiconductor integrated circuit device according to claim 5, wherein the impurity concentration of the low concentration source region and drain region formed under the sidewall spacer is lower than the impurity concentration of the base region. manufacturing method. 7. A method for manufacturing a semiconductor integrated circuit device having a bipolar transistor and a MISFET having the same conductivity type as the base region of the bipolar transistor, including the step of forming a gate electrode of the MISFET and the step of forming an impurity without using a photoresist film. A semiconductor integrated circuit device comprising the step of forming a base region of the bipolar transistor and forming a source region and a drain region of the MISFET in self-alignment with the gate electrode. Production method.