JPH03292762A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve a chip in positional accuracy and to make wirings between a board and a semiconductor chip very small in pitch by a method wherein a semiconductor chip where an element is formed is arranged in a fixing hole provided to a board confronting the surface of the board opposed to its primary surface at a frame. CONSTITUTION:A semiconductor chip 2 is inserted into a tapered hole 4 provided to an Si substrate 1, the upside 2a of the chip is aligned with the underside of a chip aligning frame 9 and fixed with a joining member 3. At this point, the peripheral part of the upside 2a of the chip 2 is aligned with the underside of the chip aligning frame 9, whereby the semiconductor chip 2 can be easily positioned to the Si substrate 1. As the semiconductor chip 2 is arranged coming into close contact with the Si substrate 1, and a flattening layer and a wiring can be easily interposed between the semiconductor chip 2 and the Si substrate 1. The level difference between the upside of the semiconductor chip 2 and the upside of the Si substrate 1 made by the thickness of the chip aligning frame 9 is relaxed by a flattening layer 8, and an element provided to the Si substrate 1 and an element provided to the semiconductor chip 2 are connected together by a thin film wiring 6 through the intermediary of electrodes 5 and 10 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to one that is advantageous for high-density packaging and improved reliability in integration technology.

[Prior Art] In recent years, with the miniaturization of semiconductor chips in hybrid integrated circuit devices, which are a type of semiconductor device, wiring patterns have been improved in order to realize high-speed operation of five high-density packaging circuits, a reduction in the number of contact parts, etc. There is a demand for miniaturization.

For example, in the "semiconductor device" of International Publication No. WO 90101215, we focused on significantly reducing the wiring pitch by improving the positional accuracy of the semiconductor chip, and created tapered fixing holes in the substrate. A device has been disclosed in which a semiconductor chip provided with a tapered portion corresponding to the hole is embedded and bonded to improve chip position accuracy.

[Problem to be solved by the invention]

However, since this device has a tapered part on the semiconductor chip side in order to correspond to the tapered fixing hole provided on the substrate side, the lateral area of the main surface of the semiconductor chip on which active elements etc. are formed is reduced. Due to restrictions, there is a problem in that the semiconductor chip cannot be miniaturized due to the tapered portion formation region.

In addition, in order to make the taper angles of the fixing holes on the substrate side and the semiconductor chip side the same, anisotropic etching is used when forming each taper angle, and in order to achieve anisotropic etching with good controllability. For example, if the substrate surface orientation is (10
0) plane, there is a problem that the plane orientation of the semiconductor chip is restricted by the plane orientation of the substrate, such as when the plane orientation of the semiconductor chip is set to the (100) plane. This means that when the surface orientation of the substrate is set to the (100) plane, it is suitable for semiconductor chips with the (100) plane, which is advantageous for MO3 type elements, but it is suitable for semiconductor chips with the (111) plane, such as bipolar transistors. ) would be inappropriate if it were to be implemented.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor device in which wiring pinches can be miniaturized without being subject to restrictions on the semiconductor chip side.

[Means to solve the problem]

In order to achieve the above object, a semiconductor device according to the present invention has a fixing hole penetrating therethrough, and a beam-like shape protruding toward the center of the fixing hole on the main surface side of the semiconductor device. a substrate provided with a frame portion; a semiconductor chip on which an element is formed; and a surface of the beam-shaped frame portion facing the main surface side of the substrate and a periphery of the main surface of the semiconductor chip such that the surface thereof faces the main surface side of the semiconductor chip. , a bonding member for bonding the semiconductor chip to the fixing hole; a planarization layer formed over the substrate and the semiconductor chip; electrically connected to the element, at least a portion of which is on the planarization layer. It is characterized by comprising a wiring formed in.

[Action and effect]

That is, the semiconductor chip, on which the element is formed, has a fixing hole provided in the substrate such that the periphery of the main surface of the semiconductor chip faces the surface of the beam-shaped frame that faces the main surface of the substrate. will be placed in Therefore, the chip position accuracy of the semiconductor chip with respect to the substrate can be easily improved, and the wiring pitch between the substrate and the semiconductor chip can be made finer.

In addition, the semiconductor chip can be mounted in a commonly used rectangular parallelepiped shape, and there is no need to provide a special tapered part for insertion unlike conventional ones. There are no restrictions when matching directions, etc.

Therefore, according to the semiconductor device of the present invention, the semiconductor chip side S
An excellent effect is that the wiring pinch can be miniaturized without being subject to this restriction.

Examples Hereinafter, the present invention will be explained based on two embodiments shown in the drawings.

FIGS. 1(a) and 1(b) show a semiconductor device showing an embodiment of the present invention. Note that FIG. 1(a) is a longitudinal cross-sectional view, which is a cross-sectional view taken along line AA in the plan view S shown in FIG. 1(t)l.

In Figure 1, δ, l is the plane orientation (10
0), (110) etc. 0)', y'J core (S i
) is the substrate. A tapered hole as a fixing hole and a chip alignment beam 9 as a frame are formed in this Si substrate 1 for controllability by anisotropic etching using an alkaline solution such as KOH. Reference numeral 4 is for inserting and fixing a semiconductor chip 2, which will be described later, and a chip alignment beam 9 is for aligning with the periphery of the upper surface of the semiconductor chip 2. The shape of the upper end portion 4a of the hole 4 is the same shape as the upper surface 2a of the semiconductor chip 2, or a slightly larger shape (less than about +IO several μm).

On the other hand, the semiconductor chip 2 is an electronic device in which predetermined elements such as transistors, capacitors, and resistors are formed on a semiconductor substrate such as Si or GaAs, and then chip diced. The semiconductor chip 2 is inserted into a tapered hole 4 provided in the Si substrate 1, the periphery of its upper surface 2a is mated with the lower surface of a chip alignment beam 9, and fixed by a bonding member 3.

At this time, the peripheral edge of the upper surface 2a of the semiconductor chip 2 and the lower surface of the chip alignment beam 9 are brought into contact with each other, so that the S of the semiconductor chip 2 is
Positioning with respect to the i-board 1 becomes easy. In addition, since the semiconductor chip 2 is arranged with no gap between the semiconductor chip 2 and the 51 substrate 1 on the upper surface of the Si substrate 1 by the chip alignment beam 9, a flattening layer between the semiconductor chip 2 and the Si substrate 1, which will be described later, , wiring formation becomes easy.

It was configured by the thickness of the chip joining beam 9. The level difference between the top surface of the semiconductor chip 2 and the top surface of the Si substrate 1 is alleviated by the leveling layer 8, and the elements of one example of the Si substrate and the elements of two examples of the semiconductor chips are connected to the thin film wiring 6 via the electrode 5 and IO, respectively.
connected by. At this time, the inner edge of the chip alignment beam 9 is made into a tapered shape by the above-mentioned anisotropic etching, which reduces the influence of the step difference and improves the step formation method of the upper layer. is suppressed.

With the above configuration, the wiring between the Si substrate 1 side and the semiconductor chip 2 side is miniaturized, and it becomes possible to mount the wiring on the same level as monolithic.

Further, a protective film 7 is formed on the entire surface, and if necessary, through holes for taking out electrodes are formed, and electrode pads are formed.

Note that in the above configuration, the bonding member 3 is attached to the semiconductor chip 2.
Any material can be used as long as it can bond the protective film 7 and the Si substrate 1 together, and preferably, it can be processed at a temperature below the heat resistance temperature of the element considering the heating limit temperature for materials such as the wiring 6 (approximately 500°C in the case of Al), and the protective film 7 Formation temperature (350°C ~ 400°C
A material that has a high heat resistance and can be easily filled into the bonding area is selected (e.g., polyimide resin), taking into consideration the temperature (about 10°F (about 10°F)). Further, the material of the wiring 6 may be any material as long as it allows electrical connection, such as Al, Cu, Au, or W.

There are Mo, polysi, etc. Further, the leveling layer 8 may be made of an insulating material, preferably a material that can cover and absorb large steps and has excellent workability (for example, polyimide resin). The protective film 7 may be made of the same material as that used for the protective film of ordinary ICs, such as plasma carbon
There are silicon dioxide films, silicon nitride films, etc. produced by VD.

Next, the manufacturing process of this example will be explained using FIGS. 2(a) to 2). Note that FIG. 2 shows only a schematic structure, and the detailed structure of the actual element portion (the element formed on the Si substrate 1 and the semiconductor chip 2) is omitted.

First, a semiconductor element (circuit) is formed on the surface of the Si substrate 1 by a normal semiconductor process, and a protective film 11 covering the electrode 5 of the semiconductor element and a protective film 11 covering the back surface of the Si substrate 1 are formed.
' (11 and 11゛ are 5iOz.

5ixNa etc.) is patterned into a desired shape, and as shown in FIG. 2(a), a protective film 11 is formed.
, 11' as an etching mask and alkaline solution (K
OH, NaOH? (G liquid, etc.) is used to anisotropically etch one surface of the substrate.

The upper end size W1 of the tapered hole 4 formed by this anisotropic etching. The thickness h and length b of the chip joining beam 9 can be processed with an accuracy of several μm or less by controlling the etching time or by using a marker to monitor the thickness. Here, an example of the dimensions of each part is described below. The size of W is the semiconductor chip size W to be inserted. It should be designed so that it is slightly larger than (W, = W + 1 + α), considering the variation (about ±10 μm) in the thickness t of the Si substrate l, α = 1
It is preferable to set the value to 4 μm or less. In addition, at this time, the thickness h of the chip alignment beam 9 is set at 30~
The length b of the beam 9 is preferably about 10 μm, and the length b of the beam 9 is 60 μm.
It is preferable to set the thickness to approximately 100 μm. In addition, substrate 1
By using a double-sided mask aligner or the like, positional accuracy of ±5 μm or less can be ensured for positioning the front side portion A and the back side portion B. In this case, the relative positional accuracy between the chip substrates can later be kept to about 20 to 30 μm or less. Note that the taper angle θ formed in the tapered hole 4 and the chip alignment beam 9 by anisotropic etching is 54.7° when a Si substrate with a (100) plane is used as the Si substrate 1; When a Si substrate with a (110) orientation is used, it is 35.3'.

Further, as shown in FIG. 2(b), a predetermined semiconductor element (circuit) is formed on a semiconductor substrate having a predetermined thickness to, and the semiconductor chip 2 is formed by canting it into a shape of a predetermined chip size W0. . This semiconductor chip 2 is a compound semiconductor (
For example, semiconductor devices such as GaAs (GaAs) devices, Si power devices, memory devices, etc. do not necessarily have to be formed in the same manufacturing process as the devices formed on the Si substrate 1. Note that an electrode 10 and a protective film 12 are formed on the semiconductor chip 2.

Next, as shown in FIG. 2(C), the semiconductor chip 2 is placed in the tapered hole 4 of the Si substrate 1 and bonded with the bonding member 3. At this time, the bonding member 3 connects the semiconductor chip 2 to the tapered hole 4.
After inserting the chip into the chip and supporting it with the chimp connecting beam 9, the chip is filled from the back side. For this reason, the joining member 3 is preferably made of a flexible material such as polyimide resin. Further, at this time, the filling is performed so that the bonding member 3 does not ooze out to the surface side of the semiconductor chip. After this, heat treatment is performed to harden and fix the bonding member 3.

After the semiconductor chip 2 is fixed, thin film wiring is performed using a normal semiconductor process in order to electrically connect the chip-side electrode 10 and the substrate-side electrode 5 to further reduce the size and improve the reliability of the wiring. For this purpose, the difference in level between the chip lining 9 and the surface of the chip 2 is flattened to the point where it can be easily wired. That is, as shown in FIG. 2(d), a flattening layer is applied to soften the corners of the level difference so as to absorb the level difference. Any material can be used as long as it can be used.For example, polyimide resin may be applied using a spin code method.The polyimide resin may be patterned as necessary to establish electrical connections at the electrodes 5 and 1O. After that, as shown in FIG. 2(e), a desired wiring 6 is formed by depositing an electrode film on a silicone such as aluminum and buttering it.Furthermore, as shown in FIG. ), a protective film 7 for pannosification (for example, a P SiN film) is formed over the entire surface of the bonded elements, and the semiconductor device shown in FIG. 1 is manufactured.

According to the above embodiment, since the semiconductor chip 2 is arranged and adhesively fixed in the tapered hole 4 having the chip alignment beam 9 on the upper surface 4a, workability is good in the manufacturing process, and the chip 2
The chip alignment beam 9 on the upper surface 4a of the taper hole allows positioning with an accuracy of several tens of micrometers or less, and the wiring between the substrate and the chin 1 can be miniaturized. At this time, the shape of the semiconductor chip 2' may be a normal rectangular parallelepiped shape, and there is no need to process the upper surface of the semiconductor chip 2 into a tapered shape as disclosed in the above-mentioned International Publication No. W○90101215. Also, Si according to substrate 1
(100) and Si (110).

Furthermore, this International Publication No. WO90101215 discloses that a taper having an angle opposite to that of the tapered hole is provided on the upper surface of the tapered hole on the substrate side in order to reduce the influence of the level difference between the substrate and the chimp. In order to insert the tapered portion of the semiconductor chip into the tapered hole on the substrate side, a substrate chip is placed on the surface of the substrate.

A groove, although smaller, is formed between the two.
Although the planarization process may be difficult in terms of productivity, yield, etc., in the above embodiment, the flattening process is facilitated without causing such problems.
It also improves productivity.

In the above embodiment, one semiconductor chip is mounted on the board, but as shown in FIG. 3, a plurality of semiconductor chips may be mounted.

Furthermore, the Si substrate 1 may be used simply as a wiring board.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1(a) and 1(b) are structural diagrams of a semiconductor device showing one embodiment of the present invention, and FIGS. 2(a) to 2) are longitudinal sectional views and plan views, respectively. FIG. 3 is a joint sectional view of a semiconductor device illustrating the manufacturing process of one embodiment of the invention; FIG. 3 is a vertical sectional view of a semiconductor device showing another embodiment of the invention. DESCRIPTION OF SYMBOLS 1... Si substrate, 2... Semiconductor chip, 3... Bonding member, 4... Tapered hole, 5... Substrate side electrode, 6...
... Thin film wiring, 7... Protective film, 8... Flattening layer, 9
...Chip alignment beam, 10...Chip side electrode.

Claims (2)

[Claims] (1) A substrate having a fixing hole provided therethrough and a beam-shaped frame protruding toward the center of the fixing hole on the main surface side thereof, and an element; The formed semiconductor chip is bonded to the fixing hole so that the surface of the beam-shaped frame facing the main surface of the substrate and the periphery of the main surface of the semiconductor chip are opposed to each other. A bonding member, a planarization layer formed over the substrate and the semiconductor chip, and a wiring electrically connected to the element and at least a part of which is formed on the planarization layer. semiconductor devices. (2) The beam-shaped frame portion is inclined so that the height of protrusion toward the center of the fixing hole is greater on the side facing the main surface of the substrate than on the side of the main surface of the substrate. 2. The semiconductor device according to claim 1, further comprising: