JPH03292722A - Manufacture of silicon single crystal thin film - Google Patents

Abstract

PURPOSE:To form (100) Si single crystal in very excellent bond properties between an SiO2 substrate and Si crystals to each other by a method wherein Si in the surface direction of (100) is selective epitaxially grown as seed crystals on a substrate comprising SiO2. CONSTITUTION:A 4-inch (100) Si wafer 11 is prepared and then the surface thereof is oxidized in thickness of 0.5mum to form an insulator layer 12. Next, SEG crystals 14 are selective epitaxially grown (SEG) in the openings 13 of the wafer 11 so as to be buried therein attaining the same level as that of the surface of the insulator layer 12. Successively, the surface flattened by SEG and the flattened surface of a 4-inch fused quartz wafer 10 are bonded to each other to form an interface 15 and then the (100) Si wafer 11 side is polished until the insulator layer 12 is exposed. Finally, the surface of grown crystals 16 epitaxial laterally overgrown (ELO) on an SiO2 surface using SEG crystals 14 as seed crystals are polished to form flat polished crystals 16'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides Si!
#Relates to a method for producing a crystalline thin film.

[Prior Art] It has been known that when a 51 film is formed on a substrate containing 5102, such as a quartz substrate, tensile stress acts on the Si film.

For example, when the tensile stress is applied to a Si film with a (100) plane orientation, the electron mobility in the film becomes extremely high. There is a report that this has been proven through theoretical calculations and experiments by BY, Tsaur, and colleagues at MIT (Massachusetts Canine Science) (B-Y, Tsaur,
John C, C, Fan, and M, W, Gels
, Appl, Phys, Lett, 40(4), 15
February 1982).

According to this report, a (100) oriented Si film subjected to tensile stress has an electron mobility of more than 1.5 times that of a Si wafer, which is a car.
It is said that a semiconductor element formed on an i-film can more easily achieve higher performance than a semiconductor element formed on the Si wafer. However, for thin films with orientations other than the (100) plane,
Not only is tensile stress less effective, but tensile stress can have an adverse effect on hole mobility.

On the other hand, although various methods have been reported for forming a Si single-crystal thin film on bulk SiO2 such as a quartz substrate, it is possible to fabricate a completely Si single-crystal thin film oriented in the (ioo) plane. Very few methods have been developed to do so.

However, for example, as shown in FIG.
, Tsaur et al. deposited a film 31 (polycrystalline or amorphous) 31 on a fused quartz substrate 30, melted it once with a rod-shaped heater 33 and recrystallized it, and then
) has proposed a method called the so-called melt recrystallization method (hereinafter referred to as ZMR method) to obtain the alignment film 32. This method utilizes the phenomenon that when liquid phase Si crystallizes on the 5i02 surface, it is easy to select the (100) plane orientation where the interfacial energy is stable.

Another method is the so-called bonding method as shown in FIG. In this method, the S1 wafer 41 and another support having an insulating material surface, for example, the S1 wafer 42 having an oxide layer 43 on the surface, are brought into close contact with each other, and are brought into contact with each other by heat treatment such as H2; In either case, polishing is attempted to leave an oxide film 43 and a thin film 41° (La5ky, J, B, 5
tiffler, S, RWhite, F, R, and
Abernathey, J. R., “S i l 1
con-on-Tnsu-1ator (SOI) by
Bonding and Etch-Back+IE
EE International Electro
n Devices Meeting (IEDM)Te
Chnical Digest, pp684-687.
(Dec, 1985, and several other reported examples).

[Problem to be Solved by the Invention] However, the above-mentioned prior art has the following problems.

First, the ZMR method is performed using the 5i02-S
Since the orientation of the i-interface is determined by the ease with which the interfacial energy can be stabilized, the crystal orientation is affected by minute displacements such as scratches and irregularities on the substrate surface.
- It is difficult to produce a crystalline thin film having a (100) plane orientation. Furthermore, -11Q-wise, it is known that the S film formed by the ZMR method is polycrystalline with a large grain size on the order of millimeters, which means that the grain size is
This suggests that there are boundaries (grain boundaries), that is, it is not possible to form a uniform single crystal film over the entire film.

Next, regarding the above-mentioned bonding method, in this method, a perfect crystal with a wafer-sized (100) plane orientation is
Although it is possible to fabricate it on i02, it has the drawback of weak adhesive strength. In other words, even if a 31 thin film is formed on a quartz substrate by this bonding method, peeling of the film is likely to occur due to the influence of tensile stress.

Further, even if the Si layers are bonded together in a sufficient state, it is extremely difficult to form a uniform thin film due to subsequent polishing of the bulk Si. In other words, since the S1 wafer inherently has a warp of several μm to several tens of μm, if the wafers are polished in parallel after bonding, they will have considerable @ thickness unevenness. be.

The present invention aims to solve the problems of the prior art described above.
The substrate soil has a uniformly determined (100) plane orientation,
@ S1 is uniform in thickness and useful for application to high-performance semiconductor devices! # The purpose is to share how to make and knit crystal clothes.

[Means for Solving the Problems] The present invention has been achieved through extensive research in order to achieve the above objects.

The present invention includes S10. On a substrate whose component is
In the method of manufacturing 5il-crystalline FiPA of (100), a first insulating layer is formed on the surface of the Si wafer, which can be selectively polished with Si and can also be used as a mask for selective epitaxial growth. forming an opening in a portion of the insulating layer to form a mask;
a second step of selectively epitaxially growing Si of the Si univer facing through the opening up to the surface of the insulating layer; and bringing the surface on which the selective epitaxial growth has been made into close contact with the surface of the substrate; a third step of performing heat treatment to bond the adhering portion; a fourth step of performing selective polishing from the Si wafer side of the bonded rough substrate using the mask as a stopper; and a fourth step of performing selective polishing using the mask as a stopper. S of plane orientation of (ioo)
A fifth step of selectively growing Si on the substrate using i as a seed crystal.

[Operation] (I) In the first step, an insulating layer is formed on the surface of the (100) Si wafer by oxidation or the like.

The insulating layer functions both as a mask and a stopper for selective polishing, so it is possible to use materials that can be used for both.
For example, it consists of 5i02, Sis N4.5iON, etc. In this case, when SiO2 is selected as the material, the surface of the Si wafer 11 may be thermally oxidized. In other cases, the material is deposited by CVD or the like.

The thickness of the insulating layer is preferably set to 0.1 to 10 μm, more preferably 02 to 0.5 μm, so that it can sufficiently function as both a mask and a stopper. Note that the optimum film thickness varies depending on the material of the mask and the method of subsequent polishing.

(11) In the second step, a minute opening is formed at an arbitrary position in the insulating layer formed in the first step, and then the Si plane exposed from the opening is selected as a seed crystal. Epitaxial growth (hereinafter referred to as SEG) is performed.

The size of the opening is 1 to 5 μm in diameter, preferably 2 to 4 μm, considering the SEG and lateral growth.
Optimally, it is set to about 3 μm.

The growth of the SEG crystal formed by the SEG is terminated when its growth surface becomes flush with the surface of the insulating layer serving as the mask.

When performing the above SEG, the gas system is SiH4, S
Silane-based ones such as i□H6, and 5iH2Cn2,
A chlorosilane type material such as 5iHCf13, 5iCu4, etc. is used, and as the additive residue, HCJ2 or the like having an etching action is used.

Furthermore, H2 is used as the carrier cassette.

The temperature depends largely on the gas used, etc., but is between 800 and 120.
The temperature is set at 0°C, preferably 900-1100°C.

The pressure is set in the range of several tens of Torr to 200 Torr, preferably around 100 Torr.

(III) The third technique is to bring a substrate containing SiO2 into contact with the surface of the SEG-treated Si unibar,
Afterwards, a mounting process is performed to ensure that the corresponding contact areas are sufficiently bonded.

Materials for the substrate containing 5i02 include fused silica,
Synthetic quartz, high heat-resistant glass, etc., which have 5in2 as a main component and can withstand the heat treatment temperature, can be used. The temperature of the heat treatment is preferably around the glass transition temperature of the 5102 substrate 10. Further, the atmosphere for the heat treatment is preferably hydrogen (H2) or a forming gas containing hydrogen.

In the step (rV)i4, the S] wafer with a surface orientation of (100) is polished with a selected stone.

The polishing is finished when the surface of the insulating layer serving as a mask is exposed.

There are two types of selective polishing methods.

One is mechanical chemical polishing method (mechanochemical etching),
One is a mechanical polishing method (mechanical etching).

The former is a selective polishing method in which when 5102 is selected as the forward bending insulator layer, a special chemical polishing solution is mixed to make the polishing speeds of Si and 5102 significantly different (Hamada, Journal of the Physical Society of Japan, Vol. 56, No. 11, p. 1480, etc.).

Specifically, the above polishing is performed using, for example, ethylene diamine,
This is done using an alkaline solution called pyrocatechol with a borizing cloth. In addition, the above chemical polishing liquid polishes Si with 5i (
It dissolves as OH)62- but does not react with 5i02, so the exposed 5i02 surface becomes the polishing end position.
The exposed surface acts as a stop.

On the other hand, when a material such as Si3N4, which has a Mohs hardness sufficiently higher than that of Si, is used for the insulating layer serving as a mask, a material polishing method can be used (Japanese Patent Application No. 63-247819). The above polishing method uses "colloidal" abrasive grains, which have a hardness equal to or higher than St, but lower than 5L3N4.
Silica is used as an abrasive for mechanical polishing. Colloidal silica has low hardness, so Si3N
Since the Si3N4 surface cannot be polished, the polishing is finished when the Si3N4 surface is exposed.

Note that any insulator that is harder than colloidal silica and that can be selectively grown can be used as a mask for mechanical polishing in the process of the present invention.

Next, the insulating layer is etched. At this time, 5i
Etching of the 02 substrate and SEG crystal is avoided. Note that if the material of the insulating layer is, for example, 5isN4, hot phosphoric acid is preferable. The material of the insulating layer is a thermal oxide film of a (100) Si wafer or deposited by atmospheric pressure CVD, etc. 5
If it is iOz, a dilute hydrofluoric acid solution or the like can be used. However, in this case, the substrate needs to be made of fused silica or synthetic quartz. (Fused quartz, synthetic quartz, etc. have a slower HF etch rate than a thermal oxide film or CVD-SiO2).

Further, when the material of the insulating layer is 5i02, the etching step can be omitted.

(V) In the fifth step, selective growth of Si is performed using the SEG crystal as a seed crystal.

The selective growth may be the same as the second step. However, it is preferable that the treatment be carried out until the grown crystals grown from adjacent seed crystals come into contact with each other and form grain boundaries. However, the grown crystals obtained by the selective growth do not necessarily have to be continuous across grain boundaries.

Note that since the grown crystal has facets, the upper surface is polished to obtain a flat polished crystal. Polishing in this case may be performed in the same manner as general final polishing such as when forming a mirror surface of a Si wafer.

The thickness of the polished crystal is preferably about 1.2 to 10 μm, more preferably about 0.4 to 2 μm. The optimal thickness is about 0.5 μm.

During the polishing, since the grown crystals have the same size and plane orientation, the thickness of the film to be left can be easily controlled by controlling the time.

[Example 1] The above (100) Si single crystal Fi! Next, a first example of a method for manufacturing a membrane will be specifically described.

(a) First, as shown in Figure S1 (a), a 4-inch (
100) Prepare a Si wafer 11, and make its surface 0.5
An insulator layer 12 was formed by oxidizing the insulating material to a micrometer. The oxidation conditions were H
The temperature is 1000℃ in an atmosphere of 2:02=3・2,
The oxidation time was 3 hours.

Next, using a normal photolithography process, five portions of the insulating layer 12 that will become the openings 13 with a diameter of 2 μm are formed.
Patterned in a matrix at 0 μm intervals, HF
M? W-etched.

(b) Next, as shown in FIG. 1(b), an SEG crystal 14 is grown in the opening 13 of the wafer by SEG, and the SEG crystal 14 becomes a surface that is flush with the surface of the insulating layer 12. It was buried like that. The SEG conditions are as follows.

Gas type: S i H2Cfl 2 / HC
Jl/H2 gas flow ratio...0.53/1.6/
100 [1/min] Temperature...+030 [t] Pressure -100 [Torr Co-growth time -180 [sec] (c) Subsequently, as shown in FIG. 1(c), the SEG
The flat surface of the 4-inch fused silica wafer 10 is brought into close contact to form an interface 15.
Heat treatment was performed at 980° C. for 30 minutes in a forming gas atmosphere of 2:N2 = 20:80 (%) to bond the adhesive portions.

(d) Furthermore, as shown in FIG. 1(d), the (100) Si wafer side of the bonded product is polished. In this case, the thickness of the Si wafer 11 is originally formed to be about 520 μm, so the thickness of the Si wafer 11 is alumina (Af12) up to 50 μm.
Rough cutting was performed using coarse abrasive grains such as No. 03), and thereafter, polishing was performed using the mechanochemical etching method described above, and the polishing was completed when the insulating layer 12 was exposed.

Specifically, polishing was performed while sliding the Si single crystal part on a commercially available polishing cloth and injecting small amounts of ethylenediamine pyrocatechol, set at pH = 9.5 and temperature 45°C, onto the sliding surface. .

(e) In the process diagram shown in FIG. 1(e), the insulating layer 12 serving as a mask is etched, but in this example, the insulating layer 12 is SiO2, which has the same composition as the quartz substrate 10, that is, S
Since the stress on the i-crystal is the same, the main etching step can be omitted.

(f) Then, as shown in FIG. 1(f), the SEG
Lateral growth (
Epitaxial Lateral Overg
rowth.

(hereinafter referred to as ELO). The conditions at this time were the same as the SEG conditions used in the step (b) above. However, the growth time was 90 minutes, which was the time until adjacent grown crystals 16 came into contact with each other to form grain boundaries 17.

(g) Finally, as shown in FIG. 1 (g), the ELO
The upper surface of the grown crystal 16 was polished to form a flat polished crystal 16'' with a thickness of 2 μm. The polishing in this case is similar to the polishing when making a normal Si wafer, and the final result is a mirror finish.

As shown in FIG. 2, the Si single-crystal thin film produced in this manner has a Si complete single-crystal film 26' with (ioo) plane orientation in each region surrounded by grain boundaries 27. It became formed. As described in (a) above, the size of one region of the single crystal film 26° was 50 μm in length and width and 2 μm in thickness since the pitch of the openings 13 was 50 μm.

Note that one NM in one region of the single crystal @26″
When an OS transistor was formed, its electron mobility was 800 cm2/v sec, and the electron B mobility on a normal Si wafer formed by the same process was 600 cm2/v sec.
This greatly exceeded V-see.

[Other Examples] Next, a second example will be explained.

(a') A 4-inch (100) Si wafer 11 was prepared, and an insulating layer 12 made of Si3N4 was deposited to a thickness of 0.2 μm on its surface by the LPCVD method (first
(See figure (a)). The deposition conditions in this case are SiH2CJ
Using a mixed gas of 22 = 20 sec and NH3 = 80 sec, the temperature was 800°C, and the degree of vacuum was 0.3 Torr.
The deposition time was 60 minutes. Next, openings 13 having a diameter of 2 μm were patterned in the insulating layer 12 at intervals of 50 μm using a conventional photolithography technique, and etched by RIE (reactive ion etching).

(bo) Perform the SEG under the following conditions (Figure 1(b)
reference).

Gas type...S i H2Cf12 / HCj
2/H2 gas flow ratio...0.53/2.4/1
00 [base/m1nl] Temperature...1 oso [℃] Pressure -80 [Torr] Growth time -220 [sec] (C) A fused silica wafer 10 was placed on the growth surface side of the grown crystal thus obtained. Let me watch, 1000' with H4 air
The adhesion surface was bonded by heat treatment with Cl2O for a minute (first
(See figure (C)).

(d') Polishing the bonded wafer from the Si wafer side. This polishing is the mechanical polishing described above, and is performed using colloidal silica (SiO2) as abrasive grains (Fig. 1(d)
)reference). Specifically, commercially available Borising cloth has 51
Polishing was performed while sliding the single crystal and injecting colloidal silica suspended in a neutral solution into the sliding part. This solution was a mixture of methanol and water in a ratio of 3=7, and colloidal silica with particle sizes of 100 was used.

(e') When the insulating layer 12, which is a Si3N4 film, is exposed, the polishing is finished, and the insulating layer 12 exposed to the surface is removed.
was etched with hot phosphoric acid H3PO4 (180°C) (see Figure 1(e)).

(fo) Using the SEG crystal 14 as a seed crystal, 5f3
The grown crystal 16 is subjected to ELO on the N4 plane (see FIG. 1(f)). The conditions for this ELO are as follows.

Gas type: S i H2CIt 2 / HC
IL/H2 gas flow ratio...0.53/1.8/
100 [It / m t n temperature ... bow 050 ['C] pressure - = 80 [Torr growth time ... 90 [min] (go) After that, as in the case of the first embodiment, When the upper part of the grown crystal 16 was polished, a uniform polished crystal 16° with a thickness of 1 μm was obtained (see FIG. 1(g)).
.

Note that the electron mobility of the NMo5 transistor formed on this 16° polished crystal is 800 Cm2/v-5eC, which is similar to that of the first example, and it also has a performance higher than that of the bulk single crystal 51. was.

[Effects of the Invention] As explained above, according to the present invention, complete control of the plane orientation can be achieved by selectively growing Si with a (100) plane orientation as a seed crystal on a substrate containing SiO2 as a component. grain boundaries can be set at any position. In addition, in the present invention, only the seed crystal part is bonded together, and most of the crystals are grown laterally on the substrate, so the adhesion between the SiO□ substrate and the Si crystal is extremely good (100 ) A Si single crystal can be formed.

[Brief explanation of drawings]

FIGS. 1(a) to (g) are process diagrams according to embodiments of the present invention,
FIG. 2 is a perspective view of a substrate on which a single crystal film of the present invention is formed, FIG. 3 is a side sectional view illustrating the production of a single crystal film by the conventional ZMR method, and FIG. 4 (a). (b) is a side sectional view illustrating the production of a single crystal film by a conventional bonding method. Figure (Explanation of symbols) 10.20...Quartz substrate, 11...Si substrate, 12
... Insulator layer, 13... Opening, 14... SEG
Crystal, 15...Interface, 16...Growing crystal, 16°・
...Polished crystal 26°...5ijlL crystal film layer, 17.
27... Grain boundary 412 Fig. 4 Fig.

Claims (1)

[Claims] (1) On a substrate containing SiO_2, the plane orientation is (
(100) In the method for producing a Si single crystal thin film, a first step is performed to form an insulating layer on the surface of the Si wafer, which can be selectively polished with Si and can also be used as a mask for selective epitaxial growth. a second step of forming an opening in the insulating layer to form a mask, and selectively epitaxially growing Si of the Si wafer exposed through the opening to the surface of the insulating layer; a third step of bringing the surface on which selective epitaxial growth has been performed and the surface of the substrate into contact and performing heat treatment to bond the corresponding contact portion; and applying the mask from the Si wafer side of the bonded substrate. A fourth step of performing selective polishing as a stopper, and S of the orientation of the (100) plane left by the selective polishing.
a fifth step of selectively growing Si on the substrate using i as a seed crystal.