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JPH03296253A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPH03296253A
JPH03296253A JP9821490A JP9821490A JPH03296253A JP H03296253 A JPH03296253 A JP H03296253A JP 9821490 A JP9821490 A JP 9821490A JP 9821490 A JP9821490 A JP 9821490A JP H03296253 A JPH03296253 A JP H03296253A
Authority
JP
Japan
Prior art keywords
lead
rigidity
hole
processing
molding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9821490A
Other languages
Japanese (ja)
Inventor
Shoichi Kobayashi
小林 昇市
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Semiconductor Package and Test Solutions Co Ltd
Original Assignee
Hitachi Ltd
Hitachi Yonezawa Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Yonezawa Electronics Co Ltd filed Critical Hitachi Ltd
Priority to JP9821490A priority Critical patent/JPH03296253A/en
Publication of JPH03296253A publication Critical patent/JPH03296253A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To decrease the effect of spring back even if molding is applied, and improve the accuracy in processing attendant upon the molding by providing a means which reduces the rigidity of a lead. CONSTITUTION:The lead part 2 of a lead frame 1 is provided, at regular intervals, with through holes 3, as rigidity reducing means for weakening the rigidity. The through hole 3 can be made by press processing or etching processing. The diameter of the through hole 3 is changed according to the width of the lead part 2. By having provided the through hole 3, the rigidity of the lead part 2 is weakened, and the accuracy in processing after molding becomes a planned value, and the dispersion of accuracy in processing by feedback can be made small. In addition, it follows that the area of the surface of the lead part 2 has increased, and the contact area of the junction material (solder, or the like) interposed between the outer lead and the pattern on the substrate in mounting widens, and the junction part has irregularity by the through hole 3, so junction strength improves.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置のリードに関する技術、特に、リー
ドの成形加工を高精度に行うた島に用いて効果のある技
術に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technology related to leads of semiconductor devices, and in particular to a technology that is effective when used to form leads with high precision.

〔従来の技術〕[Conventional technology]

従来、半導体装置に用いられるリードフレーム■ は、第8図に示すように、プレス加工によってインナー
リード及びアラクーリードを形成し、これをフィルム板
状に連続的に並べる構成にしている。
Conventionally, a lead frame (2) used for a semiconductor device has a structure in which inner leads and Araku leads are formed by press working and are continuously arranged in a film plate shape, as shown in FIG.

なお・・、プレス加工に代え、エツチングによる加工も
用いられている。
Note that instead of press working, etching is also used.

ところで、本発明者は、リードの剛性について検討した
By the way, the present inventor studied the rigidity of the lead.

以下は、本発明者によって検討された技術であり、その
概要は次の通りである。
The following are the techniques studied by the present inventor, and the outline thereof is as follows.

すなわち、リードフレームを用いた半導体装置のリード
成形を行う場合、半導体チップの外周に対するモールド
が終了ののち、不要部分を切断除去すると共にパッケー
ジから突出するリードを上下方向に曲げ加工を施すこと
により、機械的に折り曲げ加工を行っている。
That is, when molding the leads of a semiconductor device using a lead frame, after the molding of the outer periphery of the semiconductor chip is completed, unnecessary parts are cut and removed and the leads protruding from the package are bent in the vertical direction. The bending process is done mechanically.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところが、前記のようにリードフレームを用いて加工し
たリードは、その剛性に配慮がなされていない為に、成
形加工時にスプリングバックが生じ、予定した加工精度
が出ないという問題のあることが本発明者によって見い
出された。
However, since the rigidity of the leads processed using the lead frame as described above is not considered, springback occurs during the molding process, resulting in a problem that the expected processing accuracy cannot be obtained. discovered by someone.

特に、この問題はQFP(クワッド・フラット・パッケ
ージ)型リードにおいて顕著である。
This problem is particularly noticeable in QFP (quad flat package) type leads.

そこで、本発明の目的は、成形加工における加工精度を
向上させることのできる技術を提供することにある。
Therefore, an object of the present invention is to provide a technique that can improve processing accuracy in molding processing.

本発明の前記目的と新規な特徴は、本明細書の記述及び
添付図面から明らかになるであろう。
The above objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

〔課題を解決するための手段〕[Means to solve the problem]

本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、以下の通りである。
A brief overview of typical inventions disclosed in this application is as follows.

すなわち、工程の最終段階でリードに対し成形加工が施
されるリードフレームであって、少なくともリードの成
形加工部に剛性低減手段を設けるようにしている。
That is, in a lead frame in which the leads are molded at the final stage of the process, at least the molded portion of the leads is provided with a rigidity reducing means.

〔作用〕 上記した手段によれば、リードの剛性低減手段を設けた
部分は、他の部分に比べて剛性が小さくなり、成形加工
を施してもスプリングバックの影響を小さくすることが
できる。したがって、成形加工に伴う加工精度を向上さ
せることができる。
[Operation] According to the above-described means, the portion of the lead provided with the rigidity reducing means has a lower rigidity than other portions, and even if molding is performed, the influence of springback can be reduced. Therefore, it is possible to improve the processing accuracy associated with the molding process.

〔実施例1〕 第1図は本発明によるリードフレームの一実施例の主要
部を示す平面図である。
[Embodiment 1] FIG. 1 is a plan view showing the main parts of an embodiment of a lead frame according to the present invention.

リードフレーム1のリード部2には、一定間隔に剛性を
弱くするための剛性低減手段として、貫通孔3を第2図
のように設けている。この貫通孔3は、プレス加工また
はエツチング加工により作成することができる。また、
貫通孔3は、リード部2の幅に応じてその直径を変えて
いる。
As shown in FIG. 2, through holes 3 are provided in the lead portion 2 of the lead frame 1 as a rigidity reducing means for weakening the rigidity at regular intervals. This through hole 3 can be created by pressing or etching. Also,
The diameter of the through hole 3 changes depending on the width of the lead portion 2.

このように貫通孔3を設けたことにより、リード部2の
剛性が弱められ、成形後の加工精度は予定した値になり
、スプリングバックによる加工精度のばらつきを小さく
することができる。加えて、貫通孔3を設けたことによ
りリード部2の表面積が増大したことになり、放熱効果
を向上させることができる。
By providing the through hole 3 in this manner, the rigidity of the lead portion 2 is weakened, the processing accuracy after molding becomes a predetermined value, and variations in processing accuracy due to springback can be reduced. In addition, by providing the through holes 3, the surface area of the lead portion 2 is increased, so that the heat dissipation effect can be improved.

さらには、実装時のアウターリードと基板上のパターン
との間に介在する接合材(はんだなど)の接触面積が広
くなり、かつ接合部分が貫通孔3により凹凸を有するこ
とから、接合強度が向上する。
Furthermore, the contact area of the bonding material (solder, etc.) interposed between the outer lead and the pattern on the board during mounting is widened, and the bonding area is uneven due to the through holes 3, so the bonding strength is improved. do.

なお、リードの先端に貫通孔を設けた例として、例えば
、特開平1−140647号公報がある。
Note that, as an example of providing a through hole at the tip of the lead, there is, for example, Japanese Patent Application Laid-Open No. 1-140647.

しかし、ここに示された構成は、はんだが貫通孔内に蓄
積されるようにして、はんだ不良の低減を目的としたも
のであり、本発明のように成形加工部に設けるものでは
なく、リード先端に設けたものであるから、剛性を低減
することは不可能である。
However, the configuration shown here is intended to reduce solder defects by allowing solder to accumulate in the through-hole, and is not provided in the molded part as in the present invention, but rather in the lead. Since it is provided at the tip, it is impossible to reduce the rigidity.

〔実施例2〕 第3図は本発明による剛性低減手段の第2実施例を示す
断面図である。
[Embodiment 2] FIG. 3 is a sectional view showing a second embodiment of the rigidity reducing means according to the present invention.

前記実施例が貫通孔であったのに対し、半球状の凹部4
を設けたものである。この形状は、貫通孔3に比べて剛
性低減効果は弱くなるが、リード部2の幅及び材質に応
じて使い分けることができる。
Whereas the previous embodiment had a through hole, a hemispherical recess 4 was used.
It has been established. Although this shape has a weaker stiffness reducing effect than the through hole 3, it can be used depending on the width and material of the lead portion 2.

なお、片面に限らず第4図に示すように両面に凹部4a
、4bを設けることも可能である。この構成では、第2
図の構成と第3図の構成との中間程度の剛性低減効果が
得られる。
Note that the recess 4a is not limited to one side, but is formed on both sides as shown in FIG.
, 4b may also be provided. In this configuration, the second
An intermediate stiffness reduction effect between the configuration shown in the figure and the configuration shown in FIG. 3 can be obtained.

また、凹部4に代えて、第5図に示すように、すり林状
の凹部5を設けることもできる。
Furthermore, instead of the recess 4, a forest-like recess 5 may be provided as shown in FIG.

以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることは言うまでもない。
Above, the invention made by the present inventor has been specifically explained based on Examples, but it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. stomach.

例えば、第1図においては、剛性低減手段をリード部2
の全体に設けるものとしたが、第6図に示すような曲げ
加工を施す場合、この部分にのみ、剛性低減手段を第7
図に示すように、リード部2の成形加工部のみに設ける
ものとしてもよい。剛性が問題になるのは、曲げ加工の
施される部分のみであり、実装強度の向上を必要としな
い場合に有効である。
For example, in FIG. 1, the rigidity reducing means is connected to the lead portion 2.
However, when bending as shown in Fig. 6, the stiffness reducing means is provided only in this part.
As shown in the figure, it may be provided only in the molded part of the lead part 2. Rigidity is a problem only in the part that is bent, and is effective when there is no need to improve mounting strength.

〔発明の効果〕〔Effect of the invention〕

本願において開示される発明のうち、代表的なものによ
って得られる効果を簡単に説明すれば、下記の通りであ
る。
Among the inventions disclosed in this application, the effects obtained by typical ones are as follows.

すなわち、工程の最終段階でリードに対し成形加工が施
されるリードフレームであって、少なくともリードの成
形加工部に剛性低減手段を設けるようにしたので、成形
加工に伴う加工精度を向上させることができる。
In other words, in the lead frame in which the leads are molded at the final stage of the process, at least the molded part of the leads is provided with a rigidity reducing means, so that the processing accuracy associated with the molding process can be improved. can.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明によるリードフレームの一実施例の主要
部を示す平面図、 第2図は断面図1図に示す貫通孔の詳細を示す断面図、 第3図は本発明による剛性低減手段の第2実施例を示す
断面図、 第4図は第3図の剛性低減手段の変形例を示す断面図、 第5図は第4図の剛性低減手段の他の変形例を示す断面
図、 第6図は成形加工の一例を示す斜視図、第7図は第6図
の成形加工を行うためのリードフレーム形状を示す平面
図、 第8図は従来のリードフレームを示す平面図である。 1・ ・ ・リードフレーム、2・ ・ ・リード部、
3・・・貫通孔、4.4a、4b、5・・・凹部。
FIG. 1 is a plan view showing the main parts of an embodiment of a lead frame according to the present invention, FIG. 2 is a sectional view showing details of the through hole shown in FIG. 1, and FIG. 3 is a rigidity reducing means according to the present invention. 4 is a sectional view showing a modification of the stiffness reducing means shown in FIG. 3; FIG. 5 is a sectional view showing another modification of the stiffness reducing means shown in FIG. 4; FIG. 6 is a perspective view showing an example of the forming process, FIG. 7 is a plan view showing the shape of a lead frame for performing the forming process shown in FIG. 6, and FIG. 8 is a plan view showing a conventional lead frame. 1. . . Lead frame, 2. . . Lead part,
3... Through hole, 4.4a, 4b, 5... Recessed part.

Claims (1)

【特許請求の範囲】 1、工程の最終段階でリードに対し成形加工が施される
リードフレームであって、少なくともリードの成形加工
部に剛性低減手段を設けることを特徴とするリードフレ
ーム。 2、前記剛性低減手段は、貫通孔であることを特徴とす
る請求項1記載のリードフレーム。 3、前記剛性低減手段は、少なくとも片面に設けた凹部
であることを特徴とする請求項1記載のリードフレーム
[Scope of Claims] 1. A lead frame in which the leads are subjected to molding at the final stage of the process, characterized in that at least the molded portion of the leads is provided with rigidity reducing means. 2. The lead frame according to claim 1, wherein the rigidity reducing means is a through hole. 3. The lead frame according to claim 1, wherein the rigidity reducing means is a recess provided on at least one surface.
JP9821490A 1990-04-13 1990-04-13 Lead frame Pending JPH03296253A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9821490A JPH03296253A (en) 1990-04-13 1990-04-13 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9821490A JPH03296253A (en) 1990-04-13 1990-04-13 Lead frame

Publications (1)

Publication Number Publication Date
JPH03296253A true JPH03296253A (en) 1991-12-26

Family

ID=14213726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9821490A Pending JPH03296253A (en) 1990-04-13 1990-04-13 Lead frame

Country Status (1)

Country Link
JP (1) JPH03296253A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5541451A (en) * 1994-10-24 1996-07-30 Kabushiki Kaisha Toshiba Packaged semiconductor device with external leads having anchor holes provided at polyamide/glass sealed regions
US5683944A (en) * 1995-09-01 1997-11-04 Motorola, Inc. Method of fabricating a thermally enhanced lead frame
JP2012512477A (en) * 2008-12-17 2012-05-31 エフシーアイ IC non-contact communication device manufacturing method
JP2023516450A (en) * 2021-02-05 2023-04-19 チャンシン メモリー テクノロジーズ インコーポレイテッド Package substrate and semiconductor structure comprising the package substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5541451A (en) * 1994-10-24 1996-07-30 Kabushiki Kaisha Toshiba Packaged semiconductor device with external leads having anchor holes provided at polyamide/glass sealed regions
US5683944A (en) * 1995-09-01 1997-11-04 Motorola, Inc. Method of fabricating a thermally enhanced lead frame
JP2012512477A (en) * 2008-12-17 2012-05-31 エフシーアイ IC non-contact communication device manufacturing method
JP2023516450A (en) * 2021-02-05 2023-04-19 チャンシン メモリー テクノロジーズ インコーポレイテッド Package substrate and semiconductor structure comprising the package substrate

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