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JPH03282381A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPH03282381A
JPH03282381A JP2084008A JP8400890A JPH03282381A JP H03282381 A JPH03282381 A JP H03282381A JP 2084008 A JP2084008 A JP 2084008A JP 8400890 A JP8400890 A JP 8400890A JP H03282381 A JPH03282381 A JP H03282381A
Authority
JP
Japan
Prior art keywords
signal
circuit
test
output
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2084008A
Other languages
Japanese (ja)
Inventor
Katsuhiko Nakagawa
克彦 中川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2084008A priority Critical patent/JPH03282381A/en
Publication of JPH03282381A publication Critical patent/JPH03282381A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To effectively perform a thermal acceleration test without reducing economy by generating a test control signal inside an integrated circuit (IC) device and simultaneously outputting it to the outside terminal. CONSTITUTION:When a test signal 13 is inactive, an input signal 7 is inputted to a control circuit 5 by a selection in an input changeover circuit 6. The control signals 8, 9 are outputted to each part of the IC device 1 inside by the circuit 5 in accordance with this signal 7, and a signal 10 is outputted from an output signal generator 2 and transmitted to the output terminal through an output changeover circuit 3, then the device 1 performs the normal operation. Next, when the signal 13 is active, a control signal 11 generated from a test control signal generating circuit 4 is outputted as an output signal 12 through the circuit 3 and also inputted to the circuit 5 through the circuit 6, then the signals 8, 9 are outputted by the circuit 5. In the circuit 4, the next signal 11 is generated by the signal 9, and the same operations are repeated thereafter. Then, by observing these signals from the outside, the decision is made whether the device 1 is properly operated during the thermal acceleration test for the device 1, or not.

Description

【発明の詳細な説明】 [産業上の利用分野コ 本発明は集積回路装置に関する。[Detailed description of the invention] [Industrial application fields] The present invention relates to integrated circuit devices.

[従来の技術] 従来、集積回路装置の熱的加速試験は、集積回路装置の
電源端子に電圧を加えた状態で加熱して行なわれていた
。この時、集積回路装置の入力端子は電源電位または接
地電位に固定されていた。
[Prior Art] Conventionally, a thermally accelerated test of an integrated circuit device has been carried out by heating the integrated circuit device while applying a voltage to the power supply terminal thereof. At this time, the input terminal of the integrated circuit device was fixed at a power supply potential or a ground potential.

[発明が解決しようとする課題] 上述した従来の熱的加速試験方法は、次のような欠点か
ある。
[Problems to be Solved by the Invention] The conventional thermally accelerated testing method described above has the following drawbacks.

(1)入力端子が固定されており集積回路装置の内部は
ほとんど動作しないため、内部素子に流れる電流が実際
の動作状態と異なることにより、加速試験の効果が低下
する。
(1) Since the input terminal is fixed and the inside of the integrated circuit device hardly operates, the current flowing through the internal elements differs from the actual operating state, reducing the effectiveness of the accelerated test.

(2)また、内部を動作させた状態で加速試験を行なう
ためには、パターン発生器等の高価な装置を必要とする
ため経済的に不利である。
(2) Furthermore, in order to perform an accelerated test while the internal parts are in operation, expensive equipment such as a pattern generator is required, which is economically disadvantageous.

(3)さらに、パターン発生器を用いた場合でも集積回
路装置が正しく動作しているか否かを監視している必要
があるため実現はかなり困難となる。
(3) Furthermore, even when a pattern generator is used, it is quite difficult to realize this because it is necessary to monitor whether the integrated circuit device is operating correctly.

本発明の目的は、パターン発生器等の高価な装置を必要
とすることなく、内部を動作させた状態で熱的加速試験
を行なうことができる集積回路装置を提供することであ
る。
SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit device in which a thermally accelerated test can be performed while the device is in operation, without requiring expensive equipment such as a pattern generator.

[課題を解決するための手段] 本発明の集積回路装置は、 外部からのテスト信号がアクティブのときテスト制御信
号を発生するテスト制御信号発生回路と、 前記テスト信号がインアクティブのとき本集積回路装置
の通常動作にもとづく出力信号を、前記テスト信号がア
クティブのとき前記テスト制御信号発生回路から出力さ
れたテスト制御信号をそれぞれ出力端子に出力する出力
切換回路と、前記テスト信号かインアクティブのとき本
集積回路装置に入力された入力信号を、前記テスト信号
がアクティブのとき前記出力切換回路から出力されたテ
スト制御信号をそれぞれ、本集積回路装置全体の動作を
司とる制御回路に出力する入力切換回路とを有し、 前記テスト制御信号発生回路は前記制御回路の出力信号
にもとづいてテスト制御信号を発生することを持金とす
る。
[Means for Solving the Problems] An integrated circuit device of the present invention includes: a test control signal generation circuit that generates a test control signal when an external test signal is active; and an integrated circuit that generates a test control signal when the test signal is inactive. an output switching circuit that outputs an output signal based on the normal operation of the device to an output terminal, and a test control signal output from the test control signal generation circuit when the test signal is active; Input switching that outputs the input signal input to the integrated circuit device and the test control signal output from the output switching circuit when the test signal is active to the control circuit that controls the operation of the entire integrated circuit device. The test control signal generating circuit is configured to generate a test control signal based on the output signal of the control circuit.

[作用] テスト信号がアクティブレベルのとき試験モートになり
、テスト制御信号が発生して、集積回路装置外に出力さ
れるとともに、制御回路に入力されて次のテスト制御信
号が発生する。
[Function] When the test signal is at active level, it becomes a test mode, and a test control signal is generated and output to the outside of the integrated circuit device, and is also input to the control circuit to generate the next test control signal.

したがって、このテスト制御信号を観測することにより
、熱的加速試験を効果的に、かつ経済的に行なうことが
できる。
Therefore, by observing this test control signal, the thermally accelerated test can be performed effectively and economically.

[実施例コ 次に、本発明の実施例について図面を参照して説明する
[Embodiments] Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例の集積回路装置のブロック図
である。
FIG. 1 is a block diagram of an integrated circuit device according to an embodiment of the present invention.

本集積回路装置1は、出力信号発生器2(例えばメモリ
)と、出力切換回路3と、テスト制御信号発生回路4と
、制御回路5(例えばCPU)と、入力切換回路6と、
その他不図示の回路から構成されている。
This integrated circuit device 1 includes an output signal generator 2 (for example, a memory), an output switching circuit 3, a test control signal generation circuit 4, a control circuit 5 (for example, a CPU), an input switching circuit 6,
It is composed of other circuits not shown.

出力信号発生器2は、制御回路5の制御信号8(命令)
により信号10を出力する。テスト制御信号発生回路4
はテスト信号13かアクティブのとき、制御回路5の制
御信号9にもとづいてテスト制御信号11を発生する。
The output signal generator 2 generates a control signal 8 (command) of the control circuit 5.
outputs signal 10. Test control signal generation circuit 4
generates a test control signal 11 based on the control signal 9 of the control circuit 5 when the test signal 13 is active.

出力切換回路3、入力切換回路6はテスト信号3がイン
アクティブのときそれぞれ出力信号発生器2の出力信号
10、入力信号7を選択し、テスト信号3がアクティブ
のときそれぞれテスト制御信号11、出力切換回路3の
出力信号12(テスト制御信号)を選択し、それぞれ出
力端子(図示せず)、制御回路5に出力する。
The output switching circuit 3 and the input switching circuit 6 select the output signal 10 and input signal 7 of the output signal generator 2, respectively, when the test signal 3 is inactive, and select the test control signal 11, and the output signal, respectively, when the test signal 3 is active. The output signal 12 (test control signal) of the switching circuit 3 is selected and outputted to an output terminal (not shown) and the control circuit 5, respectively.

次に、本実施例の動作を説明する。Next, the operation of this embodiment will be explained.

(1)テスト信号13がインアクティブのとき、この場
合、入力切換回路6は入力信号7を選択し、制御回路5
に出力する。制御回路5は入力信号7に応して出力信号
8.9等を本集積回路装置1内の各部へ出力する。出力
信号発生器2へは出力信号8か出力され、出力信号8に
応じて信号lOが出力信号発生器2から出力され、出力
切換回路3を経て出力端子に出力される。このように、
テスト信号3がインアクティブのとき本集積回路装置1
は通常の動作を行なう。
(1) When the test signal 13 is inactive, in this case, the input switching circuit 6 selects the input signal 7, and the control circuit 5
Output to. The control circuit 5 outputs output signals 8, 9, etc. to each part in the integrated circuit device 1 in response to the input signal 7. An output signal 8 is outputted to the output signal generator 2, and a signal lO is outputted from the output signal generator 2 in accordance with the output signal 8, and is outputted to the output terminal via the output switching circuit 3. in this way,
When test signal 3 is inactive, this integrated circuit device 1
performs normal operation.

(2)テスト信号3がアクティブのときこの場合、テス
ト制御信号発生回路4からテスト制御信号11が発生さ
れ、これが出力信号12として出力切換回路3を経て外
部端子に出力されるとともに、入力切換回路6を経て制
御回路5に入力される。制御回路5はテスト制御信号1
1により各種制御信号8.9等を出力する。テスト制御
信号発生回路4は制御信号9により次のテスト制御信号
11を発生し、以下同様の動作が繰り返される。このテ
スト制御信号11を外部から観測することにより、本集
積回路装置1の熱的加速試験中に本集積回路装置!が正
しく動作しているか否かを判定できる。
(2) When the test signal 3 is active In this case, the test control signal generation circuit 4 generates the test control signal 11, which is output as the output signal 12 to the external terminal via the output switching circuit 3, and the input switching circuit 6 and is input to the control circuit 5. Control circuit 5 receives test control signal 1
1 outputs various control signals 8, 9, etc. The test control signal generation circuit 4 generates the next test control signal 11 based on the control signal 9, and the same operation is repeated thereafter. By observing this test control signal 11 from the outside, it is possible to detect the present integrated circuit device 1 during a thermal acceleration test of the present integrated circuit device 1! You can determine whether or not it is working correctly.

なお、集積回路テスト回路(テスト制御信号発生回路4
)を内蔵するものであれば、切換回路3と6を追加する
だけで容易に実現できる。
Note that the integrated circuit test circuit (test control signal generation circuit 4
), it can be easily realized by simply adding switching circuits 3 and 6.

第2図は本発明の応用例を示すブロック図である。FIG. 2 is a block diagram showing an example of application of the present invention.

本応用例は、基板26上に、第1図に示した、n個の集
積回路装置21.22、・・・、22nと、監視用発光
ダイオード25と、これら集積回路装置21〜2nの出
力を比較し、これらに王政が発生すれば出力を”0”に
して監視用発光タイオード25を発光させる比較器24
が実装されている。
In this application example, n integrated circuit devices 21, 22, . A comparator 24 which compares these and sets the output to "0" and causes a monitoring light emitting diode 25 to emit light if a monarchy occurs.
has been implemented.

本応用例では、複数個の集積回路装置の動作状態を容易
に監視できる利点がある。また、比較器等の集積度が低
い集積回路は一般的に信頼性か高くくり返し利用可能で
あるため、経済性を低下させることもない。
This application example has the advantage that the operating states of a plurality of integrated circuit devices can be easily monitored. In addition, since low-integration integrated circuits such as comparators are generally highly reliable and can be used repeatedly, economical efficiency is not reduced.

[発明の効果] 以上説明したように本発明は、テスト制御信号を集積回
路装置内部で発生させ、同時に外部端子に出力すること
により、経済性を低下させることなく熱的加速試験の効
果を向上させる効果がある
[Effects of the Invention] As explained above, the present invention improves the effectiveness of thermally accelerated testing without reducing economic efficiency by generating a test control signal inside an integrated circuit device and simultaneously outputting it to an external terminal. It has the effect of making

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の集積回路装置のブロック図
、第2図は本発明の応用例を示すブロック図である。 1・・・集積回路装置、 2・・・出力信号発生器、 3・・・出力切換回路、 4・・・テスト制御信号発生回路、 5・・・制御回路、 6・・・入力切換回路、 7・・・入力信号、 8.9・・・制御信号、 10・・・出力信号、 11・・・テスト制御信号、 12・・・出力信号、 21〜2n・・・集積回路装置、 24・・・比較器 25・・・監視用発光タイオード、 26・・・基板
FIG. 1 is a block diagram of an integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an application example of the present invention. DESCRIPTION OF SYMBOLS 1... Integrated circuit device, 2... Output signal generator, 3... Output switching circuit, 4... Test control signal generation circuit, 5... Control circuit, 6... Input switching circuit, 7... Input signal, 8.9... Control signal, 10... Output signal, 11... Test control signal, 12... Output signal, 21-2n... Integrated circuit device, 24. ... Comparator 25 ... Monitoring light emitting diode, 26 ... Board

Claims (1)

【特許請求の範囲】 1、集積回路装置において、 外部からのテスト信号がアクティブのときテスト制御信
号を発生するテスト制御信号発生回路と、 前記テスト信号がインアクティブのとき本集積回路装置
の通常動作にもとづく出力信号を、前記テスト信号がア
クティブのとき前記テスト制御信号発生回路から出力さ
れたテスト制御信号をそれぞれ出力端子に出力する出力
切換回路と、 前記テスト信号がインアクティブのとき本集積回路装置
に入力された入力信号を、前記テスト信号がアクティブ
のとき前記出力切換回路から出力されたテスト制御信号
をそれぞれ、本集積回路装置全体の動作を司どる制御回
路に出力する入力切換回路とを有し、 前記テスト制御信号発生回路は前記制御回路の出力信号
にもとづいてテスト制御信号を発生することを特徴とす
る集積回路装置。
[Claims] 1. In an integrated circuit device, a test control signal generation circuit that generates a test control signal when an external test signal is active; and a normal operation of the integrated circuit device when the test signal is inactive. an output switching circuit that outputs a test control signal output from the test control signal generation circuit to an output terminal when the test signal is active; an input switching circuit that outputs an input signal input to the integrated circuit device and a test control signal output from the output switching circuit when the test signal is active to a control circuit that controls the operation of the entire integrated circuit device. An integrated circuit device, wherein the test control signal generation circuit generates a test control signal based on an output signal of the control circuit.
JP2084008A 1990-03-30 1990-03-30 Integrated circuit device Pending JPH03282381A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2084008A JPH03282381A (en) 1990-03-30 1990-03-30 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2084008A JPH03282381A (en) 1990-03-30 1990-03-30 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPH03282381A true JPH03282381A (en) 1991-12-12

Family

ID=13818574

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2084008A Pending JPH03282381A (en) 1990-03-30 1990-03-30 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPH03282381A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6202184B1 (en) 1997-07-25 2001-03-13 Nec Corporation Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6202184B1 (en) 1997-07-25 2001-03-13 Nec Corporation Semiconductor integrated circuit device

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