JPH03280719A - A/d converter - Google Patents

Abstract

PURPOSE:To improve the linearity and to reduce the distortion factor without need of a complicated and large sized circuit structure by giving a level corre sponding to a correction data read from a storage circuit to a correction capaci tor so as to correct the voltage at one electrode. CONSTITUTION:When the capacitance of capacitors 1a-1e has an error, a voltage VREV applied to a capacitor 10 is varied to obtain a correction level. The correc tion data DREV is stored in an EPROM 13. A correction level in response to the discrimination result of high-order bits is applied to the capacitor 10 for a discrimination period of B3 and LSB to correct the capacitance error of the capacitors 1a-1d. A digital signal DOUT with an excellent linearity is obtained with respect to an inputted analog signal VIN.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a charge redistribution type A/D converter with a binary weighted capacitor array.

(Example) Prior Art FIG. 3 is a circuit diagram of a conventional charge redistribution type A/D converter, and shows the case of a 4-bit configuration.

In the case of a 4-bit configuration, the binary weighted capacitor array (1) has 5 capacitances of 8C, 4C, 2C, C, and C, respectively.
It is composed of two capacitors (1a) to (1e),
The first electrodes of each of the two terminals (la)--(1, e) are connected in common to the ground via the switch (2), and the second electrodes are connected to the respective selector switches. 3a) ~ (3e
). One end of each of the changeover switches (3a) to (3e) is grounded, and the other end is connected to the changeover switch (4). The changeover switch (4) receives the reference voltage VR on one side, and inputs the analog signals V and A on the other side. These switches (3a) to (3e), (4) and (2) are also controlled in accordance with a switching control signal SC from a control logic <5) to be described later.

The first electrode side of the capacity array (1) is connected to the switch (2) and also connected to the inverting input side of the differential amplifier (6).The non-inverting input side of the differential amplifier (6) is grounded. Therefore, the potential Vx on the 1st L pole side of the capacitor array (1>
If is negative, the output of differential a/b (6) is rl, and if positive, it is 10.Then, the output of differential amplifier cross is input to control logic (5>, and digital). Data D and □A are created. Furthermore, in the control logic '7 (5), switching control signals SC, - SC, are created based on the output state of the differential amplifier (6), and each switch <3a) to (
3e) , (and (2) CS is supplied.

Next, the A/D conversion operation will be explained.

FIG. 4 is a timing diagram of the switch operation of FIG. 3. Here, the switching of each switch (3-(3e) and (4) is not shown in FIG. 3 when each switching control signal SC, -SCs is 1 degree. When it becomes L side,
It is assumed that the switch (2) is turned on when the switching control signal SC, is 11''.

First, during the Zumbling period, the switching control signals SC0 to SC become 11, and each switch (3a) to (3e) (4) is switched to the L side, and when the switch (2) is turned on, each capacitor (1 , a)-(le), an analog signal V□ is applied to the second electrode side of each capacitor (la) = (1
e) respectively 8CVrn, 4CVIM, 2CVIN,
The amount of charge of CVl, , CVl,f is accumulated. and,
During the hold period, the switching control signals SC6 to SC5 become r□'' and each switch (3a> to □ (3e)
When the switch 2) is turned on and the switch 2) is turned off, the second electrode side of each capacitor 1a) to (1e) is pulled down to the potential of the first terminal which is in the bloating state.
The potential on the electrode side becomes -VIN. At this time,
The total amount of charge accumulated in Denry (1a) to (1e) is 16CVIN, and this amount of charge should be held.

Next, when the switch (3a) is switched to the L side again during the MSB determination period, the second electrode of the capacitor 1-(la)
3 is applied, and the amount of charge shown in bold is distributed to each capacitor (1a) to (1e) during the hold period. This charge distribution is such that the potentials between the two electrodes of the capacitors (1a) to (IQ) are equal, and the second electrode of the capacitor (1a)
This is done so that the potential of the 1E electrode is higher by 1 than the potential of the second electrode of the capacitors (1b) to (le). Therefore, the capacitance of capacitor (1a) and capacitor (1b)
Since the total capacities of ~(1e) are equal to each other, the 11th
The potential ■8 on the 1i pole side is -V +ll+ Vl/2,
! : This ■ is compared with the ground potential in the differential amplifier (6). Therefore, if the analog signal ■, is higher than ■, /2, v8 will be negative, and the output of the differential ab>・b (6) will be rl, and the control logic (5) will set the MSB to 11.
”. Conversely, if the analog signal Vl is lower than v,l/2, ■8 becomes positive and the MSB becomes 10. The 4 control logic (5) that is determined as follows along with the determination of the MSB,
It generates the switching control signal SC1, and the MSB is "1.
When , the switching control signal SC is maintained as 1 (7
, "0. Noto Port will receive "0.
shall be.

If the MSB is determined to be 1"1., during the continuation<B2 determination period, the switch (3a) remains on the L side and the switch (3b)
is switched to the L side. Then V. -V Ill V
*/ 2 + V R/ 4, and the second bit (B2) is determined in the same way as the MSB determination depending on the sign of V8. That is, if vo is higher than 3VII/4, V8 is negative and B2 is 11. If Vx is lower than 3v1/4, vx becomes positive and B2 becomes rO.

On the other hand, MSB is r6. Judgment! If the switch (3a) is 1. in the following B2 determination period. The switch (3b) is switched to the L side. Therefore, Vx becomes -V I N + V */4, and B2 is determined depending on the sign of this Vx.

Hereinafter, the third bit (
B3) and LSB are determined in the same manner as B2. Therefore, by switching each switch (3a) to (3e) in sequence, Vx is brought close to the ground potential, and the final switch (
The states 3a) to (3e) are digital data D. It will represent UT. Therefore, the control logic (5) collects the MSB-LSB obtained serially in each determination period, and
BIT's digital data D. Output as UT.

Such a charge redistribution type A/D converter is, for example, IE
E E J, 5olid 5tate C1rcu
its, Vol, 5C-10, No. 6,
”A11-MOS Charge Redistrib
tion Analog-to-Digital C
onversion Technigues-Part
1”.

(Problem to be solved by the present invention) In the above-mentioned A/D converter, the capacitor array (1)
Since the relative precision of the capacitance of each capacitor (1a) to (1e) is important, a plurality of unit capacitors with uniform capacitances are formed and these unit capacitors are connected in parallel according to a predetermined capacitance ratio. and each capacitor (1a) ~ (
1e). For example, if the capacitance of a unit capacitor is C, 8, 4, and 2 unit capacitors are connected in parallel to form capacitors (1g), (lb), and (IC).

However, even when each capacitor (1a) to (1e) is configured by connecting unit capacitors in parallel, each capacitor (1a) to (1e) may
There is a problem in that an error occurs in the capacitance of (1e) and the linearity decreases. In particular, when attempting to obtain high resolution by increasing the number of bits, the influence of linearity is large, and there is a risk that the distortion rate will increase even though the resolution is high.

Therefore, the linearity is improved by correcting the capacitance using laser trimming and correcting the data itself using digital correction, but these corrections require expensive manufacturing equipment and large-scale logic circuits. This will lead to higher costs.

Therefore, the present invention uses a simple correction circuit to prevent the linearity from decreasing due to element variations, and achieves high-precision A/
The purpose is to provide a D converter.

(d) Means for Solving the Problems The present invention is intended to solve the above-mentioned problems, and is characterized by a capacitor array in which a plurality of binary-weighted capacitors are arranged in parallel. , means for applying a first reference potential to one electrode side of the capacitor array and applying an analog signal of the converted value to the other electrode side, and applying a second reference potential to the other electrode side of the capacitor array. means and
means for applying the first reference potential for each capacitor to the other one pole side of the capacitor array; and a comparison circuit that compares the potential on one electrode side of the capacitor array with the first reference potential;
a control circuit that creates digital data based on the comparison result of the comparison circuit and switches and controls the supply of each potential from each of the means to the capacitor array; a correction capacitor arranged in parallel with the capacitor array; a memory circuit that stores correction data for correcting a capacitance error of each capacitor of the capacitor array; and a memory circuit that applies a potential to the correction capacitor according to the output of the comparison circuit and the correction data read from the memory circuit to one side of the capacitor array. and a correction circuit for correcting the potential on the electrode side.

(E) Effect According to the present invention, by applying a specific potential to the correction capacitor based on the correction data stored in the memory circuit, a positive or negative charge according to the correction data is applied to the correction capacitor. is accumulated in Therefore, the potential on one electrode side of the capacitor array is raised or lowered depending on the amount of charge that can be stored in the correction capacitor, and the potential error due to the capacitance error of each capacitor in the capacitor array is corrected.

(f) Example An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of the A/D converter of the present invention, and shows a 4-bit configuration. In this figure, the capacitor array <
1) and each switch (2), (3a) to (3e), and (4) are the same as in FIG. 3, and the same parts are given the same reference numerals.

The features of the present invention are correction data D□7 for correcting capacitance errors of each capacitor (18) to (1e) and a differential amplifier (6).
The potential (8) on the first electrode side of the capacitor array (1) is corrected based on the output of the capacitor array (1).

That is, a correction capacitor (
10) is connected, and the correction data calculation circuit (12) is connected to this conte series "00) via the D/A conversion circuit (11,).
is connected. This correction data calculation circuit (12) includes:
Correction data DiiE? EPROM (13
) is connected, and the output of the differential amplifier <6) is also connected, so that a correction potential V-17 is applied to the capacitor (10) for each pin 1- determination operation. E
Correction data l31I stored in PRC)M(13)
Ill18 is written into the E F ROM (13) during an operation test after manufacturing, for example, by an error detection operation to be described later. , - No: -me, change the correction data D□7 to 1T
There is no need to provide the same, and it is possible to simplify the peripheral circuitry when using the A/D converter.

Here, the correction f−D□ is stored in the E P ROM (13)
In addition to 1 and 2, EPROM (Electronic
trially EraI3ab1. e PyoBr
aminahl, eROM) and 0TPROM (Orp
, e Tiff1e Program■abl, eRO
M) A non-volatile memory C on which data can be written can be used in place of the EPOM (13).

Next, I will explain one thing about error detection operation.

Figure 2 is a timing diagram of the switch operation during the error detection operation.
4) is fixed to the H side, that is, the switching control signal SC is 'Od:
m fixed signal, 7s J-r-1 signal vIll is not input.

First, when detecting the error of =7nd-9(10), the switching control signal SC,,SC, becomes 11'', the switch (2) is turned on, and the switch (1a) is switched to the H side. . At this time, the switching control signal SCs is "
OJ, and switches (lb) to (le) are on the H side.

Next, the potential v*mv applied to four capacitors (10)
After fixing Vf to an arbitrary potential Vf, the switch knob (2) is turned down to bring the first electrode side of the capacitor array (1) into a floating state. Therefore, the switching control signal S C+ is changed to "0.
At the same time, the switching control signals SC2 to SC3 are set to 1"1", and the switch (3a) is set to 1, and the switch (3b) is set to 1.
(3e) to the H side7, then the capacitor (1a
) The charges accumulated in the capacitors (1b) to (l
e) is divided by h-1, and the error of the continuity (1a) is distributed to the capacitor (10). That is, condenna (
1a) capacity t (8C) and capacitor (lb) = (R
e) capacity - sum (4(':.

+ 2 C + c + C = 8 c) is equal to 1, then the charge accumulated in the -1 ndenza (1a) is distributed to constituencies (1,b) to (1e), and even in 2, ■8 does not change. However, if the capacitance of -1 ndenza (1a) = (le) includes an error, VT: will vary by that error.
At that time, V x applied to the capacitor (10)
Avoid fluctuations in gv (= Vf)? Let v1 be equal to the initial ground potential, and its variation is the capacitor (1
B) becomes a correction potential Δ■8. The knee correction potential ΔVa is converted into a digital value, and the correction data D□7
(7) is stored in EFROM (13).

Next, when detecting an error in the capacitor (ib), the switching control signal SC, SC- becomes "1", and the switch (
2) is on 1. Then the switch (lb) is switched to 'HJ@. At this time, the switching control signals SC, , SC, ~S
C, is '0. T, switch (la), (lc)”
(le) is on the H side 6 Next, V I and IV are fixed at Vf. No. SC3 to SC8 rl” and 1. The charge accumulated in the capacitor (1b) is distributed to the capacitors (1, C) to (1e).Then, as in the error detection operation of the capacitor (1a), V, cv is set so that Vx becomes the ground potential. (=
Vf) is varied, and the amount of variation is
The correction potential Δ■b becomes.

Thereafter, in the same manner as shown in Figure 21 (knee), move each switch.
Switch (2), (3a) to (3e) - Correction potentials ΔVe, Δ of t(le)<1d)
Obtain Vd. Part 1. So, the quantum correction potential Δ■8~ΔVd
Correction data DIEV indicating DIEV is stored in the EP ROM (13).

Next, the A/D conversion operation will be explained and explained.

The A/D conversion operation is basically the same as in the case of FIG. 3, and the switching operation follows the timing diagram of FIG. 4.

First, each capacitor (la) −(
1e), the electric charge corresponding to the analog signal Vl)I is accumulated, and during the subsequent hold period, the first electrode side of the total array (1) is put into a bloating state so that V +! Hold +.

Then, when the switch (3a) is switched to the H side during the MSB determination period, the capacitor (10) is connected to Vf-ΔvA (
V mgv = Vf - ΔVA) is applied to the capacitor (
Correct the error in 1a). Subsequently, when the switch (3b) is switched to the H side during the B2 judgment period, the MSB becomes 10.
When the capacitor (10) has Vf-Δvb(V l
1lV = Vf - ΔVb) is applied, and the MSB is rl,
When , the capacitor (10) has Vf - ΔV a - Δ
Vb (V**v=Vf-ΔVa-ΔVb) can be applied completely.

Thereafter, in the same manner, during the determination period of B3 and LSB, a correction potential according to the determination result of the upper bit is applied to the capacitor (10), and errors in each of the capacitors (1a) to (1d) are corrected. That is, the correction data calculation circuit (12>)
Based on the determination result of each bit, each capacitor (1a) ~
Add the correction data D□7 of (1d) and convert the added value to V
It is configured to subtract it from the f-equivalent value and give it to the capacitor (10) via the D/A converter (11), and the switches (3a) to (3d) are on the H side in each judgment period. , reference potential V, is applied to the capacitor (1a)
The sum of correction potentials ΔVa to ΔVd of ~(1d) is subtracted from Vf and applied to the capacitor (10). Therefore, in each determination period, correction is applied to the capacitors (1a) to (1d) to which the reference potential (1) is fully applied, and a digital signal with good linearity is generated with respect to the input analog signal vttt. You can get UT.

In this embodiment, a case of a 4-bit configuration is illustrated, but a 5-bit configuration can be achieved by adding a capacitor or by combining with an A/D converter using other methods, such as a comparison method using a resistor string. The above can be easily achieved.

(G) Effects of the Invention According to the present invention, by incorporating a ROM in which correction data for correcting capacitance errors in a capacitor array is stored, errors can be easily corrected and linearity can be improved. It is possible to reduce the distortion rate. In addition, since there is no need to detect errors in the capacitor array every time an A/D conversion operation is performed,
The rise of the A/D converter becomes extremely fast, peripheral circuits for error detection can be omitted, and a reduction in circuit scale can be expected. Therefore, an A/D converter with excellent linearity can be realized without requiring a complicated and large-scale circuit configuration.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of the A/D converter of the present invention, Figure 2 is a timing diagram of error detection operation, Figure 3 is a circuit diagram of a conventional A/D converter, and Figure 4 is A/D conversion operation. FIG. (1) Capacity array, (1a) to (le) (10
)... Capacitor, (2) (3a) to (3e),
(4)...Switch, (5)...Control logic, (6)...Differential amplifier, (11)...D/A
Converter, (12>... Correction data calculation circuit, (13)
)...EPROM.

Claims (2)

[Claims] (1) A capacitor array in which a plurality of binary-weighted capacitors are arranged in parallel, and a first reference potential is applied to one electrode side of this capacitor array, and an analog value of the converted value is applied to the other electrode side. means for applying a signal; means for applying a second reference potential to the other electrode side of the capacitor array; means for applying the first reference potential to the other electrode side of the capacitor array for each capacitance; a comparator circuit that compares the potential on one electrode side of the capacitor array with the first reference potential; and a comparator circuit that creates digital data based on the comparison result of the comparator circuit and transmits each potential from each of the above means to the capacitor array. a control circuit for switching and controlling the supply, a correction capacitor arranged in parallel with the capacitor array, a storage circuit for storing correction data for correcting the capacitance error of each capacitor in the capacitor array, and an output of the comparator circuit and An A/D converter comprising: a correction circuit that corrects the voltage on one electrode side of the capacitor array by applying a potential to the correction capacitor according to correction data read from the storage circuit. (2) The A/D converter according to claim 1, wherein the memory circuit is a read-only memory in which data can be written.