JPH03287291A - Driving circuit of image display device - Google Patents

Abstract

PURPOSE:To display a high-definition image by sampling and holding the image signal of a data line by using a sampling signal of logic between the output of a common shift register and the polyphase clocks of two systems when the image signal is supplied to column electrodes of the image display device. CONSTITUTION:Sample-and-hold circuits 6 - 10 and 11 - 15 form the two systems and half-bit shift registers 1 and 2 are connected in stages and used in common between the systems. A clock of one phase is frequency-divided to generate the transfer clock and polyphase clock of the shift registers 1 and 2; and the image signal of the data line is sampled and held by using the logic signal between the outputs of the shift registers 1 and 2 and the polyphase clocks of the systems, so that even when the number of column electrodes increases, the image signal is sampled and held with the sampling signal generated by using the shift registers 1 and 2 operating with a clock of frequency a half or less than the conventional one and a logic circuit. Consequently, the high- definition image signal can be driven.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a drive circuit for an image display device in which a liquid crystal is sandwiched between substrates and the liquid crystal is driven by an active element for each pixel.

[Prior Art] FIG. 18 shows a conventional drive circuit for an image display device having a shift register and a sample-and-hold circuit. (11
7) - bit shift registers are connected in multiple stages, and each shift register output is (11, D, (21, D, (3
), . . ., the image signals DA, DB, of the three data lines are
Sample and hold De sequentially. At the timing shown in the timing chart in Figure 20, (1) is 1' (vo
, ), the data switch (118) is turned on and the image signal at that timing is sampled into the data capacity (119).

D, (1) turns off (11g) at °O' (vBB) and holds the sampled image signal at (119). The sampled and held image signal is buffered and output from a buffer amplifier (120). The enable signal W is “1° closed transfer switch (12
1) to each column electrode of the image display device, D(1)',
Image signals D(2), D(3), . . . are supplied simultaneously. FIG. 19 is a circuit diagram of a 1-bit shift register. Clock controlled inverter (122)
, (127) are simultaneously on or off, and similarly (1
24) and (125) are turned on or off at the same time. When the clock CK is 1° (VDD), the data D is (122
), as well as (126) and (127
) holds the output signal Q up to that point, and GK becomes 'O'.
(vss), the inverted clock is set to “1” by (128).
゛, and the data entered from (122) is (123).

While holding by (124), (125)
.

(126) to the output Q. As shown in FIG. 20, the shift register transfers the data Dll using the clock CL, sequentially at each clock cycle (1).

D, , (2), Dyo (3), . . . are 1°. In an image display device, drive circuits for column electrodes such as those described above are mounted on the top and bottom of the substrate, with odd-numbered column electrodes supplying image signals from the upper drive circuit, and even-numbered column electrodes supplying image signals from the lower drive circuit. A configuration is taken. 20th in the upper drive circuit
When the timing shown in the figure is used, the lower drive circuit uses data and a clock delayed by half a cycle of the clock CL, that is, an inverted clock.

Overall, the image signal is sampled every half cycle of the clock.
Hold. In displaying television images, a simple line sequential driving method is usually used. - In the horizontal scanning period, the image signal of the pixel group of one row of the image display device is updated, and in one field period of the NTSC television signal, the pixel group of 240 rows of one frame of the image display device is driven.

[Problem to be Solved by the Invention 1] In a high-definition image display device in which the number of rows is doubled to 480 and the number of columns is 480 or more, the image of a group of pixels in one row is displayed in half the horizontal scanning period. A double-speed line sequential method is used in which the signal is updated and two rows of image groups are driven in a -horizontal scanning period.

For a pixel arrangement that has 480 rows of pixels and is shifted from row to row like a triangular arrangement, the conventional column-side drive circuit requires twice as many TABs and ICs with integrated circuits mounted on flexible substrates. It is necessary to sequentially supply the image signals sampled and held during the horizontal scanning period to the same column electrode from different TABs and ICs every half of the horizontal scanning period, and the configuration of the drive circuit is It is complicated and difficult to implement, and has problems that make it difficult to realize a high-definition image display device.

[Means for Solving the Problems] The present invention makes it possible to use as many ICs as the number of terminals required to supply signals to column electrodes without increasing the number of TABs and ICs that drive the image display device. Another object of the present invention is to obtain an integrated circuit for driving an image display device which can accommodate both the simple line sequential method and the double speed line sequential method by keeping the number of elements included in the IC lower than the multiple. To achieve this purpose, the drive circuit of the present invention has two sample-and-hold circuit systems, a shift register of half-bit shift registers connected in multiple stages to be common to each system, and a one-phase clock frequency divided. The transfer clock of the shift register and the multi-phase clock are created using the shift register, and the image signal of the data line is sampled and held using the logic signals of the output of the shift register and the multi-phase clock of each system. The gist of this technology is to sample and hold image signals using sampling signals created using shift registers and logic circuits that operate at a clock frequency less than half that of conventional systems, and drive high-definition image display devices. .

FIG. 1 is a configuration diagram of a drive circuit of an image display device according to the present invention. The shift register that transfers the timing signal necessary to create the sampling signal that samples and holds the image signal is a half-bit shift register as shown in 1) and (2), with the horizontal scanning start signal D6 as the data input. are connected in multiple stages and are common to each system. (3) divides the one-phase clock CL by 1/N, and the shift register transfer clock φ3. φ2. φ3. ..., create an N-phase polyphase clock that is the timing signal necessary to create the sampling signal of one system, and (4) use the one-phase clock CL' to sample the other system. It creates an N-phase multiphase clock that serves as the timing signal necessary to create the signal. (4) can have the same configuration as (3). The reset signal R is used to initialize the frequency divider circuit during the horizontal retrace period, and P is used to select the output pulse width of the sampling signal. A logic circuit (5) creates a sampling signal from the output of the shift register (1) and the multiphase clocks (3) and (4). Data switch (6) with that sampling signal,
Turn on and off (11), data capacity (7), (1
2) Sample and hold the image signals DA, D'' on the data line.

- After storing the image signals of the horizontal scanning period in each data capacity,
Enable signal W during horizontal retrace period. '1' (
Transfer switch (8) in synchronization with Vflfl)
, (13) is turned on, and the buffer amplifier (9) is turned on.

The signal is transferred to the input capacitor (14) and converted into a signal with low output resistance by a buffer amplifier. Two systems of buffer amplifiers (9) and (1) are located at the same position in terms of the order of sampling signals.
The output of 4) is led to one terminal via select switches (10) and (15) controlled by select signals W and W'', respectively, and is supplied to the column electrode as D(1). (6 ) to (10) are sample-and-hold circuits of one system, and (11) to (15) are sample-and-hold circuits of the other system. Signals w, , w, and w' are sent to the level conversion circuit (16 ) corresponds to 'O', '1' Vss, V
The signal potential of no is VBB, V. 0 and opens and closes the transfer switch and select switch of each system. The data lines on which the image signals are sampled and held are: one system is the image signal corresponding to red (R), green (G), and blue (B) [IA, DI', DC three data lines, the other is DA'IIB' corresponding to the three colors with similar families
, D", and are wired individually for each system inside the integrated circuit. 03 is the buffer output of the shift register at the final stage of the integrated circuit, and becomes the data input for the next integrated circuit. Signals: Voo, Vs-, Van
(Vn+,>Vss;i:Vall) is a power input that drives the circuit.

[Function] In the present invention, the sample-and-hold circuit is configured as one system in the integrated circuit, and the shift register is a multi-stage connection of half-bit shift registers to be common to each system, thereby eliminating the shift of the conventional drive circuit. The number of elements is equal to or less than that of a resistor. Input a single-phase clock, divide it to create a shift register transfer clock and a multi-phase clock, and use a sampling signal based on the logic of the shift register output and each system's multi-phase clock to generate an image signal on the data line. Since the data is sampled and held, the speed of the transfer clock is low and a single-phase clock is required, which simplifies signal processing in the drive circuit. sample·
By having two hold circuits, it is possible to drive the image display device in a double-speed line sequential method, and the select signal W or Wo
If one system of image signals is supplied to the column electrodes during one horizontal scanning period, driving can be performed in a simple line sequential manner.

[Embodiment] FIG. 2 is a circuit diagram for creating clocks CL and CL', which are the basis for creating two-system circuit transfer or multiphase clocks, in the drive circuit of the image display device of the present invention. The one-phase clock CL enters one of the RS flip-flops (18) through an inverter (17), and enters the other (18) of the RS flip-flop.
19) receives a reset signal R8. Therefore, the reset signal R during the horizontal retrace period outputted through (20) is R8.
is "1" for a period of "1", and after R becomes "Oo", CL becomes "Oo" after becoming 0°.CL.

is input to the NAND (21) together with the output of (19), and CL is output through the inverter (22), which becomes the reference clock for one system. The output of (21) is passed from the inverter (23L delay circuit (24) to the clock-controlled inverter (25), or the inverter (27), and the clock-controlled inverter (28), and then passes through the inverter (26) to the other side. It becomes the reference clock CL' of the system. (25) or (27) depending on "O" and '1° of the clock state setting manual S.

1 2 (28) routes are selected. When S is °O°, (25) is selected by the inverted output of (29), and C
The clock CL' is delayed by a certain period of time from the clock CL'.

The delay circuit (24) connected to other than the integrated circuit is simply (
23) and (25), it becomes the same phase as CL. When S is 1°, (28) is selected, and the signal delayed by the inverter (27) by a constant time plus a half cycle of the clock is set as CL'. If the drive circuits of the image display device are arranged on the top and bottom of the board with odd numbered columns and even numbered columns, the inverted clock of CL1 is input to the drive circuit on the opposite side, so the pixel pitch corresponds to a half cycle of the clock, and the CL1 If the same signal is used for and CL', the arrangement will be such that there is no pixel shift for each row, and if CL' is a signal delayed by a certain period of time, for example, 1/4 clock period, the pixels will be arranged with a half-pitch shift every other row. A signal delayed by 3/4 clock period is selectively used to drive an arrangement shifted by one and a half pitches every other row.

FIG. 3 is a circuit diagram for generating three-phase clocks for the drive circuit of the image display device of the present invention. Set clock CL to 1 with (30)
Divide the frequency by 72, pass through exclusive OR (34),
- It is used as a clock for an l/3 frequency divider circuit consisting of three stages of bit shift registers, and the output of (34) is input to (31) and (33), and the inverted signal of (35) is input to (32). are doing. (34) has (30), (3
The inverted signal of the output of step 3) is input. If P is “Oo, then (45) gives (39), (40), (41)
The switch is turned on and exclusive or (42)
, (43) and (44) respectively include QA and QC,
QB and QA.

Q, and Q8 are input. Subscripts A, B, and C represent shift registers (31), (32), and (33), respectively.

When P is 1°, (36), (37), (38)
The switch of (42), (43), (4
The inputs of 4) are QA and QB, Qi and Qc, and Q
c and QA. Output α, α2. As shown in Fig. 5, α3 has three periods of the clock CL as one period, and when P is O゛, the period of °l° is two periods of CL, and when P is 1°, it is one period, respectively. The signal is shifted by one cycle of CL.

R is the same signal as the enable signal or a signal that becomes 1° near the beginning of the horizontal scanning start signal DB, and (30) to (
33) is being initialized.

FIG. 4 is a circuit diagram of a shift register and a logic circuit that generate a sampling signal for sampling and holding the image signal of the drive circuit of the image display device of the present invention. (47), +
48), (49), and (50) are data input sections, where φ1, which is the inverted signal of D3 according to (46), is written at 1°, and φ1 is held at O′. (50) , (
51), (52), and (53) are half-bit shift registers in the first stage of the connected shift registers, which operate with clock φ1, and the clock in the second stage is φ2.3.
The 3rd tier is φ3. The 4th tier is φ1°... The output of the first stage shift register and the output of the NOR (54) and (58) of α1 and α1 among the three-phase clocks of each system are expressed as (55) to (57) and (59) to (6), respectively.
In step 1), the level is converted from LD-VSS to voo-vtts to create sampling signals of Ds(t), o', and (+).

FIG. 5 is a timing chart of the drive circuit shown in FIGS. 2-4. Time that CL' is delayed with respect to CL, D', (1), D', (2), D'5 (3), -
From Ds(1), DI+(2), Ds(3),..., the sampling timing of 1° (VDD) is delayed, P is Oo and 2 cycles of CL, and P is 1° and 1 This is the periodic sampling period. The sampling timing of each system of sampling signals is sequentially shifted by one cycle of the clock CL.

FIG. 6 is a circuit diagram of a shift register and a logic circuit for generating a sampling signal for sampling and holding an image signal, in a second embodiment of the drive circuit for an image display device according to the present invention. The manual part of the data Dg is the same as that shown in FIG. 4, and the transfer clock of the shift register to be connected is one phase and φ. (62) and (63) are half-bit shift registers in the first stage and second stage, respectively. Of the output of the first stage shift register and the two-phase clock of each system, α
1 and α1° output Q of Noah (64) and (65),
(1), Q', (1) creates the timing for sampling the first column of the image display device. This signal is applied to the sample and hold circuit as Vno-V. or 5 6 raV. The level is converted to D-Vllll and output.

FIG. 7 is a timing chart of the drive circuit of FIG. 6. The rise of CL' from "Oo" to "1" is delayed by 374 cycles from the rise of CL, and the transfer and each two-phase clock φ1, a+, α2α, °, α2° have two cycles of CL as one cycle.

Q” s (1), Q’ s (2), “’ is Q
From s (1), Qs (2), .=, the sampling timing is delayed by 374 cycles of CL.

FIG. 8 is a circuit diagram for generating a multiphase clock for the other system from a multiphase clock signal for one system. The clock αi (i=1.2...) of one system is (75),
Through the half-bit shift register (76) and (77) and the buffer (78), an inverted signal αi° delayed by the delay time of CL' with respect to CL is output. The clocks CP and CP of this shift register are a half-bit shift register consisting of 66), (67), and (6B) with Vllll as data, and the output of (67) as (69).
), (70) and from NAND (71) with CL' as one input, (72) or (73), (74
) is obtained through an inverter. (67) is a NAND, and CL' is one of the clocks, and cp and cp have a common clock as shown in the shift registers (66) to (68) and (75) to (77).

FIG. 9 is a timing chart of the circuit of FIG. C
' o ' (Vllll
l) to 1° (cp becomes 1° in synchronization with the rise to Vool, input “0°” from (66), (66)
~ (71), (72) propagation time delayed from 1'
Changes to O'. When CL' is °0'', CP is obtained by (71)
The output of remains at 0, and (67) and (68) change the output of (67L and (70) from Oo to 1, and wait for CL'' to change from 0 to 1. By repeating these operations, a clock signal as shown in the figure is output.

FIG. 10 is a circuit diagram of a shift register and a logic circuit for generating a sampling signal for sampling and holding an image signal in a third embodiment of the drive circuit for an image display device according to the present invention. The input portions of data D and l are the same as in FIG. 4, and the transfer clock of the connected shift registers is one phase and φ1.

(75) and (76) are half-bit shift registers in the first and second stages, respectively. The output Y (1) of the first stage shift register and the NOR (77
) to (82) outputs Q, (I), Q', (I) (I=
1.2.3), create the sampling timing for the first row, and set the output Y(2) and βi of the second stage shift register,
The outputs Q, (J) of Noah (83) to (88) with βi°,
Q'11(J) (J・4,5°6) is used to create the sampling timing for the fifth column. Similarly, from the second stage onward, the outputs of the odd-numbered shift registers and αi, αi°
, the sampling timing is created by the outputs of the even-numbered shift registers and βi, βi°.

FIG. 11 shows six-phase clocks α, ~α3. It is a circuit diagram for making β1 to β3. 1/ shown in Figure 3 (30) to (35)
The respective outputs of (31), (32), and (33) of the divide-by-6 circuit are QA, QA, Q,, Q,, Qc,
Signals are generated using QC. When P is °O° (10
7), (95) to (100) are selected, and (101)
qA and QC, Qn and QA respectively by ~(106)
, Qc and QI1, and when QAP is 1°, (89) to (9
4) are selected, QA and Q, , QIl and Q, respectively.
, Q, and QA, QA and Q,, QB and Q. , becomes the NAND output of Qc and QA.

α1°, α2°, α3°, β +, β2°, β3′ are made in the same manner as in FIG.

FIG. 12 is a timing chart of the drive circuits shown in FIGS. 10 and 1. Y(1), Y(2), . . . have six cycles of clock CL, and the period of O° is α1. α2. α
3 is the output of odd-numbered shift registers from °1° to “O”.
synchronized with the change to o, sequentially shifted by one period of CL, P
When P is "0", there are 2 periods of CL, when P is "1°, it is 1 period, and O
°. β1. β2. β3 is synchronized with the change of the even stage shift register from °1° to "Oo. Therefore, qs(1)+qs(2), -1s), -...
is a sample whose period of “l” is sequentially delayed by one period of Ct.
9 Bling signal is activated.

FIG. 13 is a circuit diagram of a shift register and a logic circuit for generating a sampling signal for sampling and holding an image signal, in a fourth embodiment of the drive circuit for an image display device according to the present invention. The clock of the shift register that transfers data D3 is one phase and φ1, and (89) and (91) are the first stage,
This is a second stage half-bit shift register. 1st stage,
2nd stage output Y(1), output of NAND (90) of Y(2) Z(1), or output of (90) as ψ, and NOR(9
9) and a delayed output Z''(1) through a flip-flop consisting of Noah (100) and (101);
Multiphase clock α.

α1°, α2. A NOR logic signal is created from α2°, αa, and α3°, and a sampling timing signal Qs (
I), Qs'(I) (I=1.2.3). (
100).

(101), the R/S flip-flop consists of Y(1
), Y(2) are both °1°, that is, the input of (100) is °1° at the timing when Z(1) is "0" and ψ is 0.
As a result, the output Z''' (1) becomes 0°, and the outputs z(2) and ψ1 of the NAND (92) of the second and third stages Y(2) and Y(3) both become At the timing of 0°, the output of Noah (102), that is, the input of (101) becomes 1°, and the output of 21 (1) returns to 1°.

(93), (94), and (95) are each α8
．． α1°.

Noah of α2 and Z(1), (96), (97),
(98) is α2°.

α3. It is a NOR of α3° and 2′″ (1). After receiving the output of the second stage shift register (91), Z (2)
, Create a timing signal for Z"" (2) (92),
(102), (103).

(104) are first-stage logic circuits (90).

Corresponding to (99), (100), (101),
The same circuit configuration is repeated from the third stage onwards. α8. α2
．． α3 is composed of the circuit shown in Figure 3, (101), (1
04) input Z”(1), Z”(2) from O゛ to °1
The signal to be returned to
A signal is used that changes ψ from 1' to 0°, but instead, the rise from ψ1 and from 0° to 1° is the same, and ψ
, a signal whose timing of falling from 1° to °O° is earlier may be used.

2. FIG. 14 is a timing chart of the four drive paths shown in FIG. 13. The output Z(I) from the shift register is synchronized with the rising edge of the transfer clock φ1, and the period of °0° is three cycles of CL, and the clock ψ1 used to delay Z(I) is synchronized with the rising edge of the transfer clock φ1. Change in sync, Z”
(I) is synchronized with the falling of ψ, and the period of O° is CL'
There are three periods, and ψ and α2′ have the same timing when P is 1°. As shown in FIGS. 2 and 3, the clock ψ1 used to delay the output of the shift register is used as a base for creating the common shift register transfer clock φ1 with the same timing as QA. It is created using a clock CL' that is the same as the phase clock CL or is delayed. Therefore, as already mentioned above, the delayed clock CL' is produced by delaying the base one-phase clock CL by a certain period of time, or by a period equal to the certain period plus a half period of the clock. α,.

G2 G3. Qllα2. α3° has three periods of CL' as one period, and when P is Oo, two periods of CL and CL' are 1
．． When P is 1°, it is 0° for one period. Therefore, QS(1), Q, (2), Q, (3), and Qs'(1)
,Qll(2),Q,' f3) is P's °O° or 1°
Correspondingly, the l° period is two cycles or one cycle of CL and CL', and the sampling signals are successively delayed by one cycle of CL and CL'.

FIG. 15 is a circuit diagram of a shift register and a logic circuit for generating a sampling signal for sampling and holding an image signal, in a fifth embodiment of the drive circuit for an image display device according to the present invention. The clock of the shift register that transfers the data D's has one phase and is φ1, (105), (106),
(107) and (IO2) correspond to (89), (90), (91), and (92) in FIG. 13, respectively. (1(15), (l[17), the clock input to the half-bit shift register is reversed in the odd and even stages.The output Y( 1), the output of NAND (106) of Y(2) Z(1) or the output of (106) is further passed through a half-bit shift register (109) at a timing of ψ of l°, and the output is delayed. Z'(1) and multiphase clock αh a+, α2I G2.α3I G3
Create a Noah logic signal from
It is said that (111), (112), (113)
are each. The operation timing of this drive circuit is
It is the same as FIG. 14 except that the inverted signal ψ1 of ψ1 is used to delay the output of the common shift register. The clock ψ1 used to delay the output of the shift register is the same as the one-phase clock CL from which the transfer clock φ1 is created, or is a delayed clock CL'.
Similarly to the fourth embodiment, CL' is created with a delay from CL by a fixed time or a time equal to the fixed time plus a half cycle of the clock. A shift register (109) that delays the output from the common shift registers (105), (107).

(110) replaces the data input with Z(I) and inputs teY(I)
4, and instead of the clock ψ1, we use a clock φ2° which has the same period as φ and is delayed from φ1 by a time equal to the delay time of CL and CL' plus one period of CL, and the outputs Z"CI) and Z"(
I + 1) (7) A similar function can be achieved by inputting the output of NAND to a NOR that creates a logic signal with a multiphase clock like Z (Il). In that case, φ2
Qll in Figure 3 is set to a signal with the same timing as the delayed signal using the circuit in Figure 8, and the clock input is reversed between odd and even stages, (109), (110
), how the clock φ2' enters into (105), (
The method of inputting the clock φ to 107) is the same.

FIG. 16 shows image signals DA, DB, DC, D'', D'', D'', enable signals W, select signals w, w', and row electrode signals G1 of the double-speed line sequential method of the image display device according to the present invention. , shows the timing of G2 and G3.■β~■
Following the sampling period of one horizontal scanning period of the image signal at the potential α, there is a horizontal retrace period in which Wo is 1°, and the sampling image signal of one of the two systems is supplied to the column electrodes W There is a period of 1 degree, and a period of 1 degree of Wo, which supplies the sampling image signal of the other system to the column electrode, and Wo is an inverted signal of W. - row, second row, As shown in the signals G1, G2, and G3 of the row electrodes in the third row, half of one horizontal scanning period is the selection period for the pixel group in each row, and the pixel groups in the next row are sequentially selected during the same period as the selection period. Selected.W is 1° for odd rows, Wo is 1° for even rows.
The image signal for the period ゛ is input to the pixel. The image signal is inverted for each field and AC drives the liquid crystal of each pixel.

FIG. 17 shows the timing of the simple line sequential method of the pixel display device according to the present invention. - w, w for each horizontal scanning period
' are alternately set to 1°, and the signal on the row electrode has a selection period in which the potential is at VC+Q during the -horizontal scanning period, the rest of the -field period is a non-selection period at the potential at V-, and -horizontal scanning Pixel groups in successive rows are selected in each period.

[Effects of the Invention] The drive circuit for the image display device of the present invention has a shift register and a sample/hold circuit, and for supplying image signals to the column electrodes of the image display device, a common shift register output and two systems are used. The image signal on the data line is sampled using the sampling signal based on the logic of the multi-phase clock.
It is designed to hold the image display device, and can drive both a simple line sequential type image display device and a double speed line sequential type image display device. A single-phase clock is frequency-divided within an integrated circuit to create transfer and multi-phase clocks, which have sufficient resolution to drive a high-definition image display device while maintaining a low clock frequency. The configuration allows easy setting of sampling timing for the two circuits corresponding to the pixel arrangement of the image display device, and the shift register common to each system is constructed by connecting half-bit shift registers in multiple stages. Since the output of the shift register is divided and used by a multi-phase clock, the number of integrated circuit components can be reduced to the same level or less than conventional ones, and it is superior in terms of functionality and quality.

7

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a drive circuit of an image display device according to the present invention. Figure 2 is a circuit diagram for creating clocks CL and CL'' which are the basis for transferring two circuits or creating multi-phase clocks in the drive circuit of the image display device of the present invention, and Figure 3 is a three-phase clock. 4 is a circuit diagram of a shift register and logic circuit that generates a sampling signal for sampling and holding an image signal, and FIG. 5 is a timing chart. FIG. FIG. 7 is a circuit diagram of a shift register and a logic circuit that generate a sampling signal for sampling and holding image signals in the second embodiment of the circuit, and FIG. 7 is a timing chart. FIG. 8 is a driving diagram of the image display device of the present invention. FIG. 9 is a timing chart of a circuit for generating a multi-phase clock signal of one system from a multi-phase clock signal of the other system. FIG. FIG. 11 is a circuit diagram of a shift register and a logic circuit for generating a sampling signal for sample-holding an image signal, and FIG. 11 is a circuit diagram for generating a six-phase clock, and FIG. 12 is a timing chart. FIG. 13 is a circuit diagram of a shift register and logic circuit that generates a sampling signal for sampling and holding an image signal, and FIG. 14 is a timing chart of a fourth embodiment of the drive circuit for an image display device of the present invention. FIG. 15 is a circuit diagram of a shift register and logic circuit that generates a sampling signal for sampling and holding an image signal in a fifth embodiment of the drive circuit for an image display device according to the present invention. Fig. 17 is a timing chart of the double-speed line sequential method of the image display device. Fig. 18 is a driving circuit diagram of a conventional image display device, and Fig. 19 is a timing chart of a 1-bit shift register. The circuit diagram and Figure 20 are timing charts. (1), (2): Half-bit shift registers in the first and second stages of the shift registers common to each system (
3) Frequency division and clock generation circuit that generates multiphase clocks for one system, (4): Clock generation circuit that generates multiphase clocks for the other system, (5): Shift register Logic circuit that creates sampling signals from output and multiphase clocks, (61, (11): data switch, (7), (12): data capacity, (8),
(13): Transfer switch, (9),
(14): Buffer amplifier, (10), (15)
:Select switch, CL, for selecting one of the two systems of sampling image signals. CL': One phase clock input of two circuits, DS
: Common shift register data horizontal scanning start signal, DA, l) B, DC, image signal of data line of one system, n'', DB', D'': image of data line of other system signal, Wo=enable signal,
W, W': Select signal that controls the select switch. 1 ” □n42對4z謬行ξ法4试 111111111111111 O4 GI valley ab 2浣8=3 ambiance output ≧ ≧ ≧ 8 ships

Claims (1)

[Claims] 1. In a drive circuit for an image display device having a shift register and a sample-and-hold circuit, the sample-and-hold circuit has two systems, and the shift register has half-bit shift registers connected in multiple stages to each system. Common, one-phase clock is divided to create shift register transfer clock and multi-phase clock, and the image signal of the data line is sampled using the logic signal of the shift register output and each system's multi-phase clock. - A drive signal for an image display device characterized by being held. 2. The image described in item 1 in which a multiphase clock for the other system is created using a clock that is the same as or delayed from the single-phase clock that is the basis for creating the multiphase clock for one system. Display device drive circuit. 3. The drive circuit for an image display device according to item 2, wherein the delayed clock is produced by being delayed by a certain period of time or a time equal to the certain period plus a half period of the clock from the base one-phase clock. 4. The sampled data is transferred to the buffer amplifier in synchronization with the enable signal, and the outputs of the two buffer amplifiers at the same position in terms of the sampling order are selectively output to one terminal. A drive circuit for an image display device as described in 2. 5. The drive circuit for an image display device according to item 1, wherein the data line through which the image signal is sampled is individually wired for each system within the integrated circuit. 6. The signal for sampling and holding the image signal on the data line is a logic signal of a common shift register output and a multiphase clock, or a logic signal of a shift register output delayed by passing it through a flip-flop and a multiphase clock. The driving circuit for an image display device according to the first term, the second term, the third term, the fourth term, or the fifth term, which uses a logic signal. 7. The signal for sampling and holding the image signal on the data line is a logic signal of the output of a common shift register and a multiphase clock, or the output of the shift register is further passed through a half-bit shift register and the output is delayed. The driving circuit for an image display device according to the first term, the second term, the third term, the fourth term, or the fifth term, which uses a logic signal with a multiphase clock. 8. The clock used to delay the output of the shift register is the same as the one-phase clock that is the basis for creating the common shift register transfer clock, or is created using a delayed clock.Section 6 Or a drive circuit for an image display device according to item 7. 9. The drive circuit for an image display device according to item 8, wherein the delayed clock is produced by delaying the base one-phase clock by a certain period of time, or by a time equal to the certain period plus a half period of the clock.