JPH03286497A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To set the threshold value of a memory cell within a prescribed range by providing a write verify control circuit to confirm a data write state by impressing a prescribed write verify potential to the control gate of the selected memory cell. CONSTITUTION:A control gate control circuit 6 outputs prescribed control signals to the control gate line of a memory cell array 2 corresponding to respective operations such as data write, erase, read and verify. After executing a write operation according to data to be written latched by a data latch circuit 5, the write verify operation is executed by the control circuit 6. In such a case, when all the write data are set within desired threshold destribution, the signal of data write end is obtained by a verify end detection circuit 9. Thus, the threshold value of the memory cell in the data write state can be set within the prescribed range.

Description

Detailed Description of the Invention [Object of the Invention (Industrial Application Field) The present invention provides an electrically rewritable non-volatile semiconductor memory device W.
(EEFROM), and particularly relates to an EEFROM having a recell array having a NAND cell structure.

(Conventional technology) NAND, which can be highly integrated, is one of the EEFROMs.
Cell-type EEPROMs are known.

In this method, a plurality of memory cells are connected in series so that adjacent cells share their sources and drains, and are connected as a unit to a bit line. Memory cells are usually FETMO in which a charge storage layer and a control gate are stacked.
It has an S structure. The memory cell array is integrated within a p-type well formed in a p-type substrate or an n-type substrate.

The drain side of the NAND cell is connected to a bit line via a selection gate, and the source side is also connected to a source line (reference potential wiring) via a selection gate. The control gates of the memory cells are arranged continuously in the row direction to form word lines.

The operation of this NAND cell type EEPROM is as follows. The data write operation is performed in order from the memory cell located farthest from the bit line. A high voltage Vl)p (about -20V) is applied to the control gate of the selected memory cell, and an intermediate potential V, pp)4 (- 1
Approximately 0V) is applied to the bit line, and OV is applied to the bit line according to the data.
Or give an intermediate potential. When Ov is applied to the bit line, the potential is transmitted to the drain of the selected memory cell, causing electron injection from the drain to the floating gate. This causes the threshold value of the selected memory cell to shift in the positive direction. This state is set to "1", for example. When an intermediate potential is applied to the bit line, no electron injection occurs;
Therefore, the threshold value does not change and remains negative. This state is “
0".

Data erasure is performed simultaneously on all memory cells in the NAND cell. That is, a high voltage of 20 V is applied to the p-type well and the n-type substrate with all control gates and selection gates set to OV, bit lines and source lines in a floating state. As a result, electrons from the floating gates of all memory cells are released into the p-type well, and the threshold voltage is shifted in the negative direction.

In the data read operation, the control gate of the selected memory cell is set to OV, the control gates and selection gates of the other memory cells are set to the power supply potential Vcc (=5V), and it is detected whether or not current flows in the selected memory cell. It is done by doing.

As is clear from the above operation explanation, NAND cell type E
In EPROM, unselected memory cells act as transfer gates during write and read operations. From this point of view, a limit is placed on the threshold voltage of a memory cell that has been programmed. For example, the preferred range of the threshold value of a memory cell written by 1 degree is about 0.5 to 3.5V. Considering the dispersion,
The threshold distribution after data writing is required to be within a smaller range.

However, in the conventional method of writing data to all memory cells under the same conditions by fixing the write potential and write time, it is difficult to keep the threshold value range after writing "1" within an allowable range.

For example, variations in the characteristics of memory cells occur due to variations in the manufacturing process. Therefore, when looking at write characteristics, there are memory cells that are easy to write to and memory cells that are difficult to write to. Conventionally, in order to sufficiently write to memory cells that are difficult to write to, it is common practice to write to all memory cells under the same conditions, with a margin in writing time. In this case, more data is written to memory cells that are easy to write to than necessary, and the threshold voltage becomes higher than the allowable range.

On the other hand, if the threshold voltage of a memory cell to which O'' has been written or a NAND cell to which data has been erased does not exceed a certain value in the negative direction, this also becomes a problem.

In other words, the threshold value of a memory cell to which "O" has been written changes due to the cell current (read current) when reading data, and as a result, the access time changes.
Affects the specifications of FROM. Also, if the data is not erased sufficiently, the threshold value for the "1" state will become higher than necessary during subsequent data writing.
This will exceed the threshold tolerance.

(Problem to be solved by the invention) As described above, in the conventional NAND cell type EEPROM,
There has been a problem in that it is difficult to keep the threshold value of the memory cell within an acceptable range when erasing or writing data.

The present invention provides a NAND cell-type EE that makes it possible to keep the threshold value of a memory cell in a data erased state within a predetermined range.
The purpose is to provide PROM.

Another object of the present invention is to provide a NAND cell type EEFROM that is capable of keeping the threshold values of memory cells in a data erased state and a data written state within a predetermined range.

[Structure of the Invention] (Means for Solving the Problems) In the present invention, a charge storage layer and a control gate are stacked on a semiconductor substrate, and electrical rewriting is possible by transfer of charge between the charge storage layer and the substrate. In an E/EFROM having a memory cell array arranged in a matrix by connecting a plurality of memory cells in series to form a NAND cell, a predetermined signal is applied to the control gates of all memory cells in a selected NAND cell. It is characterized by having an erase verify control circuit that applies an erase verify potential to confirm the data erased state.

The present invention is also characterized in that such an EEPROM has a write verify control circuit that applies a predetermined write verify potential to the control gate of a selected memory cell to confirm the data write state in addition to the erase verify control circuit. shall be.

(Function) In the present invention, sequentially selected NAs after data deletion are
Execute an erase verify operation in which, for example, OV is applied to all memory cells of the ND cells and read data, and if there is even one NAND cell that cannot be read to "0" within a certain set time, the data will not be erased. judged to be insufficient. In that case, all NAND cells (if data is erased for each block, all NAND cells in that block)
The data erase operation is executed again for the ND cell). Then, the same read operation is performed again.

This operation is repeated, and when the read time of all NAND cells becomes less than a certain value, the data erase operation is completed. By the above control operation, it is possible to obtain a state in which the threshold values of the memory cells in all the NAND cells are smaller than a certain value (in the case of an n-channel, a sufficiently negative state).

This is because the read current of a NAND cell is limited by the memory cell with the highest threshold value among the memory cells included in one NAND cell.

In the present invention, in addition to the erase verify operation, after data is written, the write verify control circuit evaluates the threshold voltage of the memory cell to which data has been written. If there is a memory cell that has not reached the desired threshold value, a write operation is added. After that, the threshold value is evaluated again. This operation is repeated, and when it is confirmed that the threshold values of all memory cells are within a desired tolerance range, the write operation is terminated.

In this way, according to the present invention, the NAND device makes it possible to keep the threshold values of the memory cells in the data erased state and, if necessary, in the data written state, within a predetermined range.
A cell-type EEPROM can be obtained.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a NAND cell type EEFROM in one embodiment.
shows the configuration of In the figure, an address buffer for selecting an address, an address decoder in rows and three columns, and the like are omitted, and only the configuration of parts related to write and erase verify operations is shown. A data read/write circuit 5 and a sense amplifier circuit 1 are provided for writing and reading data into the memory cell array 2.

These sense amplifier circuits 1. The data source circuit 5 is connected to the data source output buffer 4. The control gate control circuit 6 outputs predetermined control signals to the control gate lines of the memory cell array 2 in response to data write, erase, read, and verify operations. During the write verify operation, the data latch circuit 5 and the sense amplifier circuit 2 perform a sensing operation and latch data to be backwritten in accordance with the column address output from the column address generation circuit 7. The data comparison circuit 3 also has the function of comparing and detecting the match between the write data latched by the data latch circuit 5 and the data read by the sense amplifier circuit 1 for each column address during the verify operation, and latching the result. have The output of this comparison circuit 3 is the output buffer 8
The signal is guided to the verify completion detection circuit 9 via the . After a write operation is performed according to the data to be written latched in the data latch circuit 5, a write verify operation is performed by the control circuit 6, and if all the write data is within the desired threshold distribution, The verify completion detection circuit 9 obtains a data writing completion signal. If the data write end signal is not output, the data write operation is performed again and the verify operation is repeated.

Figures 2(a) and 2(b) show one N of the memory cell array.
This is a plan view and an equivalent circuit diagram of the AND cell part, and Figure 3 (
a) and (b) are sectional views taken along line AA' and line BB' in FIG. 2(a), respectively. A memory cell array consisting of a plurality of NAND cells is formed in a p-type silicon substrate (or p-type well) 11 surrounded by an element isolation oxide film 12. In this embodiment, eight memory cells M, to M8 are connected in series to form one NAND cell. Each memory cell has floating data on the substrate 11 via the gate insulating film 13).
14 (14+, 14°, . . . , 148) are formed, and a control gate (16) is formed thereon via an interlayer insulating film 15.
(161, 162, . . . , 16s) are formed and configured. The memory cells are connected in series so that the n-type diffusion layers 19, which are the sources and drains of these memory cells, are shared by adjacent ones. Selection gates 149 and 1 are formed on the drain and source sides of the NAND cell at the same time as the floating gate and control gate of the memory cell, respectively.
69, 14+o, and 16+o are provided. The substrate on which the elements are formed is covered with a CVD oxide film 17, on which a bit line 18 is arranged. The bit line 18 is in contact with a drain side diffusion layer 19 at one end of the NAND cell. The control gates 14 of the NAND cells arranged in the row direction share control gate lines CG, CG2, . . .
, CO2. These control gate lines become word lines.

Selection gates 149, 16. and 14 ro, 16
The selection gate lines SG are connected continuously by 1° in the row direction.

It is arranged as SG2.

FIG. 4 shows an equivalent circuit of a memory cell array in which such NAND cells are arranged in a matrix.

FIG. 5 shows sense amplifier circuit 1° data latch circuit 5. Data comparison circuit 3. A specific configuration of the output buffer 8 portion is shown. The data latch circuit 5 is
Data at an address selected by the logic of the latch signal LATCH and the address a1 is latched into the latch circuit main body LA. The sense amplifier circuit 1 receives the sense control signal 5EN.
The bit line data of the address selected by SE and the logic of address a1 by I is sensed and output. The output of the sense amplifier circuit 1 is compared with the corresponding data of the data latch circuit 5 by the comparison circuit 3, and as a result, it is latched by the latch signals LATCHV, LATCHV. Next, depending on the result, the latch circuit body LA
Output to. and a latch signal LATCHV.

Release LATCHV and prepare for what is selected by the logic of the next address.

FIG. 6 shows a specific configuration of the control gate control circuit 6 in FIG. This control circuit includes a high potential supply circuit 2 that applies a high potential vpp to the selection gate during writing.
1. Similarly, when writing, the intermediate potential V is applied to unselected control gates.
Intermediate potential supply circuit 22 providing ppM, write verify control signal V-VEI? A write verify potential supply circuit 23 that selectively supplies a write verify potential V VER by IFY, a read signal READ, an erase signal ERASE, and an erase verify control signal E-VERI.
It is composed of an erase/continuation control circuit 24 that sets a control gate potential using FY. Such a circuit is provided for each control gate line. The high potential supply circuit 21 is a NAN which takes the logic of the write signal WRITE and the address ai.
E type controlled by D gate day.

It is mainly composed of n-channel switching MOS transistors QEI and E type, a p-channel switching MO8) transistor Qpr, and an E-type, p-channel MO5) transistor QP2 serving as an output buffer. MOS) Between transistors QEI and QPl, MOS
Between the transistor Qp+ and the high potential Vl)I) terminal,
switching MO3) n-channel MOS to protect transistors from high potentials) transistor QDll, respectively
QD2 is provided. These MOS transistors Q p 1+QD2 are of D type. Buffer stage MO
8) Similarly, above and below the transistor Qp+, type D, n
Channel MOS) transistors Q 031 Q D4 are provided. The reason why a p-channel MOS transistor and a D-type, n-channel MOS transistor are used in the output stage is to supply the high potential Vpp to the control gate line without threshold drop. In particular, the MOS transistor QD4 serves to prevent the drain junction of the p-channel MOS transistor QP2 from becoming forward biased when a positive potential is supplied to the control gate line from another circuit. Similarly to the high potential supply circuit 21, the intermediate potential supply circuit 22 also includes a NAND gate G2 and an E-type, n-channel switching MOS transistor Q8 controlled by the NAND gate G2.
□, an E-type, p-channel switching transistor Qps, a p-channel MOS transistor QP4, which serves as an output buffer, and D-type, n-channel MOS transistors Qos to QD8.

The erase/read control circuit 24 includes a NAND gate G3. G
9. Erase signal ERASE and erase verify control signal E-
NOR gate G6 that takes the sum of VERI PY, NAND
A NAND gate selects the output of gates G5 and G6, and an E-type, n-channel MOS for switching controlled by these NAND gates and G, respectively.
Transistors QE3 and E type, p-channel MOS transistor QP5, MO3 for switching these transistors, and D type for protection provided between the transistor and the control gate line.

It is composed of an n-channel MOS transistor QDIOr QD9.

The write verify potential supply circuit 23 includes a NAND gate G4 that takes the logic of the write verify signal VERIFY and the address ai, and an inverter gate 11 that inverts its output.

E type for switching to supply the verify potential VVER to the control line.

n-channel MOS) transistor Q24, and this MO
S) A protective D-type, n-channel MOS transistor QD provided between the transistor QE4 and the control gate line.
11.

FIG. 7 shows a configuration example of a circuit for generating the verify potential vv□ applied to the write verify potential supply circuit 23.

The write verify potential V VER is equal to the power supply potential VCC when the write verify signal VERIFY is input! Outputting the intermediate potential set between the ground potential and the sixth
It is supplied to the control gate line selected by the verify potential supply circuit 23 in the figure, and in this embodiment, Vc
It is mainly composed of E-type, n-channel MOS transistors Qp, 6, and QE7 connected in series between C and ground potential. A voltage dividing circuit including resistors R1 to R5 is provided to apply a predetermined bias to the gates of these MOS transistors. In principle, it is sufficient to apply the power supply potential VCC to terminal A of these voltage divider circuits, but in this case a through current will flow. In order to prevent this, in this embodiment, an E-type n-channel MOS transistor QE
s, QE9, an E type, p channel MOS) transistor QP610P7, and a switching circuit including an inverter I3.

That is, when the verify signal VERIFY goes to the "H" level, the MOS transistor QE8 is turned on, the transistor QP7 is turned on, and Q11!9 is turned off, and the power supply potential Vcc is supplied to the terminal A of the voltage dividing circuit. As a result, the MOS transistor Q E61QE7 is set by the voltage dividing ratio of the voltage dividing circuit.
A write verify potential vvTlR of an intermediate potential corresponding to the conduction state of is obtained. Verify signal VERIF
When Y is at L2 level, MOS) transistor QE9 is turned on, terminal A of the voltage divider circuit becomes the ground potential, and the verify potential vvER terminal becomes floating.At this time, in the switching circuit, MOS) transistor Qpt is turned on. Since it is off, no current flows.

Figure 8 shows the two selection gates SGI and S of the NAND cell.
This is the control circuit for G2. NAND gate selects the selection gate according to the output of the row decoder
, 2 and inverters 111 and 11° provided at their output terminals.

2 inputs N when write signal WRI TE is “H level”
NA by OR gate G13 and inverter 113
The "H" level is applied to the ND gate G11, and at this time, the selection gate SGI on the drain side is selected, and the selection gate SG2 on the source side is not selected.

The other input terminal of the NOR gate G13 receives the erase signal E.
RASE, read signal READ, write verify signal W-VERIFY and erase verify signal E-VE
NOR gate G, 4 into which RIFY enters and inverter 114
is provided. That is, erase signal ERASE, read signal READ, write verify signal W-VERIFY,
Either erase verify signal E-VERIFY is “H”
When the voltage reaches the "H" level, the NOR gate G13 enters the "H" level, and the two selection gates SGI and SG2 are selected at the same time.

However, the erase verify signal E-VERI PY is supplied to the NOR gate G14 via the timer circuit 25.

In this embodiment, the timer circuit 25 is a two-input NOR circuit in which the erase verify signal E-VERIFY is directly connected to one input.
Gate G13. Inverter 1 installed at its output terminal
15. Delay circuit D for supplying erase verify signal E-VERIP"Y to NOR gate G14 for a certain period of time
L and an inverter II6. That is, erase verify signal E-VERI FY times signal “H”
When the level is reached, the "H" level enters the NOR gate G14, and the selection gates SG, SG2 are simultaneously selected.Then, after a time determined by the delay circuit DL, both inputs of the NAND gate G14 become "H" level. NO
The "H" level supplied to R gate G14 returns to level.

The delay circuit DL may be composed of, for example, a resistor and a capacitor, or may be a circuit that counters the output of a ring oscillator and outputs an output when a certain count is reached.

FIG. 9 shows an example of the configuration of the verify completion detection circuit 9.
As shown in the figure, it is composed of a flip-flop, a NAND gate, and an inverter.

Next, the operation of the EEFROM configured as described above will be explained.

First, prior to writing data, data is erased from all memory cells. When erasing data, OV is applied to all control lines (word lines) CG. That is, in the control circuit shown in FIG. 6, the erase signal E is sent to the erase/read control circuit 24.
RASE enters, which causes MOS) transistor QE3
is turned on and all control gate lines CGi are set to OV. At this time, the selection gate lines SG, SG2 are also set to OV.

Then, with the bit line and source line in a floating state, a high voltage vpp is applied to the p-type substrate (or p-type well and n-type substrate) on which the memory cell array is formed. By maintaining this bias state for, for example, 10111 seconds, electrons are emitted from the floating gates of all memory cells, and the threshold becomes a negative "0° state."

An erase verify operation for checking whether the threshold value of an erased memory cell has become sufficiently negative is performed as follows. In the control circuit of FIG. 6, the erase verify signal E-ERASE is input to the erase/read control circuit 24, the switching MO3) transistor QE3 is turned on, and all memories in the selected NAND cell are erased regardless of the address. The control gate of the cell is set to OV. At the same time, the selection gates S Gr and S G2 are selected by inputting the erase verify signal E-ERASE to the control circuit shown in FIG. 8, and are set to, for example, 5V. For example, 1. - 5V is applied and the source line is set to OV. At this time, the time during which the selected data (SG, sG2) is 5V is set to the time when data "0" can be read if the threshold of the erased memory cell becomes negative to some extent. It is set by the timer circuit 25 having the delay circuit DL shown in Fig. 8.For example, when all the control gates are OV and the bit line is 1.5V, the memory cell is 10μ
If the readout time when A is allowed to flow is to be lower than the threshold value of 200nsee, this readout time is set to 150nsee. If data "0" is not read out within this set time, the data is erased again and the same verify operation is repeated until the condition is met.

In data writing, data for one word is latched in the data latch circuit 5, and the bit line potential is controlled by the data to write "O" or "1". At this time, the selected control gate line is given a high potential Vpp, and the unselected control gate line on the bit line side is given an intermediate potential Vpp.
M is applied. In the control circuit of Fig. 6, the write signal WR
ITE is input.

That is, depending on the logic of the write signal WRITE and addresses ai and aj, the high potential supply circuit 21 or the intermediate potential supply circuit 22 is turned on, and the selected control gate line is supplied with vpp.
, v pI)M is applied to unselected control gate lines.

The bit line BL is set to OVl when writing data “1”.
For "O" writing, an intermediate potential is applied. The time for maintaining the bias condition for data writing is sufficiently short compared to the conventional writing method, for example, about 1/100 of the conventional writing method, specifically about 10 μsec. In a memory cell in which "1" is written, the threshold value shifts in the positive direction, and in a memory cell in which "0" is written, the threshold value remains negative.

Next, a write verify operation begins. In this embodiment, it is checked whether the threshold value of the memory cell to which data "1" has been written has reached a desired value. This desired threshold value is determined in consideration of the data retention characteristics of the memory cell, and is, for example, about 2.5V. Such a verify operation is performed for the memory cell of one word line to which writing has been performed. FIG. 10 is a timing diagram of the write verify operation. First, sense signal 5E
NSE becomes "H" level and the sense amplifier circuit 2 is enabled. Column address aj is inputted by this time column address generation circuit 7, data is outputted to the data output line, and data from the data latch circuit 5 is outputted to the latch output line. In this write verify operation cycle, the verify signal W-VERIFY is sent to the control circuit of FIG.
and read signal READ are input at the same time. Based on the logic between these and the address aj aj, the selected control gate line is set to VCC by the verify control circuit 23.
The write verify potential V is set between the ground potential and the ground potential.
VER-2.5V is supplied. Other control gate lines are connected to the NAND gate of the erase/read control circuit 24.
The output of G3 becomes “L” level and Ve is applied to the control gate line.
e is supplied. At this time, the selection gate lines SG are simultaneously selected by the control circuit of FIG.

Both S02 are set to Vec, and the bit line BL is set to 1.
5V is applied, and the source line is set to OV.

As a result, if the selected memory cell has been written with "1" and its threshold value exceeds 2.5V, the selected memory cell becomes non-conductive and data "1" is written. Read out.

If "1" has been written but the threshold voltage has not reached 2.5V, the selected memory cell becomes conductive and is read as data "○".

Then, the write data and the data read by the verify operation are compared by the data comparison circuit 3, and the comparison result is latched when the latch signal LATCHV changes from the "L" level to the "H" level. That is, if the read data is 1°, it is inverted by the inverter 31 in the comparator circuit 3 and enters the NAND gate 32 together with the write data "l" from the data latch circuit 4, and the write data is inverted by the inverter 33. If it is “1”, it becomes “0” and is latched in the latch circuit 34.The write data is “1°”, but the writing is insufficient and “0”.
If “1°” is read out, the latch circuit 34 has “1°”.
latched as . When the write data is 10', it is latched into the latch circuit 34 in the comparison circuit 3 as "O" regardless of the read data. The state of the latched data in the data comparison circuit 3 is summarized in Table 1.

Table 1 When "1" appears at the output of the data comparison circuit 3, the verify end detection circuit 9 does not issue a verify end signal. That is, in FIG. 9, after the flip-flop is initialized by the write verify signal W-VERIFY, when 41''' appears at the output of the data comparison circuit 3, the output of the flip-flop is set to "O". The data comparison signal remains “O” until the comparison is completed.
m Therefore, the verify end signal is output as "0", indicating that the verify is not completed. When the data comparison of all bit lines is completed, the data comparison end signal becomes “1”.
However, if verification is not completed, a signal will be emitted. 1)7
When V is at the "H" level, the data in the data comparison circuit 3 is again passed through the data buffer 8 and latched into the data latch circuit 5 as new data via the data input line. As is clear from the table above, the "1" data is latched again only for the address where writing was insufficient, and the "1" data write operation is repeated again. Then, the verify operation is performed again, and the "1" data is latched again. ``When there are no memory cells that are insufficiently written, the data comparison circuit 3 outputs 1.
"1" no longer appears, and the flip-flop becomes "0"
remains set, and the data comparison end signal is “
When the voltage reaches 1, the verify completion detection circuit 9 outputs a completion signal "1", and the data write operation ends.

Table 2 summarizes the potential relationship of each part in each of the above operation modes. Here, a case is shown in which control gate line CG2 is selected during write and write verify.

Table-2 The data read operation is the same as the conventional one.

As described above, according to this embodiment, the threshold voltage of a memory cell in an erased state can be set to be lower than a certain value by executing data erase verify control. This makes it possible to prevent the speed when reading "0" from slowing down, and also prevent the threshold value after writing "1°" from becoming too large.

Further, in this embodiment, when data is written, the operation of shortening the time for one write and writing again to memory cells for which the write is insufficient is repeated. This prevents excessive writing due to variations in the manufacturing process when reliably writing "1" data in a single write operation as in the past, that is, the threshold value of 12 data becomes unnecessarily high. Therefore, variations in the threshold values of all memory cells to which "1" data is written can be reduced. As a result, unselected memory cells function as transfer gates, and the reliability of the NAND cell type EEFROM is increased.

In the embodiment, the threshold evaluation standard in the write verify operation is set to 2.5V, but this can be set to any other appropriate value in relation to the permissible threshold distribution. The same goes for the time for one write; for example, in order to make the final threshold distribution smaller, it is possible to shorten the time for one write and repeat the write/verify operation in small increments. good. Similarly, the check time during the erase verify operation can be set to an appropriate value as necessary. Further, in the embodiment, a NAND cell type EEPROM using tunnel injection has been described, but the present invention is effective as long as it is a NAND cell type EEPROM that uses a communication method such as hot electron injection.

In addition, the present invention can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, by performing erase verify control or write verify control together with the erase verify control, the threshold value of the memory cell is set to the optimum state and reliability is improved. A cell-type EEFROM can be provided.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an EEPROM according to an embodiment of the present invention, FIGS. 2(a) and 2(b) are a plan view and an equivalent circuit diagram of one NAND cell in the memory cell array, and FIG. 3(a) (
b) are A-A' and B-B' in FIG. 2(a), respectively.
4 is an equivalent circuit diagram of a memory cell array, FIGS. 5 and 6 are diagrams specifically showing the main part configuration of FIG. 1, FIG. 7 is a diagram showing a write verify potential generation circuit, and FIG. FIG. 8 is a diagram showing a selection gate control circuit, FIG. 9 is a diagram showing a configuration example of a verify completion detection circuit, and FIG. 10 is a timing diagram for explaining a write verify operation. DESCRIPTION OF SYMBOLS 1...Sense amplifier circuit, 2...Memory cell array, 3...Data comparison circuit, 4...Human output buffer,
5... Data latch circuit, 6... Control gate control circuit, 7... Column address generation circuit, 8... Verification end detection circuit, 21... High potential supply circuit, 22...
Intermediate potential supply circuit, 23... Write verify potential supply circuit, 24... Erase/continuation control circuit, 25...
timer.

Claims (4)

[Claims] (1) A charge storage layer and a control gate are stacked on a semiconductor substrate, and a plurality of memory cells that can be electrically rewritten by transfer of charge between the charge storage layer and the substrate are connected in series to form a NAND cell. In a non-volatile semiconductor memory device having a memory cell array configured and arranged in a matrix, a predetermined erase verify potential is applied to the control gates of all memory cells in a selected NAND cell, and a data erase state is established by a bit line current. A nonvolatile semiconductor memory device comprising an erase verify control circuit for verifying. (2) A charge storage layer and a control gate are stacked on a semiconductor substrate, and multiple memory cells that can be electrically rewritten by transfer of charge between the charge storage layer and the substrate are connected in series to form a NAND cell. In a non-volatile semiconductor memory device having a memory cell array configured and arranged in a matrix, a predetermined erase verify potential is applied to the control gates of all memory cells in a selected NAND cell, and a data erase state is established by a bit line current. An erase verify control circuit for verifying, and a write verify control circuit for verifying a data write state by applying a predetermined write verify potential to the control gate of a selected memory cell in a selected NAND cell. Non-volatile semiconductor memory device. (3) The nonvolatile semiconductor memory device according to claim 1 or 2, wherein the erase verify control circuit includes a built-in timer for setting a predetermined operating time and performing reading. (4) A charge storage layer and a control gate are stacked on a semiconductor substrate, and a plurality of memory cells that can be electrically rewritten by transfer of charge between the charge storage layer and the substrate are connected in series to form a NAND cell. a memory cell array configured and arranged in a matrix; a data input buffer and data latch circuit that provides write data to bit lines of the memory cell array; a sense amplifier circuit and a data output buffer that read bit line data of the memory cell array; a write verify control circuit that reads data by sequentially applying a write verify potential to confirm the write state to selected control gate lines after writing data to the memory cell array; the data latch circuit and the sense amplifier; A data comparison circuit that has a function of comparing the outputs of the circuit and temporarily latching the result, and a means for confirming the write state based on the output of this data comparison circuit and performing back-writing to memory cells that are insufficiently written. , Apply a ground potential to the control gates of all memory cells in the selected NAND cell and change its NA by bit line current.
A nonvolatile semiconductor memory device comprising: an erase verify control circuit for confirming the erased state of a memory cell in an ND cell.