JPH03266578A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To form a high vision picture of wide band on a liquid crystal display device with a high quality regardless of the use of source drivers of low speed of a sampling a holding circuit by dividing a real-time video signal to plural channels to input it to source drivers. CONSTITUTION:An analog video signal is subjected to A/D conversion, and the digitized video signal of one channel is divided to plural channels in real time. Video signals divided to plural channels are sampled and held by D/A converting means 41 to 4n and 4'1 to 4'n provided for respective channels while the timing of sampling and holding is successively delayed by the A/D conversion sampling period. Thereafter, video signals are multiplexed with respect to time and are inputted to source drivers 101 to 10m and 111 to 11m. Thus, the time which source drivers require to accurately sample and hold the input video signals is secured, and a picture including wide band signal components like a high vision picture can be formed on the display device though source drivers of low speed of the sampling and holding circuit are used.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is used to synthesize and reproduce images on a display using a TPT-LCD source driver with a slow sampling speed from a wideband video signal. The present invention relates to a suitable video signal processing circuit.

[Prior art] The current television system, NTSC, has a scanning line count of 5.
25 lines/frame, interlace ratio 2=1, and aspect ratio 423.

On the other hand, so-called Hi-Vision, which is a type of high-definition television system, has 1125 scanning lines/frame.
Interlace ratio is 2:1. The aspect ratio is 16:9, and the amount of information is about five times or more than that of the NTSC system.

Regarding high-definition television that handles wideband video signals, there is application technology for cathode ray tube displays, but application technology for liquid crystal displays is still under development, and the applicant of this patent application has previously filed Japanese Patent Application No. 1-258822. There are 4 other cases.

These are all measures to deal with the digital processing section of the source driver, that is, the slow sample and hold circuit section, and are measures because the component specifications cannot satisfy the system requirements. It goes without saying that in order to faithfully reproduce images, it is essential that the video signal input section sampler performs ultra-high-speed processing.

[Problems to be Solved by the Invention] In order to display such a high-definition video signal on a TPT-LCD, a source driver that can be driven at high speed is required. In particular, with the significant increase in the number of pixels, the speed of the sample and hold circuits in current sources and drivers cannot support wideband high-definition video signals, so analog video signals cannot be processed using the conventional NTSC system. Even if the source driver (AC signal for LCD application) is applied as is to the source driver, it will not work, or even if it works, only an image with extremely low horizontal resolution will be obtained.

However, since the speed of current sample-and-hold circuits is at its limit, the video signal of one channel is divided to form the video signal of multiple channels, and the video signals of the multiple channels in step 2 are sequentially and repeatedly sampled to generate the pixel signal. It is possible to form a According to this, pixel signals can be formed satisfactorily while keeping the speed of the sample and hold circuit in each channel low.

Therefore, the present invention provides a circuit that can faithfully form an image on a TPT-LCD from a broadband high-definition video signal even when using a source driver with a slow sample-and-hold processing speed.

Means for Solving the Problems] The present invention provides a means for A/Df converting an analog video signal, a means for dividing a digitized one-channel video signal into multiple channels in real time, and a means for dividing a digitized one-channel video signal into multiple channels, and a means provided for each divided channel. The apparatus also includes D/A conversion means and means for sequentially outputting analog video signals of a plurality of channels.

[Effect]

Each video signal divided into a plurality of channels is sampled and held by a D/A conversion means provided for each channel with a delay in A/Di conversion sampling cycle timing.

Thereafter, each video signal is temporally multiplexed and input to the source driver. As a result, the source driver can secure the time necessary to accurately sample and hold the input video signal, and even if a source driver with a slow sample-and-hold circuit is used, it can still capture wideband signal components such as high-definition video signals. Images can be formed on the display.

[Example] (a-1) 1 First, as a specific example of the LCD panel module according to the present invention, an outline of one using a three-person video driver compatible source driver will be explained with reference to FIG.

The reason why it was made to be 3-man-powered is that R and G are 3-man-powered.

The advantage is that it can be used as a source driver for a single-panel LCD that is used as a BFT print source.

In this example, a liquid crystal display for displaying high-definition images (
One horizontal scanning period of the video signal supplied to R, G, and B (total of 3 images) is 6 times for each of red signal R1, green signal G, and blue signal B.
Divide the channels (upper, hinge 8 channel Iv) and repeat them in a time difference series to produce red signals R1-3: R1-3, green signals Gl-3: G; ~3, and blue signals B 1-3p. 1
3'l/%+3 is obtained.

(a-2) Next, a general example of the specific example of (a-1) will be briefly explained using FIG. 3.

Source drivers 10 □ to □ and 111 to m are connected to each other by 1p on the upper and lower sides of the TFT-LCD panel 13, respectively.
Connected every ixel, gate driver 1 on left and right
2. ~k are connected.

The source drivers 10 and 11 used in the present invention have a plurality of analog video signal input terminals, and each source driver has a plurality of analog video signal input terminals.
It corresponds to driver output terminals 112131..., n.

Thereafter, the output terminals 1 to n are repeatedly connected to the panel. In addition, the input analog video signal is sampled and held by the sampling clocks CLU and CLL corresponding to the upper and lower source driver groups, and the upper and lower source drivers 101 to 101 to n, 1 are input during the next horizontal scanning period.
They are output from 1□ to n all at once through the source path line.

cb-t) From now on, as an example of the present invention, the above (a
A description will be given of what corresponds to the specific example of -1).

First, the system of the red signal R will be explained.

In FIG. 1, the red signal supplied to the input terminal IR is converted into a digital signal by the A/D converter 1, and the γ-RO
M2 is input to latch 3.

The digitized video signal is divided into two D/A converter groups 4□-3; 41-3 for upper and lower sides, and the sampled video signal is converted by sampling clock 7CL1-3; CLl-3. becomes.

At the same time, by applying an inversion clock INVH having a period of a horizontal scanning period, a positive/inverted video signal is formed and a sampled AC signal is obtained.

These signals are converted into analog AC video signals by LPF groups 51-3;
3, video signals R1 to 3 suitable for liquid crystal display: R1 to
Output. These series of operations will be explained using FIG. 2. CLI ~ 5 - CL1 ~ 3 are each A/D of each other
With a clock shifted by the conversion sampling period TI [T2
+T3 (switching timing)].

One D/A converter converts D/A at a period (T2) that is T104 times.
The A conversion operation is performed, and the signals ■~■, ■~@ν[phase]~required, . . . are obtained. In this way, the 6-channel sampled analog signal, which is temporally expanded by 4 times and whose timing is shifted by T1, is output as a multi-channel analog AC video signal through an LPF and an amplifier. input to the driver.

As mentioned above, the source driver has three signal inputs, and the video signals R, ~3; R1~3 are input to the upper source driver and lower source driver, and the sampling clock CLU for the upper side and the lower Since the side CLL performs analog sampling and holding, six channels of video signals are sequentially applied to pixels arranged in the horizontal direction as shown in FIG.

At this time, four times the A/D conversion period Tl is allocated as the sample hold time of the source driver.

CLu and CLt are set to be shifted from each other by T at twice the period of the basic clock CLK. In other words, A/D9 conversion is performed using ultra-high-speed sampling, and the input signal of the source driver is divided into multiple channels of real-time video signals. As a result, an image faithful to the original signal can be formed on the display even if a source driver with a slow sample-and-hold circuit is used.

Although the red signal R has been described in detail above, the green signal G and blue signal B operate in the same manner.

(b-2) Next, an embodiment corresponding to (a-2) in which multi-channel division is extended to a general example will be described using FIG.

This example is a liquid crystal display (R) for displaying high-definition images.
. Signal R1-n; R'l-n, green signal Gl-n; G-~n, blue signal B1~n p B 1=
This is to obtain n.

First, the red signal RO system will be explained.

In FIG. 1, the red signal supplied to the input terminal IR is converted into a digital signal by the A/D converter 1, and the γ-RO
M2 is input to latch 3. The digitized video signal is transferred to two D/A converter groups 4□ to n for the upper and lower sides.
e Divided and connected to 41-H, with predetermined clock CL
1-n; CL'1 to CL'n become sampled video signals. At the same time, the horizontal scanning period cycle clock INVH
By applying , positive and inverted video signals are formed and a sampled AC signal is obtained. These signals are LPF group 5
+-n; 5'1 to n becomes an analog AC video signal and becomes an amplification word group 6! -n; 6'l-n, video signals R1-n; R't-n suitable for liquid crystal are output. (b-1
), (n+1) times T1 is assigned as the sample hold time of the source driver.

That is, the slow source of the sample and hold circuit
This drive method is compatible with the driver.

[Effects of the Invention] As explained above, according to the present invention, a real-time video signal is divided into multiple channels and inputted to the source driver, so even if a source driver with a slow sample-and-hold circuit is used, broadband high-definition can be achieved. Images can be formed on a liquid crystal display with high quality.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the video signal processing circuit of the present invention, FIG. 2 is a timing chart when dividing into 6 channels, which is a specific embodiment of the present invention, and FIG. 8 is an LCD of the present invention. FIG. 4 is a block diagram of a specific embodiment of the LCD panel module of the present invention. In the drawing, 1uA/D converter, 2trlr-ROM,
3 is a buffer, 41=ny 41-n is a D/A converter, 51-H, ' 51-n beam, P, F group, 61-
n161~. indicates a widening word group.

Claims (1)

[Claims] 1. means for digitally converting one analog video signal; means for dividing the digital output into multiple channels in real time; means for converting into a sampled analog signal provided for each divided channel; and the plurality of channels. A video signal processing circuit comprising: means for sequentially sampling and holding (analog memory) analog video signals within a horizontal scanning period and simultaneously outputting them after a predetermined period of time has elapsed.