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JPH03266494A - Manufacture of printed wiring board - Google Patents

Manufacture of printed wiring board

Info

Publication number
JPH03266494A
JPH03266494A JP6787690A JP6787690A JPH03266494A JP H03266494 A JPH03266494 A JP H03266494A JP 6787690 A JP6787690 A JP 6787690A JP 6787690 A JP6787690 A JP 6787690A JP H03266494 A JPH03266494 A JP H03266494A
Authority
JP
Japan
Prior art keywords
board
circuit pattern
printed wiring
resist film
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6787690A
Other languages
Japanese (ja)
Inventor
Megumi Aoyanagi
青柳 恵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP6787690A priority Critical patent/JPH03266494A/en
Publication of JPH03266494A publication Critical patent/JPH03266494A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To enable a required fine pattern to be easily formed by a method wherein a solder resist film pattern is deposited on a laminated board which is formed by laminating base materials into one piece, and a chemical plating layer is deposited on a prescribed circuit pattern region. CONSTITUTION:A copper foil is plated on the primary surface of, for instance, a prepreg layer where resin deposited by dipping is semi-cured or partially uncured to form a base board 7, a required through-hole 4 is bored in the board 7, and a photoetching treatment is carried out to form a required circuit pattern 1 on the board 7. The base board 7 is cured into one piece by thermocompression forming to enable the circuit pattern 1 to be buried in the surface of the base board 7, consequently a laminated board 3' whose surface is flattened can be obtained, and a required solder resist film pattern 2 is selectively formed on the surface of the laminated board 3'. The laminated board 3' is subjected to a chemical copper plating treatment, whereby a chemical plating layer 5 is deposited on circuit pattern regions 1a and 4a not covered with the solder resist film 2 to form a required printed wiring board 3. By this setup, a fine patterning can be carried out.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明はプリント配線板の製造方法に係り、特に実装回
路ユニットの構成に適するプリント配線板の製造方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a printed wiring board, and particularly to a method for manufacturing a printed wiring board suitable for the configuration of a mounted circuit unit.

(従来の技術) 電子機器類の小形化や回路機能の向上に対応して、いわ
ゆる混成機能回路ユニットが開発され、広く実用に供さ
れている。すなわち、電子機器類においては、構成の簡
略化やコンパクト化などを目的にし、配線部にプリント
配線板を用い、このプリント配線板面にメモリーIC素
子および抵抗体などを搭載・実装して成る混成機能回路
ユニットが知られている。
(Prior Art) In response to the miniaturization of electronic devices and the improvement of circuit functions, so-called hybrid function circuit units have been developed and are now widely put into practical use. In other words, in electronic equipment, for the purpose of simplifying and compacting the configuration, a printed wiring board is used for the wiring part, and a memory IC element, a resistor, etc. are mounted and mounted on the printed wiring board surface. Functional circuit units are known.

しかして、上記混成機能回路ユニットの構成には、第3
図に要部を断面的に示すような構造のプリント配線板が
使用されている。すなわち、図示されていない内層回路
パターン層を有する一方、外表面に所要の回路パターン
1が設けられ、さらに所要の接続用バッド1aやスルホ
ールランド4aなどの領域以外の面をソルダーレジスト
膜2て被覆した構造のプリント配線板が用いられている
However, in the configuration of the above-mentioned hybrid functional circuit unit, there is a third
A printed wiring board is used, the main part of which is shown in cross section in the figure. That is, while it has an inner circuit pattern layer (not shown), a required circuit pattern 1 is provided on the outer surface, and the surface other than the required connection pads 1a and through hole lands 4a is covered with a solder resist film 2. A printed wiring board with a similar structure is used.

また、前86プリント配線板は、一般に次のようにして
製造されている。すなわち、所定の回路パターンを設け
た内層基板(基材)間にプリプレグ層を介在させ、外層
としてプリプレグ層を介して銅箔張り基材を積層し、加
圧加熱して硬化一体化した後、外層の銅箔について選択
的ホオトエッチング処理を施して、所要の外層回路パタ
ーン1を形成している。したがって、外層回路パターン
1は、銅箔の厚さ分プリント配線板3面に突出した形を
なすか、ソルダーレジスト膜2の被着形成によってほぼ
平坦化した状態をなしている。
Further, the front 86 printed wiring board is generally manufactured as follows. That is, a prepreg layer is interposed between inner layer substrates (base materials) provided with a predetermined circuit pattern, and a copper foil-clad base material is laminated as an outer layer via the prepreg layer, and after being cured and integrated by heating and pressurizing, A desired outer layer circuit pattern 1 is formed by selectively photo-etching the outer layer copper foil. Therefore, the outer layer circuit pattern 1 protrudes from the surface of the printed wiring board 3 by the thickness of the copper foil, or is substantially flattened by the solder resist film 2 being deposited thereon.

(発明が解決しようとする課題) しかし、上記構成のプリント配線板3は、表面実装用、
換言すると混成機能回路ユニット用とした場合、次のよ
うな不都合がある。すなわち、電子部品の表面実装密度
の向上や混成機能回路ユニットのコンパクト化に当って
は、プリント配線板3の外層回路パターン1幅の狭小化
および外層回路パターン1間隔の狭小化か必然的に要求
されることになる。このため、隣接して表面に露出して
いる外層回路パターン1同士か短絡し易いばかりでなく
、所定の位置に所要の電子部品たとえばメモリーIC素
子などのリード6を、位置ずれなく搭載・実装するにも
細心の注意や高度の技術など要し、混成機能回路ユニッ
トの構成が煩雑になるなどの問題がある。
(Problem to be Solved by the Invention) However, the printed wiring board 3 with the above configuration is for surface mounting,
In other words, when used for a hybrid function circuit unit, there are the following disadvantages. In other words, in order to improve the surface mounting density of electronic components and to make hybrid functional circuit units more compact, it is necessary to reduce the width of the outer layer circuit pattern 1 of the printed wiring board 3 and the interval between the outer layer circuit patterns 1. will be done. For this reason, not only are adjacent outer layer circuit patterns 1 exposed on the surface easily short-circuited, but also it is difficult to mount and mount the leads 6 of required electronic components such as memory IC elements at predetermined positions without misalignment. However, there are problems such as requiring careful attention and advanced technology, and making the configuration of the hybrid functional circuit unit complicated.

本発明は上記事情に対処してなされたもので、所望の微
細パターンの形成も容易でかつ、表面実装する電子部品
の位置決めなどにも繁雑さを要しないプリント配線板が
得られる製造方法の提供を目的とする。
The present invention has been made in response to the above circumstances, and provides a manufacturing method for obtaining a printed wiring board that allows easy formation of a desired fine pattern and does not require complicated positioning of electronic components to be surface mounted. With the goal.

[発明の構成] (課題を解決するための手段) 本発明は、主面に所要の回路パターンが設けられかつ、
含浸被着した樹脂が半硬化状ないし一部未硬化状の基材
を少くとも回路パターンが外表面に位置するように積層
し加圧加熱して硬化一体化する工程と、 前記一体化して得た積層板面に選択的に所要のソルダー
レジスト膜パターンを被着形成する工程と、 前記ソルダーレジスト膜で覆われていない所定の回路パ
ターン領域に化学めっき層を被着形成する工程とを具備
してなることを特徴とする。
[Structure of the Invention] (Means for Solving the Problems) The present invention has a main surface provided with a required circuit pattern, and
A step of laminating base materials in which the impregnated resin is semi-cured or partially uncured so that at least the circuit pattern is located on the outer surface, and curing and integrating them by pressurizing and heating; a step of selectively depositing a desired solder resist film pattern on the surface of the laminated board; and a step of depositing a chemical plating layer on a predetermined circuit pattern area not covered with the solder resist film. It is characterized by being

(作 用) 本発明によれば、主面に所要の回路パターンが設けられ
かつ、含浸被着した樹脂が半硬化状ないし一部未硬化状
の基材を少くとも回路パターンが外表面に位置するよう
に積層し加圧加熱して硬化一体化されるため、外層回路
パターンは基材に互いに隔絶して埋込まれて面が平坦化
する。また積層板面に、たとえば接続用パッド面を露出
させて選択的にソルダーレジスト膜パターンを被着形成
して、前記露出面に化学めっき層を選択的に被着形成す
るため、半田付は性なども補強される。
(Function) According to the present invention, at least the circuit pattern is located on the outer surface of a base material in which a required circuit pattern is provided on the main surface and the impregnated resin is semi-cured or partially uncured. Since the outer layer circuit patterns are laminated and cured and integrated by heating and pressing, the outer layer circuit patterns are embedded in the base material while being separated from each other, and the surface is flattened. In addition, a solder resist film pattern is selectively deposited on the laminate surface, for example by exposing the connection pad surface, and a chemical plating layer is selectively deposited on the exposed surface, so soldering is easy. etc. will also be reinforced.

一方、前記ソルダーレジスト膜の厚さに対して形成され
る化学めっき層の厚さが薄いので、ソルダレジスト膜が
ダム的な役割をなし、短絡防止や位置決めなどにも寄与
する。
On the other hand, since the chemical plating layer formed is thinner than the thickness of the solder resist film, the solder resist film acts as a dam and also contributes to short circuit prevention and positioning.

(実施例) 以下第1図および第2図を参照して本発明の詳細な説明
する。
(Example) The present invention will be described in detail below with reference to FIGS. 1 and 2.

第1図(a)〜(d)は本発明に係るプリント配線板の
製造工程における態様を模式的に示す断面図であり、ま
た第2図は本発明に係るプリント配線板の製造方法で得
たプリント配線板に搭載・実装した電子部品のリードの
半田付けされた態様を模式的に示す断面図である。
FIGS. 1(a) to (d) are cross-sectional views schematically showing aspects of the manufacturing process of a printed wiring board according to the present invention, and FIG. FIG. 2 is a cross-sectional view schematically showing how the leads of an electronic component mounted and mounted on a printed wiring board are soldered.

先ず、含浸被着した樹脂が半硬化状ないし一部未硬化状
のたとえばプリプレグ層の主面に銅箔を張合せた素板7
を用意する。次いで前記素板7に所要のスルホール4を
穿設した後、銅箔についていわゆるホオトエッチング処
理を施して所要の回路パターン1を形成する(第1図(
a))。
First, a blank plate 7 is prepared by laminating copper foil on the main surface of a prepreg layer in which the impregnated resin is semi-cured or partially uncured.
Prepare. Next, after drilling the required through holes 4 in the blank plate 7, the copper foil is subjected to a so-called photo-etching process to form a required circuit pattern 1 (see FIG. 1).
a)).

しかる後、前記により所要の回路パターン1を形設した
含浸被着する樹脂が半硬化状ないし一部未硬化状の素板
(基材)を加熱・加圧成形により硬化一体化して前記回
路パターン1が素板(基材)7面に埋込まれて表面が平
坦化した積層板3′を得る(第1図(b))。かくして
得た積層板3′の面にたとえば光硬化性のソルダーレジ
スト膜2を被着形成し、これに露光、現像処理を施して
選択的に所要のソルダーレジスト膜パターン2を形成す
る。つまり、前記形設された回路パターン1中、接続用
パッドlaおよびスルホールランド4aなどを成す部分
を露出させ、他の領域面を選択的に所要のソルダーレジ
スト膜2でマスキングする(第1図(C))。
Thereafter, the base plate (base material) in which the required circuit pattern 1 has been formed and the impregnated resin is semi-cured or partially uncured is cured and integrated by heating and pressure molding to form the circuit pattern. A laminated plate 3' having a flattened surface is obtained by embedding No. 1 into the 7 sides of the blank (base material) (FIG. 1(b)). For example, a photocurable solder resist film 2 is deposited on the surface of the thus obtained laminate 3', and is exposed and developed to selectively form a desired solder resist film pattern 2. That is, in the formed circuit pattern 1, the portions forming the connection pads la and through-hole lands 4a are exposed, and other areas are selectively masked with a required solder resist film 2 (see FIG. 1). C)).

次に、上記により所要のマスキングを行った積層板3′
について、所要のめっき前処理を施してから、化学銅め
っき処理を施し、前記ソルダーレジスト膜2で覆われて
いない回路パターン領域1aおよび4aに化学めっき層
5を被着形成することによって所望のプリント配線板3
が得られる(第1図(d))。
Next, the laminated plate 3' which has been masked as described above
After performing the required plating pre-treatment, a chemical copper plating process is performed to form a chemical plating layer 5 on the circuit pattern areas 1a and 4a not covered with the solder resist film 2, thereby forming the desired print. Wiring board 3
is obtained (Fig. 1(d)).

上記により得られたプリント配線板3は、互いに電気的
に隔絶(基材に埋込まれ)した外表面のパターン1の一
部がソルダーレジスト膜2で覆われ、一方このソルダー
レジスト膜2が露出している接続用パッドlaやスルホ
ールランド4aなどに対して隔壁ないし堰として作用し
、第2図に示すように、たとえばメモリーIC素子のり
−ド6を接続用パッド1aに半田付けして接続した場合
も、半田の流出により隣接する接続用パッド13間の短
絡など起る恐れも全面的に回避される。
In the printed wiring board 3 obtained as described above, a part of the patterns 1 on the outer surface that are electrically isolated from each other (embedded in the base material) are covered with a solder resist film 2, while this solder resist film 2 is exposed. As shown in FIG. 2, for example, a memory IC element glue 6 is connected to the connecting pad 1a by soldering. In this case, the risk of short circuits between adjacent connection pads 13 due to solder leakage is completely avoided.

なお、上記では両面型のプリント配線板の製造方法例を
示したが、片面型のプリント配線板および多層型のプリ
ント配線板の製造にも勿論適用し得る。
In addition, although the example of the manufacturing method of a double-sided printed wiring board was shown above, it can of course be applied to the manufacturing of a single-sided printed wiring board and a multilayer printed wiring board.

[発明の効果コ 上記説明したように、本発明に係るプリント配線板の製
造方法によれば、実装密度が高く、また電子部品の搭載
・実装における位置決めも容易になし得るため、混成機
能回路ユニットの構成に適するプリント配線板を容易に
得ることができる。
[Effects of the Invention] As explained above, according to the method for manufacturing a printed wiring board according to the present invention, the mounting density is high and the positioning during mounting and mounting of electronic components can be easily performed. A printed wiring board suitable for this configuration can be easily obtained.

すなわち、外層回路パターンなどを、比較的薄い銅箔を
出発材料として形成し得るので微細なパターンニングが
可能となる。しかも、外層回路パターンなどは支持基材
に埋込まれ、互いに隣接する回路パターンは電気的にも
隔絶されているためピッチを狭くしても短絡を起す恐れ
もない。また、半田付は性などを補強するための選択的
化学めっきに用いたソルダーレジスト膜が、位置決めや
半田流れの防止などに寄与するので、所要電子部品の搭
載・実装作業も容易になる。
That is, since the outer layer circuit pattern and the like can be formed using relatively thin copper foil as a starting material, fine patterning becomes possible. Moreover, since the outer layer circuit patterns and the like are embedded in the support base material, and adjacent circuit patterns are electrically isolated from each other, there is no risk of short circuiting even if the pitch is narrowed. In addition, the solder resist film used in selective chemical plating to reinforce soldering properties helps with positioning and prevents solder flow, making it easier to mount and mount required electronic components.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a) 、 (b) 、(c)および(d)は本
発明に係るプリント配線板の製造方法の一実施態様例を
模式的に示す要部断面図、第2図は本発明に係るプリン
ト配線板の製造方法で製造したプリント配線板の使用例
を示す要部断面図、第3図は従来の混成機能回路ユニッ
ト用プリント配線板の要部断面図である。 1・・・・・・外層回路パターン 1a・・・・・・接続用パッド 2・・・・・・ソルダーレジスト膜 3・・・・・・プリント配線板 3′・・・積層板 4・・・・・・スルホール 4a・・・・・・スルホールランド 5・・・・・・化学めっき層 6・・・・・・電子部品のリード
FIGS. 1(a), (b), (c) and (d) are sectional views of essential parts schematically showing an embodiment of the method for manufacturing a printed wiring board according to the present invention, and FIG. FIG. 3 is a cross-sectional view of a main part of a conventional printed wiring board for a hybrid functional circuit unit. 1...Outer layer circuit pattern 1a...Connection pad 2...Solder resist film 3...Printed wiring board 3'...Laminated board 4... ...Through hole 4a...Through hole land 5...Chemical plating layer 6...Lead of electronic parts

Claims (1)

【特許請求の範囲】 主面に所要の回路パターンが設けられかつ、含浸被着し
た樹脂が半硬化状ないし一部未硬化状の基材を少くとも
回路パターンが外表面に位置するように積層し加圧加熱
して硬化一体化する工程と、 前記一体化して得た積層板面に選択的に所要のソルダー
レジスト膜パターンを被着形成する工程と、 前記ソルダーレジスト膜で覆われていない所定の回路パ
ターン領域に化学めっき層を被着形成する工程とを具備
してなることを特徴とするプリント配線板の製造方法。
[Claims] Base materials each having a required circuit pattern on the main surface and semi-cured or partially uncured resin impregnated with the resin are laminated so that at least the circuit pattern is located on the outer surface. a step of curing and integrating by pressurizing and heating; a step of selectively forming a desired solder resist film pattern on the surface of the laminate obtained by the integration; 1. A method for manufacturing a printed wiring board, comprising the step of depositing a chemical plating layer on a circuit pattern area.
JP6787690A 1990-03-15 1990-03-15 Manufacture of printed wiring board Pending JPH03266494A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6787690A JPH03266494A (en) 1990-03-15 1990-03-15 Manufacture of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6787690A JPH03266494A (en) 1990-03-15 1990-03-15 Manufacture of printed wiring board

Publications (1)

Publication Number Publication Date
JPH03266494A true JPH03266494A (en) 1991-11-27

Family

ID=13357557

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6787690A Pending JPH03266494A (en) 1990-03-15 1990-03-15 Manufacture of printed wiring board

Country Status (1)

Country Link
JP (1) JPH03266494A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015167238A (en) * 2009-09-23 2015-09-24 スリーエム イノベイティブ プロパティズ カンパニー Electrical constitution part assembly and flexible lighting assembly

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015167238A (en) * 2009-09-23 2015-09-24 スリーエム イノベイティブ プロパティズ カンパニー Electrical constitution part assembly and flexible lighting assembly

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