JPH03253074A - Solid-state image sensing device - Google Patents

Abstract

PURPOSE:To increase an amplification factor and to prevent a picture quality from being deteriorated by an irregularity in a signal output at each picture- element cell by a method wherein one part of a channel region of a JFET is set as a long and narrow high-concentration region and other regions are set as low-concentration regions in which depletion layers always exist. CONSTITUTION:At a JEET, a feedback capacity is formed of a junction capacity between n<+> semiconductor regions 4 at the upper part of a photodiode region; adjacent picture-element cells are isolated by a field plate 7. A control gate region 3 is connected to a poly-Si interconnection 12 via a contact 5; the drain region 4 is connected to an Al interconnection 11 via a contact 6. A highconcentration region 1 as a channel is formed to be narrow as compared with an n-type semiconductor region between a p<-> semiconductor region 2 and the control-gate p<+> semiconductor region 3. The region 1 is formed in a uniform width along the region 3; an n<-> semiconductor region exists between the regions 1 and 2 and is depleted. A drain current flows as shown by an arrow, and a channel length L is longer than a channel width 2.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a solid-state imaging device, and more specifically, it is constructed by a vertical channel junction field effect transistor (vertical JFET) in which one of a drain electrode and a source electrode is placed on the surface of a semiconductor substrate, and the other is placed inside the substrate. The present invention relates to a pixel amplification type two-dimensional solid-state imaging device formed by arranging a plurality of pixel cells. [Prior Art] As a type of conventional solid-state imaging device, a pixel amplification solid-state imaging device is known in which each pixel cell is provided with an amplification element having a photodetection function and an amplification function. One such pixel amplification solid-state imaging device is the IDM Technical Digest, 16.
4 (1985), page 440, page 443 (■ED
MTechnical Digest, 16.4(1
985), pp. 440-443) in which each pixel cell is composed of a static induction transistor (SIT). The pixel cell is shown in FIG. In the same figure, 54 is an n+ semiconductor substrate that becomes the drain of the SIT, 53 is a p+ semiconductor region that becomes a gate, 52 is an n+ semiconductor region that becomes a source, 5 is a conductive film that forms a gate capacitor for element selection, 55 is trench isolation that isolates adjacent pixel cells. In this solid-state imaging device, when a high voltage is applied to the gate region 53, the source voltage of the pixel cell becomes a signal output voltage corresponding to the amount of light irradiation. The signal output voltage of the above pixel cell is proportional to αGLA/Ca. Here, Cc is the gate capacitance value, A is the area of the light utilization area of the pixel cell, GL is the generation rate of charge due to light,
α is a coefficient determined by the characteristics of SIT. (Problems to be Solved by the Invention) When manufacturing a large number of the above-mentioned pixel cells on a semiconductor substrate, it is difficult to manufacture each pixel cell uniformly, resulting in variations in device characteristics. did not take into account the uniformity of the output signal, and there was a problem that the sensitivity of each pixel cell to light varied greatly, degrading the quality of the reproduced image.In other words, when uniform light was irradiated, Also, the gate voltage of each pixel cell does not change uniformly due to variations in the light utilization area A and variations in the storage capacitance value Cc.Furthermore, even if the gate voltage changes uniformly, the SIT provided in each pixel cell The signal output voltage is not uniform due to variations in the characteristic α of By providing a feedback capacitance between the conversion element and matching the formation area of the feedback capacitance with the light use area, it is possible to eliminate variations in the characteristics of the amplifying element of each pixel cell and the area of the light use area. Patent application No. 1 was filed for a solid-state imaging device that can obtain uniform signal output.
An application has already been filed under No. 43025. FIG. 9 and FIG. 10 are an example of a circuit configuration diagram and a pixel cell of such a solid-state imaging device. In this pixel cell, the amplification element is a fully depleted dual gate vertical JFET (Japanese Patent Application No. 153292/1982). In Figure 9, a fully depleted dual-gate vertical JFE
T21 and MO8FET 22 serving as a load constitute an inverting amplifier that detects and amplifies the potential of the photodiode region. 23 is a feedback capacitor provided between the photodiode and the amplification element. In FIG. 10, 20 is an n-type semiconductor substrate that becomes a source of the JFET, 41 is an n-semiconductor region that becomes a channel, and 4
2 is a P-semiconductor region which becomes a photodiode, 43 is a p◆semiconductor region which becomes a control gate, and 45 is a thin film polysilicon transparent electrode which becomes a drain and further forms a feedback capacitor. Feedback capacitance 23 in FIG. 9 is an MO3 capacitance between thin film polysilicon electrode 45 and photodiode p-semiconductor region 42. Feedback capacitance 23 in FIG. Further, the light utilization region is a p-semiconductor region 42, whose planar region almost coincides with the formation region of the feedback capacitor. A voltage lower than that of the substrate is always applied to the control gate of this JFET. With respect to the photodiode voltage Vpo in the depletion state of this JFET and the punch-through voltage VPT between the control gate P+ semiconductor region 43 and the photodiode P semiconductor region 42, a negative minimum voltage such that VH < Vpo - VPT is applied to the control gate region 43. When VH is applied, the above JF
The drain and source of the ET are rendered non-conductive, and the control gate and the photodiode are rendered conductive, thereby refreshing the charges accumulated in the photodiode region 42. When a higher voltage VM is applied to the control gate region 43, all the terminals of the JFET become non-conductive, and the pixel cell becomes non-selected.6 Furthermore, when a higher voltage VL is applied to the control gate region 43, the channel region A current flows through the pixel cell 41, and the drain voltage of the pixel cell is output as a signal voltage corresponding to the amount of light irradiation. In this way, image signals can be obtained by sequentially selecting all pixel cells. The signal output voltage VS of the above pixel cell is CF+(CF10P)/G. Here, Qs is the signal charge amount, CF is the capacitance value of the feedback capacitor, Cp is the capacitance value other than the feedback capacitor attached to the input terminal of the amplification element, and G is the amplification factor in the open loop of the amplification element. Therefore, when the amplification factor G is large, the above equation becomes CF. Furthermore, since the signal charge amount Qs is proportional to the area A of the light use area of each pixel cell, and the value CF of the feedback capacitance is proportional to the area of the feedback capacitance formation area, the feedback capacitance formation area is further changed to the light use area. By matching, the signal output voltage becomes uniform regardless of the pixel cells. However, the structure of the pixel cell filed earlier had a problem in that the amplification factor G of the inverting amplifier could not be increased, and the amplification factor G did not even reach 2. This is control gate area 4
In the JFET in which 3 and the photodiode region 42 are formed by impurity diffusion, the width of the channel region becomes wider toward the inside of the substrate due to lateral diffusion of impurities, so the channel length of the JFET can be made longer than the channel width Z. First, a drain-source punch-through current occurs due to a low drain voltage, and the train conductance increases when the static characteristics of the JFET are saturated. An object of the present invention is to provide a solid-state imaging device in which the amplification factor of a vertical JFET is increased and the quality of a reproduced image does not deteriorate due to variations in signal output voltage from pixel cell to pixel cell.

[Means to solve the problem]

In order to achieve the above objective, a part of the channel region of the fully depleted dual-gate vertical JFET is made into a long and narrow high concentration region, and the other region of the channel is made into a low concentration region where a depletion layer is always present. The structure is defined as a concentration region. In addition to the above, by setting the deep part of the substrate to a high impurity concentration,
A structure is adopted in which a part of the high concentration region of the channel and a high concentration region of the substrate are directly connected. Further, the concentration and width of the channel region are uniform along the channel, and the length of the channel region is longer than the width. (Function) By the first means, no channel current flows through the low concentration region of the channel of the JFET, so the width of the channel region becomes narrow.Furthermore, by the second means, the width of the source terminal of the JFET is reduced. Transconductance due to lower parasitic resistance
gl increases. Further, with the third means, the width of the channel does not increase even inside the substrate, so the length of the channel region increases.

[Example] A first example of a solid-state imaging device according to the present invention will be described with reference to FIGS. 1 to 3. Fig. 1(a) is a planar structural diagram of a pixel cell used in the solid-state imaging device according to this embodiment, and Fig. 1(b) is a broken line AA' in Fig. 1(a) of the pixel cell.
FIG. 2 is a diagram showing the manufacturing process of the pixel cell, and FIG.
These are the static characteristics of the ET and the input/output characteristics of the inverting amplifier configured by the JFET. The amplification element provided in the pixel cell of FIG. 1 is the aforementioned fully depleted dual-gate vertical JFET,
The feedback capacitance 23 is formed by the junction capacitance between the photodiode p-semiconductor region 2 and the n+ semiconductor region 4 above the photodiode region, and the field plate 7 separates adjacent pixel cells. Control gate region 3 is connected to polysilicon wiring 2 through contact 5, and drain region 4 is connected to aluminum wiring 11 through contact 6. This embodiment is a structure of a vertical JFET in which a high concentration region 1 serving as a channel is narrower than an n-type semiconductor region between a photodiode p-semiconductor region 2 and a control gate p+ semiconductor region 3. . The high concentration region 1 is formed with a uniform width along the boundary with the control gate region 3, and an n-semiconductor region exists between the high concentration region 1 and the photodiode region 2. It is becoming depleted. In the above JFET, the drain current flows along the path indicated by the arrow in FIG. 1(b), and the channel length is longer than the channel width Z. A capacitive feedback type pixel amplification solid-state imaging device having the circuit configuration shown in FIG. 9 is constructed using the above pixel cells. The method for manufacturing the pixel cell according to this example will be described below with reference to FIG. 2. First, a 5i3N4 (silicon nitride) film 1
5, and remove the Si and N4 films in the region 1a forming the channel and control gate of the JFET (Second
Figure (a)). Next, using this Si, N, film 15 as a photomask, P(
After implanting phosphorus ions, thermal diffusion is performed with the Si and N4 films still attached (FIG. 2(b)). Furthermore, B (boron) ions are implanted using the Si3N4 film 5 as a mask. After removing the 813N4 film and undergoing a thermal diffusion process, a 5in2 (silicon oxide) film 18 and a field plate 7 are formed, and a photoresist 6 for setting the photodiode p-semiconductor region 2a is applied (see FIG. 2). C)). Furthermore, B ions are implanted using the field plate 7 and resist 16 as masks. After removing the resist, a thermal diffusion process is performed to remove the n
+A resist 17 for setting the semiconductor region 4 is applied (FIG. 2(d)). Thereafter, As (arsenic) ions are implanted using the field plate 7 and resist 17 as masks. Furthermore, polysilicon wiring, aluminum wiring, and insulating layers between each layer are formed to complete the process (FIG. 2(e)). The fully depleted dual-gate vertical JFET in the pixel cell thus completed exhibits the static characteristics shown in FIG. 3(a) when the voltage VL is applied to the control gate region. The vertical axis of the figure is the drain current i4 of the JFET, and the horizontal axis is the drain-source voltage ds, with the voltage Vgs between the photodiode region and the source input of the JFET as a parameter. When applying voltage VL to the control gate region,
The photodiode voltage becomes a bias voltage Va depending on the amount of light irradiation, and the output voltage is lower than the voltage at reset by the voltage Vs shown by the above equation. Figure 3(b) shows the J FET 21 having the above static characteristics and the load 22 represented by the load curve shown by the broken line in Figure 3(a).
The horizontal axis of the figure is the input voltage, and the vertical axis is the output voltage. The amplification factor of this inverting amplifier is 2 to 3, which is higher than the amplification factor of about 1.5 in the structure of FIG. Incidentally, in the vertical JFET shown in FIG. 9, the causes of characteristic variations are variations in the boundaries of the impurity implanted regions forming the control gate region and the photodiode region, variations in the impurity diffusion length, and variations in the amount of implanted impurities per unit area. there were. However, in the vertical JFET shown in FIG. 1, the control gate p+ boundary between the control gate p+ semiconductor region 3 and the photodiode p- The distance between the boundaries of the semiconductor regions 2 is set to be long, and a depletion layer exists there. Therefore, due to variations in the distance between the boundary 1a of the impurity implanted region forming the control gate and channel and the boundary 2a of the impurity implanted region forming the photodiode, which had a large influence on the characteristics in the conventional amount, the shape of the region where the current flows is There is almost no change, and the characteristics of the element are almost unchanged. As a result, in the JFET having this structure, variations in amplification factor are further reduced. In FIG. 3, the impurity implantation regions forming the control gate and the channel are the same, but the two regions do not need to be the same except for the boundary where the JFET channel is formed, and Si, N, and film Alternatively, it is also possible to limit one of the impurity implantation regions using photoresist or the like. Furthermore, a JFET with higher characteristics may be obtained if the boundaries where the channels of the JFETs in the two regions are formed are not the same. In this case, the above Si3N. By growing an oxide film or the like on the side surface of the film 15 and then implanting one of the impurities, a channel region can be formed with high precision. Furthermore, although Fig. 2 shows a case where the impurity diffusion length that forms the control gate is longer than the impurity diffusion length that forms the photodiode, it is also possible to create the opposite relationship by changing the order of impurity implantation or the type of impurity. is also possible. Next, a second embodiment of the present invention will be described using FIG. 4. This embodiment is also a vertical JFET in which the highly doped channel region 61 is narrower than the n-type semiconductor region between the photodiode p-semiconductor region 2 and the control gate P1 semiconductor region 3.
This is a structure of The high concentration region 61 is formed vertically with a uniform width from the surface of the substrate to the deep part, and n-semiconductor regions exist on both sides of the high concentration region, which are depleted. In this embodiment, the channel region 61 is formed by implanting n-type impurities into a narrow gap a plurality of times while gradually changing the implantation energy. Other than this point, the pixel cell is the same as the pixel cell shown in FIG. The horizontal broken line in the channel region 1 in FIG. 4 indicates the position where the n-type impurity concentration due to each of the above-mentioned impurity implantations is maximum. Moreover, the above impurities are diffused only over a very short distance from the time of implantation. When the control gate and photodiode regions are formed by a thermal diffusion process, the n-type impurity region expands into a bell shape due to lateral diffusion. However, since the highly doped n-type semiconductor region 61 with uniform width and concentration is formed deep and the regions on both sides of this highly doped region are depleted, the drain current passes through the highly doped region and J
The FET channel will be long and narrow. Next, a third embodiment of the present invention will be described using FIG. In this embodiment, the boundary of the channel region 71 is the pn junction between the photodiode p-semiconductor region 72 and the control gate p+ semiconductor region 73, and is a structure of a vertical JFET with a long channel length and uniform width and concentration. be. In the above JFET, both the photodiode region 72 and the control gate region 73 have a uniform impurity concentration from near the substrate surface to deep, and the boundary between the two regions and the channel n-type semiconductor region 71 between them is formed perpendicular to the substrate. . In this embodiment, both the photodiode region 72 and the control gate region 73 are formed by implanting p-type impurities into the same region a plurality of times with slightly different implantation energy. The horizontal broken line in FIG. 5 indicates the position where the impurity concentration due to the above-mentioned impurity implantation is maximum. and,
The above impurities are diffused only over a very short distance from the time of implantation. With this method, almost no lateral diffusion of impurities occurs,
Photodiode region 72 and control gate region 7
3 can be formed. In this structure, the channel of the JPET is clearly an n-type semiconductor region sandwiched between the photodiode region 72 and the control gate region 73, and since the boundary is formed almost perpendicular to the substrate, the JF
The ET channel will be long and narrow. In this embodiment, the impurity concentration of the channel region 71 is the same as the substrate concentration, but this region may be made to have a higher impurity concentration than the substrate in advance and the J FET described above may be formed thereon. Next, a fourth embodiment of the present invention will be described using FIG. 6. In this embodiment as well, the boundary of the channel region 81 is the pm junction surface with the photodiode P-semiconductor region 82 and the control gate P+ semiconductor region 83, and is one structure of a vertical JFET with a long channel length and uniform width and concentration. be. In this embodiment, the pn junction surface, which is the boundary of the channel region 81, is formed by lateral diffusion synthesis of n-type and p-type impurities in mutually opposing directions. That is, the boundary between the photodiode region 82 and the channel region 81 is a pn junction between the p impurity diffusion region 82a and the n impurity diffusion region 81a, and the boundary between the control gate region 83 and the channel region 81
The boundary is a pn junction between the p+ impurity diffusion region 83b and the n impurity diffusion region 81b. Note that the broken lines in FIG. 6 are the boundaries of the respective impurity diffusion regions. By this method, the boundary of the channel region 81 is formed substantially perpendicular to the substrate, and the channel width is substantially uniform.
It becomes ET. Next, a fifth embodiment of the present invention will be described using FIGS. 7 and 8. FIG. 7 is a cross-sectional structural diagram of a pixel cell of a solid-state conversion device according to the present embodiment, and FIG. 8 shows static characteristics of the JFET in the pixel cell of FIG. 7(a) and an inverting amplifier constructed using the JFET described above. is the input/output characteristic of Like the JFET in the pixel cell in Figure 1, a narrow high concentration region is provided in the n-type semiconductor region between the photodiode P-semiconductor region 2 and the control gaiter bioconductor region 3, and this region is used as a channel. It has already been mentioned that by forming a structure in which other regions are depleted, variations in the shape of the element are reduced. However, in order to reduce the shape variations of the elements. When the substrate impurity concentration is low, the substrate resistance value increases and the transconductance of JPET g. This causes a decrease in the amplification factor. However, the seventh
As shown in Figure (a), if the surface of the substrate is an n- semiconductor region, the deep part of the substrate is an n+ semiconductor region, and the high concentration region is connected to the high concentration n-type semiconductor region of the channel mentioned above, the channel of the JFET will be formed. It becomes possible to set the nearby impurity concentration and the impurity concentration in the substrate separately. Therefore, while suppressing variations in device characteristics due to boundary variations in the impurity implanted regions, the substrate resistance value can be lowered and the above-mentioned mutual conductance gm can be set to a large value. the result,
The amplification factor improves to 2.5-4. The above substrate concentration distribution is formed by epitaxial growth or diffusion of a small amount of p-type impurity. In addition, the low concentration region near the substrate surface to suppress variations in device characteristics due to boundary variations of impurity implanted regions does not need to be the entire surface of the substrate;
It is also possible to form a low concentration n-type semiconductor region by implanting P-type impurities only around the channel. Furthermore, in FIGS. 7(a) and 7(b), the region between the channel region 1 and the photodiode region 2 is a lightly doped n-type semiconductor region, but this region is an intrinsic semiconductor region or a lightly doped p-type semiconductor region. There may be. In this structure, the boundary of the channel region is determined by the pn junction position, as shown in FIG.
Since the T channel is determined by the shape of the heavily doped n-type semiconductor region, the characteristics of the device hardly change. Moreover, the above substrate concentration distribution improves the amplification factor in all vertical type JFETs in which a part of the channel region is made into a high concentration region and a current flows there. In all of the first to fifth embodiments described above, a solid-state imaging device is described in which an n-channel JPET is provided in each pixel cell, but it is also possible to provide a p-channel JFET. It is also possible to form the upper &JFET in an n-type well on an n-type semiconductor substrate or in an n-type well on a p-type semiconductor substrate. In this embodiment, the drain electrode of the JFET is placed on the surface of the semiconductor substrate, and the substrate serves as the source electrode, but it is also possible to use the substrate as a train electrode and place the source electrode on the substrate surface. It is also possible to use an insulated gate capacitor instead of a pn junction capacitor as the feedback capacitor 23. Furthermore, the present invention can be applied to an amplification element in a pixel cell of a pixel amplification solid-state imaging device that does not have a feedback capacitance, thereby reducing variations in the structure of the element. Furthermore, the present invention can also be applied to a JFET having a structure in which the photodiode region is the only control terminal. Effects of the Invention According to the present invention, it is possible to form a vertical JFET in which no punch-through phenomenon occurs between the drain and source, and to configure an inverting amplifier with a high amplification factor. Furthermore, variations in the shape of the JFET can be reduced. By providing a capacitive feedback circuit using the above amplification element for each pixel cell, it is possible to achieve high photosensitivity and uniform signal output regardless of variations in the light utilization area of each pixel cell, storage capacitance, and characteristics of the amplification element. Therefore, it is possible to provide a solid-state imaging device that can obtain high-quality reproduced images.

[Brief explanation of drawings]

FIG. 1(a) is a plan view of a pixel cell according to an embodiment of the present invention;
FIG. 1(b), FIG. 4, FIG. 5, FIG. 6, and FIG. 7 are cross-sectional views of pixel cells used in solid-state imaging devices according to embodiments of the present invention, and FIG. 2(a) to e) is a cross-sectional view showing the manufacturing process of the pixel cell shown in Fig. 1, Fig. 3 (a) is a static characteristic diagram of the vertical JFET in the pixel cell shown in Fig. 1, and Fig. 3 (b)
is an input/output characteristic diagram of the inverting amplifier using the JFET as the amplifying element, and FIG. 8(a) is the JFET in the pixel cell of FIG. 7(a).
A static characteristic diagram of the FET; an input/output characteristic diagram of the inverting amplifier; FIG. 8(b) is an input/output characteristic diagram of the inverting amplifier of the pixel cell; FIG. 9 is a circuit configuration diagram of a capacitive feedback type pixel amplification solid-state imaging device; FIG. 10(a) is a plan view of a pixel cell of a capacitive feedback type pixel amplification solid-state imaging device, and FIG. 10(b) is a cross-sectional view of the cell.
FIG. 11 is a perspective view of a pixel cell of a pixel amplification solid-state imaging device using a conventional SIT as an amplifying element. Explanation of symbols 1.41, 61, 71.81 ... N-type semiconductor region that becomes a channel 2.42, 72.82 ... P- semiconductor region that becomes a photodiode 3.43
,73.83...p+ semiconductor region 4 that becomes a control gate
...N+ semiconductor device 44 which becomes a drain and forms a feedback capacitance Thin film polysilicon 5.6 which becomes a train and forms a feedback capacitance...Contact 7...Field plate 11...Aluminum wiring 1
2゜45... Polysilicon wiring 20... N-type semiconductor substrate serving as source 21... Fully depleted dual gate vertical J FET 22... Load transistor 23... Feedback capacitance 24... Coupling capacitance 25...
・Clamp switch 26...Memory capacity 27・
...Signal write switch 28...Signal read switch 29...Amplifier 30...Horizontal signal line 31...
・Reset switch (0) 2 Figure <e) 1 Figure 53 - Gate diagram (□) (b) Input voltage VgsCV) No 7 Flash (1) (G) Cc/) Figure 53 - Gate diagram (□) (b) Input voltage VgsCV) (Length) (b) Manpower is reversedCV〕lρ

Claims (1)

[Claims] 1. Regions of a second conductivity type are provided on the surface of a semiconductor substrate of a first conductivity type, and at least a part of the region of the first conductivity type between the second conductivity type regions. In a solid-state imaging device in which a plurality of pixel cells constituted by junction field effect transistors having a current path of The region has a higher concentration than other regions of the first conductivity type region between the regions, and the length of the high concentration first conductivity type region is larger than the width of the high concentration first conductivity type region. Characteristic solid-state imaging device. 2. The solid-state imaging device according to claim 1, wherein the high concentration first conductivity type region is in contact with one of the second conductivity type regions. 3. In claim 2, the high concentration first conductivity type region is connected from the substrate surface to below the one of the second conductivity type regions, and the current flow is carried out within the high concentration first conductivity type region. A solid-state imaging device characterized in that an impurity concentration distribution of the high concentration first conductivity type region in a cross section perpendicular to the current path is equal along the current path. 4. In claim 3, the one second conductivity type region and the high concentration first conductivity type region are formed by lateral diffusion of first conductivity type impurities and second conductivity type impurities in the same direction. A solid-state imaging device characterized by: 5. The solid-state imaging device according to claim 1, wherein the high concentration first conductivity type region is formed by implanting a plurality of first conductivity type impurities with different implantation energies. 6. In claim 1, the substrate has a highly concentrated first conductivity type region in a deep portion, and the highly concentrated first conductivity type region between the second conductivity type regions has a highly concentrated first conductivity type region in a deep portion of the substrate. A solid-state imaging device characterized by being connected to a region of one conductivity type. 7. Regions of a second conductivity type are provided on the surface of a semiconductor substrate of a first conductivity type, and at least a part of the region of the first conductivity type between the second conductivity type regions is used as a current path. In a solid-state imaging device in which a plurality of pixel cells composed of junction field effect transistors are arranged, the depth of the second conductivity type region is the distance between the second conductivity type regions at the deepest part of the second conductivity type regions. A solid-state imaging device characterized by being larger than. 8. The solid-state imaging device according to claim 7, wherein the first conductivity type region between the second conductivity type regions is formed by implanting a plurality of first conductivity type impurities with different implantation energies. 9. The solid-state imaging device according to claim 7, wherein the second conductivity type region is formed by implanting a plurality of second conductivity type impurities with different implantation energies. 10. In claim 7, boundaries between the first conductivity type region and the second conductivity type region on both sides of the first conductivity type region are both of the first conductivity type and the second conductivity type in different directions. A solid-state imaging device characterized in that it is formed by lateral diffusion of impurities. 11. Regions of a second conductivity type are provided on the surface of a semiconductor substrate of a first conductivity type, and at least a part of the region of the first conductivity type between the second conductivity type regions is used as a current path. A solid-state imaging device in which a plurality of pixel cells each composed of a junction field effect transistor are arranged, wherein the length of the current path is longer than the maximum width of the current path.