JPH03259461A - Cd-wo device - Google Patents

Abstract

PURPOSE:To relieve the load of a CPU and a memory in a host system section by using a driving system section composing this CD-WO device to generate a prescribed data other than the user data stored in a CD. CONSTITUTION:A system controller 6 activates a header part data generating circuit 9 and a sub header part data register 10, and a header data and a sub header data sent from the circuit elements are written respectively to a prescribed address in a buffer RAM 5. When the data of a SYNC pattern, a header and a sub header are stored in the buffer RAM 5, a control circuit 7 sends a signal to a sequencer 12, which activates an EDC, ECC addition circuit 13 by receiving the signal. Thus, the driving system section generates the data such as the SYNC pattern, the header, the sub header, the EDC and the ECC to form a block in a prescribed format. Thus, the load of the CPU and the memory in the host system is relieved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CD-WO (Compact Disc-Write Once) device.

[Prior Art] In types such as CD-ROM (Compact Disk - Read Only Memory) and CD-I (Compact Disc - Interactive), in which the user does not write data to the CD, there is a process when writing data to the CD. The format has already been decided. On the other hand, CD-W
Even for CDs such as O, which allow the user to write data to the CD, systems are being developed for writing and reading data to and from the disc in a format similar to the CD-ROM format. In this specification, a CD refers to a recording medium in which digital information is optically or magnetically readably written on a rotating disk, and is not limited to its size.

In the format of CD-ROM and CD-I, as shown in Figure 3, depending on the mode and form, a sync pattern in which data for identifying the -block is recorded in one block of 2352 bytes; A header that records data that defines A time and mode, which is time information on a CD, user data, EDC (error detection code) that is data for error detection, and FCC (error detection code) that is data for error correction. Collection code), and in the CD-I, a subheader that defines the type, format, form, etc. of user data is provided, and these constitute one block.

Since user data is processed in the so-called host system section other than the so-called drive system section, which is the component that actually writes information to the CD, for example, when writing data to a CD using CD-WO, the above-mentioned host system Data such as the above-mentioned sync pattern must be added to the user data possessed by the host system in either the drive system section or the drive system section.

If these are added to the host system, the burden on the central processing unit (hereinafter referred to as CPU) and memory will increase, which is inefficient. In addition, since the A time data recorded in the ladder data section can be incremented sequentially for each block, and the mode is usually constant within a track, these can be stored in the drive system section of the CD-WO. It is more efficient to generate and add the

Therefore, an object of the present invention is to provide a CD-WO device in which data such as a sync pattern, a header, and a sub-header are added in the drive system section of the CD-WO device.

[Means for Solving the Problems] The present invention has a host system section that holds data to be written to an optical disk, and a drive system section that writes the data to the optical disk. In a CD-WO device that writes information to an optical disc in a format that conforms to the standard, there is a control unit that controls the operation of each component by supplying predetermined data from the host system, and a control unit that controls the operation of each component by supplying predetermined data from the host system, and a control unit that controls the operation of each component according to the above format. a data creation section that creates predetermined data under the control of the control section; and a write/readable data creation section that stores the user data supplied from the host system and the predetermined data created by the creation section according to the format. The drive system section is characterized in that the drive system section includes a memory and a data sending section that sends the data written in the memory to the next stage circuit.

[Operation] Since the codrive system section creates predetermined data other than user data in the data creation section, it acts to reduce the load on the CPU and memory provided in the host system section.

[Embodiment] In FIG. 1 showing the configuration of an embodiment of the drive system section provided in the CD-WO device of the present invention, the output of the host interface l to which user data to be recorded on a CD possessed by the host system is supplied. The side is connected to an address bus 2, a data bus 3, and an abitration circuit 4, which will be described later, provided in circuit elements constituting this drive system section. Also, a buffer RAM 5 is connected to the address bus 2 and data bus 3 for storing various data such as sync patterns recorded on the CD.
User data sent from the host system is DMA
Or host interface 1 by program transfer.
1 is stored in the buffer RAM 5 via the data bus 3. The buffer RAM 5 is divided into pages for each block. For example, when writing data for CD-1 form I, the host system writes 2048 pages from relative addresses 24 to 2071 as shown in FIG. 3 in each page. Stores bytes of user data. Note that the above block corresponds to a sector when information is written on a floppy disk, which is a magnetic recording medium.

The system controller 6 independently sends and receives commands to and from the host system, and receives and receives from the host system the data to be recorded on the CD, such as the initial value of the header, the value format of the subheader, and the number of transfer blocks. This is a circuit that controls the operation of the The output side of the system controller 6 includes a control circuit 7, a header data generation circuit 9, a subheader data register 10,
It is connected to the address generation circuit 11, the sequencer 12, and the system controller data bus 15.

The output side of the control circuit 7 includes an abitration circuit 4, a sync pattern generation circuit 8, a header part data generation circuit 9, a subheader part generation circuit IO, an address generation circuit 11 . It is connected to the sequencer 12 and to the enable terminal of the respective buffer connected to the output side of the components 8 to 11 mentioned above.

Such a control circuit 7 starts its operation in response to a control signal supplied from the sequencer 12, which starts its operation in response to a synchronization signal supplied from the host system, and starts its operation in response to a control signal supplied from the system controller 6. It controls the operations of the components 8 to 11, controls the exit of data generated by these components, and controls the operation of the abitration circuit 4. Further, the output sides of the components 8 to IO are respectively connected to the data bus 3 via the buffers, and the output side of the address generation circuit 11 is connected to the address bus 2 via the buffers.

The sync pattern generation circuit 8 has a CD-ROM and a CD-ROM.
This is a circuit that generates a sync pattern defined in the No. 1 standard.

The header part data generation circuit 9 is set with the initial value data of A time supplied from the system controller 6.
This circuit increments this in response to instructions from the control circuit 7 and sequentially sends out the data.

Note that the value of the mode byte in the header part is set by the system controller 6, but the first three blocks and the last three blocks of all the blocks recorded on the CD at one time are set by the control circuit 7. Controlled to generate special code.

The subheader section data register 10 is a circuit that receives subheader values from the system controller 6 and stores them.

The address generation circuit 11 is a circuit that generates an address for writing data such as the sync pattern and the header into the buffer RAM 5 in accordance with the format shown in FIG.

The abitration circuit 4 is a circuit that generates a signal for adjusting when there is a conflict in writing data such as the sync pattern or header to the buffer RAM 5.

The output side of the sequencer 12 is connected to the control circuit 7 and EDC, E.
EDC and FCC addition circuit 13 that adds each CC data
The sequencer 12 is connected to the components 8 to IO
When the control circuit 7 supplies a signal indicating that the generated data has been stored in the buffer RAM 5, the operation of the EDC/FCC addition circuit 13 is started.

The EDC, FCC addition circuit 13 is for CD-ROM and CD
This circuit complies with the -I standard and calculates EDC and ECC data, and its output side is connected to the address bus 2, data bus 3, and abitrage circuit 4. Therefore, after each data such as the above-mentioned sync pattern and header is stored in the buffer RAM 5, the EDC and FCC addition circuit 13 adds EDC and FCC data under the control of the sequencer 12.
data is stored in the buffer RAM 5 via the data bus 3.

The serial interface 14 is connected to the address bus 2, the data bus 3, and the abitration circuit 4.-The addition of data such as the sync pattern, header, user data, EDC, and ECC forming the block to the buffer RAM 5 is completed. The page data is read out via the data bus 3, and the read data is serially sent to the next stage signal processing circuit that performs data processing in order to write the data onto the CD.

The operation of the CD-WO device configured as described above will be explained below with reference to FIGS. 1 and 2. In addition, in Fig. 2, Sl
, S2... means step l, step 2...
・Represents. Further, in the flowchart shown in FIG. 2, it is assumed that m blocks are stored in the buffer RAM 5.

In step 1, when a command is supplied from the host system to the system controller 6, the system controller 6 writes the initial value of the header data supplied from the host system to the header section data generation circuit 9, and writes the initial value of the header data supplied from the host system to the subheader section data register lO. Write the ladder data to the sub. The system controller 6 also instructs the control circuit 7, address generation circuit 11, and sequencer 12 to format the block configuration. Further, user data is sent from the host system and stored in the buffer RAM 5 via the host interface 11 data bus 3.

In step 2, it is determined whether the block to be stored now can be stored, and if it is not possible to store it, the process is terminated,
If the data can be stored, the process moves to step 3.

In step 3, the system controller 6 sends a signal to the sequencer 12, and the sequencer 12 sends an operation start signal to the control circuit 7.

Therefore, the control circuit 7 operates the sync pattern generation circuit 8 and the address generation circuit 11. Therefore, the sync pattern data generated and sent out by the sync pattern generation circuit 8 is written to relative addresses 0 to 11 in the buffer RAM 5 in accordance with the address sent out by the address generation circuit 11 via the data bus 3.

In the next step 4, out of the total number of blocks recorded on the CD each time, 3 blocks are counted from the first block that starts recording first.
This step is related to creating a block from the third block to the last block, and when recording normal user data, the process in step 4 is not performed and the process in step 3 above is performed. Move to step 5.

The first and last three blocks of these total blocks are C
Since there is a possibility that writing data to D may become unstable, special data is recorded.

That is, in step 4-1, the first block and the last block are the targets of processing, and these blocks are added with the ladder data and become link blocks. Step 4
In -2, the second block from the beginning is the processing target, and the first run-in data is added to this block. In step 4-3, the third block from the beginning is to be processed, and to this block, the Herad data is added and the second run-in data is added. In step 4-4, the third block from the end is to be processed, and to this block, the Herada data is added and the first run-out data is added. In step 4-5, the second to last block is to be processed, and to this block, hellada data and second run-out data are added.

Furthermore, by supplying an external control signal to the header part data generation circuit 9, a function is provided that allows selection of whether to output the A time written in the system controller 6 as is or to output it after being incremented. In addition, by providing a function that can generate mode bytes according to link blocks, first run-in blocks, second run-in blocks, user data, first run-out blocks, and second run-out blocks according to external signals, It is possible to realize a system in which the flow shown in is automatically executed.

In steps 5 and 6, similarly to step 3 described above, the system controller 6 operates the header part data generation circuit 9 and the subheader part data register 10, and generates header data and sub-ladder data sent from these circuit elements. are written to predetermined addresses in the buffer RAM 5, respectively. For CD-ROMs in which 0 is specified to be written in a predetermined location in a block, such as mode 1 in a CD-ROM, predetermined data is written in the predetermined location.

When the sync pattern, header, and subheader data are stored in the buffer RAM 5, the control circuit 7 sends a signal to the sequencer 12, and the sequencer 12 receives this signal to perform EDC.

The ECC addition circuit 13 is driven. Therefore, step 7
and 8, the EDC and FCC data are stored in the buffer RAM 5 from the EDCECC addition circuit 13 via the data bus 3.

One block is completed through the above operations, and the data constituting this block is transferred from the serial interface 14 to the data bus 3 and the serial interface 14 in step 9 in order to record the data onto the CD. is sent to a signal processing circuit that processes the signal.

In step 10, the number of blocks recorded on the CD is counted, and then the process returns to step 2 and the same process as described above is performed.

In addition, in FIG. 2 and the above explanation, data transfer from the host system and data transmission from the serial interface 14 are shown as sequential flows for easy understanding, but these processes are actually pipelined. and executed in parallel.

In this way, the sync pattern is created in the drive system section.
By creating header, subheader, EDC, and FCC data and configuring blocks in a predetermined format, the load on the CPU and memory in the host system can be reduced.

Furthermore, the amount of data supplied from the host system to the drive system section can be reduced.

In addition, since the sync pattern, header, and subheader data are added in advance to the address of the buffer RAM 5 corresponding to the format, the encode circuit for EDC and FCC data can be created by adding part of the EDC and FCC decoding logic and a small circuit. can be realized.

Also, increment of A time, link, run-in,
Since a header is automatically generated and added according to each block of runout, the burden on the software of the system controller can be reduced.

[Effects of the Invention] As described in detail above, according to the present invention, by creating predetermined data other than user data to be recorded on a CD in the drive system unit constituting the CD-WO device, the CPU in the host system unit can .

It is possible to reduce the burden on the memory and allow the CD-WO device to operate efficiently.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the CD-WO apparatus of the present invention, FIG. 2 is a flowchart showing the operation of the apparatus shown in FIG. 1, and FIG. FIG. 3 is a diagram showing the configuration of blocks used. 9... Header section data generation circuit, IO... Subheader section data register, 11... Address generation circuit, 12... Sequencer, 13... E
DC, ECC addition circuit, 14... serial interface.

Claims (1)

[Claims] (1) It has a host system section that holds data to be written on an optical disk, and a drive system section that writes the data on the optical disk, and has a
In a CD-WO device that writes information on an optical disc in a format that conforms to the D-I standard, there is a control unit that controls the operation of each component by supplying predetermined data from the host system, and a control unit that controls the operation of each component based on the specified data supplied from the host system. a data creation unit that creates predetermined data other than user data under the control of the control unit; and a data creation unit that stores the user data supplied from the host system and the predetermined data created by the creation unit in accordance with the format. A CD-WO device, characterized in that the drive system section includes a readable and writable memory and a data sending section that sends data written in the memory to a next-stage circuit.