JPH0325943B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to a resistor device used in a voltage divider circuit that divides voltage according to a resistance ratio.

Possible examples of this type of voltage dividing resistor used in a semiconductor integrated circuit device include a polysilicon resistor, a diffused resistor with a high impurity concentration, and a well resistor with a low impurity concentration. As this impurity, a P-type impurity is usually used.

Among these, polysilicon resistors and diffused resistors (for example, surface concentration 10 ¹⁸ atoms/cm ³ ) have the advantage that their resistance values are less dependent on voltage. Therefore, in addition to being used as a general resistor, it is also used in gain adjustment parts of operational amplifiers (OP amplifiers) that require high relative accuracy, and A/D conversion that requires absolute accuracy. However, since these have a small sheet resistance ρ _S , they have the disadvantage that they require a large area to obtain a desired resistance value. For this reason, with the recent trend toward higher integration of ICs, there is an idea of using a semiconductor region with a large sheet resistance ρ _S (low impurity concentration), such as a well region (for example, a surface concentration of 10 ¹⁵ atoms/cm ³ ), as a resistor. However, since the resistance value of a semiconductor region with a low impurity concentration, such as the well resistance, has a problem in terms of accuracy, it has not been put to practical use in fields where high relative or absolute accuracy is required. To explain the reason in detail, since the junction between the substrate and the well region is a junction between low impurity concentration regions, a depletion layer tends to extend from the junction when a voltage is applied. For this reason, the effective cross-sectional area of the well region as a resistor becomes susceptible to modulation, so the resistance value fluctuates due to fluctuations in the applied voltage.Moreover, the extension of the depletion layer differs depending on the location, so The resistance value varies.

Therefore, an object of the present invention is to increase the resistance of devices such as gain adjustment of OP amplifiers and A/D converters in order to reduce the power consumption and occupy space, and at the same time to reduce the voltage dependence of the resistance value. The purpose of this invention is to provide a high-precision resistor (especially for voltage division) that eliminates this problem.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.

FIG. 1 shows a circuit diagram of an OP amplifier to which the present invention is applied. The input voltage V _IN is applied to the non-inverting input terminal of the illustrated OP amplifier, and the output of the OP amplifier is fed back to the inverting input terminal via a resistor R ₁ . Resistors R ₁ and R ₂ adjust the amount of feedback input voltage by adjusting the ratio of their resistance values, adjust the gain G _V of this OP amplifier, and adjust the output voltage V _OUT to its design value. This is to correct the value to a highly accurate value. That is, V _OUT with respect to V _IN is expressed as V _OUT = V _IN · (R ₁ + R ₂ )/R ₂ . If the gain G _V = (R ₁ + R ₂ )/R ₂ , then V _OUT is obtained by multiplying V _IN by G _V. Therefore, even if the input voltage of an individual IC varies by, for example, ±10% from its design value, it can be corrected by adjusting G _V , that is, by adjusting the values of R ₁ and R ₂ .
High accuracy of V _OUT to design value (e.g. ±1%)
You can get it at

According to the present invention, the gain adjustment portion of the OP amplifier mainly composed of such resistors R ₁ and R ₂ is specifically constructed as shown in FIG. 2. This gain adjustment section includes a resistor section 1 for forming resistors R ₁ and R ₂ ;
It consists of a switch group 2 for adjusting the resistance values of R ₁ and R ₂ of this resistance section 1, and a switch group control circuit 3 for controlling the switch group 2. In addition, a in the figure
Points A, b and c correspond to points a, b and c in FIG.

The resistor section 1 is a resistor made of a low impurity concentration region.
It consists of a large number of _R0s connected together. _R10
is the fixed resistance of R ₁ consisting of m R ₀ , R ₂₀
is the fixed resistance portion of R ₂ consisting of n R ₀ s. Then, the seven R ₀ between R ₁₀ and R ₂₀ are distributed to R ₁ or R ₂ by switch group 2, and based on this, the ratio of the resistance values of R ₁ and R ₂ is adjusted respectively. do.

Switch group 2 is a tree-shaped N-channel MOSFET
(Metal Oxide Semiconductor Field Effect
Transistot) selectively conducts Q ₁₁ to Q ₃₂ and
One current path is formed in the shaped wiring from the contact point (point c) of R ₁ and R ₂ to point b.

In the switch group control circuit 3, a high voltage is applied between one of the bonding pads _P1 to _P3 and _P4 to connect the corresponding polysilicon fuse _f1.
~ Melt and cut (fuse) f ₃ , MOSFETQ ₁₁ ~
Fix the signal applied to the gate electrode of _Q32 .

For example, in FIG. 2, f ₁ and f ₂ are fused to form a current path from point c through Q ₁₂ , Q ₂₁ , and Q ₃₁ to point b. In other words, since the resistance R _I and the resistance R _f have a relationship of R _I > R _f , P ₀
If V _DD is applied to P ₄ and −V _SS is applied to P 4 , the potential of pads P ₁ and P ₂ corresponding to the blown fuse becomes +V _DD
Therefore, the potential of pad _P3 becomes -V _SS . These signals are applied to switch group 2 via inverters IV ₁₁ to IV ₃₂ . Therefore, switch group 2
The MISFETs conducting in Q ₁₂ , Q ₁₄ , Q ₁₆ , Q ₁₈ ,
Q ₂₁ , Q ₂₃ , Q ₃₁ , and the others are non-conducting. Therefore, one current path is set by the tree-shaped switch.

Next, the structure of the resistance section 1 will be explained in detail.

FIG. 3 shows the layout pattern of the resistor section 1 described above, in which one end of the P-WELL with a low impurity concentration region (surface concentration 10 ¹⁵ atoms/cm ³ ) used as a resistor is connected to point a, and the other end is connected to the ground GND. It is connected.
High concentration region (surface concentration 10 ¹⁸ atoms/cm ³ ) SR ₁ , SR ₂ ,
SR ₃ ... is selectively formed in a position where the oxide film 4 does not exist in a self-aligned state with the pattern of the field oxide film 4, as shown in FIG.
Further, it is provided so as not to be electrically connected to any other area. Further, in the portion to be connected to the switch group 2 mentioned above, the high concentration region extends to the switch group, and forms, for example, the source/drain region of MISFET.

The interval L ₁ between these high concentration regions is P-WELL
The diffusion depth is equal to or less than the diffusion depth of X _j . With this interval L ₁ , the low concentration area P-WELL
The resistance component of the resistor 1 is the resistance R ₀ shown in FIG. 2, and the resistor 1 is made up of a large number of R ₀ arranged in series.
Of course, the high impurity concentration regions SR ₁ , SR ₂ ... also have resistance, so their value needs to be taken into account, but these SR ₁ and SR ₂ also have high impurity concentrations, so the junctions should be placed so that they are not affected by the junction. Since it is formed to be sufficiently shallow from the surface, its resistance value can be formed accurately with respect to the design value.

In this way, multiple high concentration regions SR ₁ , SR ₂ ,
By forming SR ₃ ... across the low concentration region P-WELL at a constant pitch and at a depth sufficiently shallower than the P-WELL, lines of electric force (equal (perpendicular to the potential line) 5 is generated so as to connect adjacent high concentration regions. That is, only the region cut by the electric lines of force 5 (that is, the region near the surface) contributes to the resistance R due to the P-WELL, and therefore the depletion layer 6 is located on the low concentration region P-WELL side as shown by the dashed line. Although it spreads to , it does not substantially affect the effective portion of the resistance R. Therefore, the extension of the depletion layer 6 varies depending on the applied voltage (voltage at point a), and the low concentration region P-
Even if the cross-sectional area of the WELL is modulated, the resistance value R will not change, making it possible to obtain a highly accurate resistance with no voltage dependence, and the above R ₀ ,
R ₁₀ and R ₂₀ can be formed as designed values. Therefore, in a circuit like the one shown in Figure 1, especially when V _IN is ±10%,
It will be understood that this is effective when it is desired to adjust V _OUT with high accuracy. According to actual measurements,
When V _IN varies by ±10% from the design value
V _OUT was achieved with high accuracy of ±0.4% of the design value.

In addition, by using the low concentration region P-WELL as a resistor, the sheet resistance ρ _S of the resistor becomes large and the current flowing through it is small, reducing power consumption, and the desired resistance can be achieved in a small area. can be formed, and high integration can be achieved. This effect is a great advantage in circuits such as those shown in FIGS. 1 and 2.

It has been experimentally confirmed that it is important that the interval L between the high concentration regions is smaller than the depth x _j of the low concentration regions (x _j /L≧1). As shown in FIG. 5, an N ^- type substrate 7 is used as a test sample.
A P ^- type low concentration resistance region P-WELL is formed inside.
P ⁺ type region SR as a terminal region on both ends of this,
SR' is prepared, and the ratio of x _j of P-WELL to the distance L between high concentration region SR-SR' (x _j /L)
The resistance value between SR and SR′ was measured according to In this case, when L is kept constant and samples with different x _j are prepared and the resistance value for each x _j /L is determined,
It became as shown in Figure 5. The resistance value is shown as a relative value with the value when x _j =L being 1. According to this,
It can be seen that when x _j /L is 1.0 or more, the resistance value hardly changes and is not affected by the depth of the low concentration region. On the other hand, when x _j /L<1.0, the resistance value increases and becomes susceptible to the influence of the depth of the low concentration region. This means that between the high concentration region SR−SR′,
That is, SR ₁ - SR ₂ and SR ₂ - SR ₃ in Figures 3 and 4.
This suggests that it is preferable to make the pitch or interval between the holes the same as or smaller than the depth of the P-WELL in order to reduce fluctuations in resistance value. In other words, when x _j /L≧1.0, the depletion layer 6
Since the number of electric lines of force 5 (see FIG. 4) that cut the current decreases rapidly, the effect of the depletion layer on the effective portion of the resistance becomes very small.

6 to 8 show another embodiment.

This example relates to a fully parallel comparison type A/D converter, in which the reference voltage V _REF is divided by a plurality of resistors R in FIG _{. 1} , and the reference voltage ( _4/5 V _REF ~ 1/5V _REF ) is generated. Each comparator outputs an "H" signal when the input signal voltage V _IN is greater than the respective reference voltage.

FIG. 2 shows a pattern of a plurality of resistors R. Each resistor R is connected to each comparator using each high concentration region (surface concentration 10 ¹⁸ atoms/cm ³ ) formed across the low concentration region (surface concentration 10 ¹⁵ atoms/cm ³ ) P-WELL as a terminal. ing. What is important is that between both terminals of each resistor R, high concentration regions SR ₁ , SR ₂ and SR ₃ similar to those shown in FIG. 3 are formed at a constant pitch L ₂ . These SR ₁ to _{SR 3} are shallower than P-WELL and P-
It is formed with a pitch L ₂ below the depth of the WELL and is not electrically connected to any other area.

With this configuration, electric lines of force as shown in Fig. 4 will occur between SR ₁ - _{SR 2} and SR ₂ - _{SR 3} in the intermediate region of the resistance R, and the current path will move near the surface. This eliminates the influence of the depth of the P-WELL (i.e., the depletion layer). In other words, there is a stable resistance between each high concentration region as shown in Figure 8.
R ₀ is formed, which is equivalent to each R being equally configured by a plurality of resistors R ₀ . Therefore, as described above, all the resistors R can be formed with high accuracy according to the designed values, and furthermore, low power consumption and high integration can be achieved. In an A/D conversion device like this example, the absolute accuracy of the resistor R directly affects the accuracy of A/D conversion, especially the nonlinearity error (differential linearity error, linearity error). According to this method, since R ₀ and R can be realized as designed, non-linearity errors caused by resistance can be almost eliminated.

The example described above can be further modified and can be applied to A/D conversion devices in general. For example, Figures 1 and 2
In the figure, point a is separated from V _OUT and used as an input, V _IN is used as an input, and R ₀
(or 2R ₀ , 3R _{0 .} . . ), an output to the switch group 2 can be provided, and the switch group control circuit 3 can also form an arbitrary current path based on an external signal.
In this case, A/D conversion can be performed with input=V _REF and input=V _IN . Note that the pattern and conductivity type of each semiconductor region described above may be changed.

[Brief explanation of drawings]

The drawings show an embodiment of the present invention, in which Fig. 1 is a circuit diagram for adjusting the gain of an operational amplifier, Fig. 2 is a circuit diagram showing its specific configuration, and Fig. 3 is a circuit diagram for adjusting the gain of an operational amplifier. Pattern diagram of the resistor part, 4th
The figure is an enlarged cross-sectional view taken along the line X-X in Figure 3, Figure 5 is a graph showing the resistance change according to the ratio of the depth of the low concentration region to the distance between the high concentration regions in the test sample, and Figure 6 is the other graph. FIG. 7 is a circuit diagram of a fully parallel comparison type A/D converter which is an embodiment of the present invention, FIG. 7 is a pattern diagram of its voltage dividing resistors, and FIG. 8 is a circuit diagram showing each resistor as a small resistor connected in series. . In addition, in the symbols shown in the drawings, 1 is a resistor section, 2 is a switch group, 3 is a switch group control circuit,
5 is a line of electric force, 6 is a depletion layer, SR ₁ to SR ₃ . . . are high concentration regions, and P-WELL is a P ^- type low concentration well.

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit device having a resistor using a first semiconductor region of a second conductivity type formed on one main surface side of a semiconductor substrate of a first conductivity type, the resistor is connected to the first semiconductor substrate. A plurality of second semiconductor regions of a second conductivity type having a higher impurity concentration than the first semiconductor region are formed in the first semiconductor region so as to cross the region and to be shallower than the first semiconductor region. Semiconductor integrated circuit device. 2. The mutual spacing between the plurality of second semiconductor regions is
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed to have a depth equal to or smaller than the depth of the first semiconductor region.