JPH03242938A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03242938A JPH03242938A JP2040004A JP4000490A JPH03242938A JP H03242938 A JPH03242938 A JP H03242938A JP 2040004 A JP2040004 A JP 2040004A JP 4000490 A JP4000490 A JP 4000490A JP H03242938 A JPH03242938 A JP H03242938A
- Authority
- JP
- Japan
- Prior art keywords
- pad
- bump electrode
- metal layer
- shape
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 239000002184 metal Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims description 11
- 239000010410 layer Substances 0.000 abstract description 19
- 230000004888 barrier function Effects 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 8
- 239000011229 interlayer Substances 0.000 abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 5
- 238000004806 packaging method and process Methods 0.000 abstract description 4
- 238000007373 indentation Methods 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910010977 Ti—Pd Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05557—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、バンブ電極とパッド間の接触抵抗が小さく、
かつ密着強度が高い半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention has low contact resistance between bump electrodes and pads.
The present invention also relates to a semiconductor device with high adhesion strength.
従来の技術
半導体装置を高密度で実装する手法の一つとして、フィ
ルムキャリアまたはＴＡＢ （テープ・オートメイテッ
ド・ボンディング）法と呼ばれる技術がある。これは半
導体装置の表面に設けられたパッド（電極）上にＡｕ等
でバンブ電極を形成し、これらのパッドの配置に対応し
て用意されたＣｕ箔製のインナーリード群とを一部ボン
ディングし、さらにインナーリード群の他端をプリント
基板等の電極にボンディングする実装技術である。2. Description of the Related Art One technique for packaging semiconductor devices at high density is a technique called a film carrier or TAB (tape automated bonding) method. This involves forming bump electrodes made of Au or the like on pads (electrodes) provided on the surface of the semiconductor device, and partially bonding them to a group of inner leads made of Cu foil prepared in accordance with the arrangement of these pads. This is a mounting technology in which the other end of the inner lead group is bonded to an electrode on a printed circuit board or the like.
この実装法を実施するための半導体装置のパッド近傍は
第２図に示すように、Ａｅ等の配線金属層の一部で形成
したパッド１１の中央付近を除いてシリコン窒化膜等の
表面保護膜１２で覆われている。またこの時、配線金属
層の一部で形成したパッド１１は、シリコン基板１３の
上の素子分離用のフィールド酸化膜１４とその上に形成
された、表面が平坦な導体層分離用のＰＳＧ （リン・
ケイ酸ガラス〉等からなる層間絶縁膜１５の上に形成さ
れている。As shown in FIG. 2, the vicinity of the pads of the semiconductor device for carrying out this mounting method is covered with a surface protective film such as a silicon nitride film, except for the vicinity of the center of the pad 11 formed of a part of the wiring metal layer such as Ae. It is covered with 12. Further, at this time, the pad 11 formed of a part of the wiring metal layer is connected to the field oxide film 14 for element isolation on the silicon substrate 13 and the PSG ( Rin·
It is formed on an interlayer insulating film 15 made of, for example, silicate glass.
つぎに表面保護膜１２開口部に露出したバッド１１開口
部表面とその周囲の表面保護膜１２を覆って、例えばＮ
ｉ−Ｃｒ−Ａｕ、Ｔｉ−Ｐｄ等の２〜３種の金属薄膜を
積層してバリアメタル層１６が設けられ、その上に少な
くともパッド１１間口部を完全に覆い、さらにそのパ・
ソド開口部の周囲をも、５〜１０μｍの幅で覆うように
Ａｕ等で１０〜２０μｍの高さのバンブ電極１７が形成
されている。このバンブ電極１７はその頂上面において
、たとえばＳｎメツキを施したＣｕ箔で作られたインナ
ーリードと熱圧着によって接合される。Next, the opening surface of the pad 11 exposed at the opening of the surface protective film 12 and the surrounding surface protective film 12 are covered with, for example, N.
A barrier metal layer 16 is provided by laminating two to three metal thin films such as i-Cr-Au and Ti-Pd, and on top of this, at least the frontage of the pad 11 is completely covered, and the
A bump electrode 17 with a height of 10 to 20 μm is formed of Au or the like so as to cover the periphery of the opening with a width of 5 to 10 μm. The bump electrode 17 is joined at its top surface to an inner lead made of, for example, Sn-plated Cu foil by thermocompression bonding.
発明が解決しようとする課題
このような従来の半導体装置では、高密度実装を実現し
ようとすると、表面保護膜１２の開口部面積が狭くなり
、バンブ電極１７とパッド１１間の接触抵抗が大きくな
り、また平坦面上にパッド１１が設けられているため、
インナーリードとの熱圧着時にパッド１１とバリアメタ
ル層１６の界面で剥離が生じやすい。Problems to be Solved by the Invention In such conventional semiconductor devices, when attempting to realize high-density packaging, the opening area of the surface protection film 12 becomes narrower, and the contact resistance between the bump electrode 17 and the pad 11 increases. , and since the pad 11 is provided on a flat surface,
Peeling easily occurs at the interface between the pad 11 and the barrier metal layer 16 during thermocompression bonding with the inner lead.
本発明は上記課題を解決するもので、信頼性の高い高密
度実装が可能な半導体装置の提供を目的としている。The present invention solves the above problems, and aims to provide a semiconductor device that is highly reliable and can be mounted at high density.
課題を解決するための手段
本発明は上記目的を達成するために、配線金属層の一部
で形成されたパッドと、そのパッドの中央付近のみを開
口させて形成された表面保護膜と、そのパッド開口部と
その周辺を覆って形成されたバンブ電極を有する半導体
装置において、パッド開口部およびその下地表面が凹凸
の形状を有するような構造にしている。Means for Solving the Problems In order to achieve the above object, the present invention provides a pad formed of a part of a wiring metal layer, a surface protection film formed with an opening only near the center of the pad, and A semiconductor device having a bump electrode formed to cover a pad opening and its periphery has a structure in which the pad opening and its underlying surface have an uneven shape.
作用
本発明は上記した構成により、表面保護膜の開口部面積
が小さくても、パッドとバリアメタル層とバンブ電極の
それぞれの接触面積が広くなる。Effect of the present invention With the above-described configuration, even if the opening area of the surface protection film is small, the contact area of each of the pad, barrier metal layer, and bump electrode is widened.
その結果、接触抵抗が小さくなり、インナーリードとの
熱圧着の際の上から加わる力に対して機械的強度が著し
く向上する。As a result, the contact resistance is reduced, and the mechanical strength is significantly improved against the force applied from above during thermocompression bonding with the inner lead.
実施例
以下、本発明の一実施例について第１図を参照しながら
説明する。EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIG.
図において、１はＡｅ等の配線金属層の一部からなるパ
ッド、２はシリコン窒化膜等の表面保護膜、３はシリコ
ン基板、４は素子分離用のフィールド酸化膜、５は導体
層分離用のＰＳＧ等からなる層間絶縁膜、６はバリアメ
タル層、７はバンブ電極である。In the figure, 1 is a pad made of a part of a wiring metal layer such as Ae, 2 is a surface protection film such as a silicon nitride film, 3 is a silicon substrate, 4 is a field oxide film for element isolation, and 5 is for conductor layer isolation. 6 is a barrier metal layer, and 7 is a bump electrode.
バンブ電極７を形成する領域において、まずシリコン基
板３上に、写真蝕刻技術、エツチング技術、熱酸化技術
等によりフィールド酸化膜４のパターンを形成する。こ
のフィールド酸化膜４は本来、トランジスタを形成する
領域あるいは基板拡散層とのコンタクトをとる領域を除
いて全面に形成されるものであるが、本実施例ではパッ
ド１開口部分の下の領域において、このフィールド酸化
膜４を選択的に成長させ、凹凸を形成している。In a region where bump electrodes 7 are to be formed, a pattern of field oxide film 4 is first formed on silicon substrate 3 by photolithography, etching, thermal oxidation, or the like. This field oxide film 4 is originally formed on the entire surface except for the region where a transistor is formed or the region where contact is made with the substrate diffusion layer, but in this embodiment, the field oxide film 4 is formed in the region under the opening of the pad 1. This field oxide film 4 is selectively grown to form irregularities.
すなわち、フィールド酸化膜４成長時に通常マスク層と
して用いるシリコン窒化膜を、パッド１開口部分の下の
領域において格子状に残しておき、この状態で、通常の
フィールド酸化膜４の成長を行えば、パッド１開口部分
の下の領域には、図に示すように、フィールド酸化膜４
が複数、互いに距離をおいて成長する。このようにして
、新たなマスク工程、エツチング工程を何ら追加するこ
となく、断面形状として凹凸形状が形成される。つぎに
、ＰＳＧ等の層間絶縁膜５を成長付着する。That is, if the silicon nitride film normally used as a mask layer during the growth of the field oxide film 4 is left in a grid pattern in the area under the opening of the pad 1, and the field oxide film 4 is grown in this state, In the area under the opening of the pad 1, a field oxide film 4 is formed as shown in the figure.
grow apart from each other. In this way, an uneven cross-sectional shape is formed without adding any new mask process or etching process. Next, an interlayer insulating film 5 such as PSG is grown and deposited.
この時、層間絶縁膜５は、下地の形状にしたがって形成
されるのでフィールド酸化膜４と同様に凹凸の形状を示
す。さらに、ＡＱ等の配線金属層よりなるパッド１を気
相成長技術、写真蝕刻技術。At this time, since interlayer insulating film 5 is formed according to the shape of the underlying layer, it exhibits an uneven shape similar to field oxide film 4. Furthermore, pad 1 made of a wiring metal layer such as AQ is formed using vapor phase growth technology and photo-etching technology.
エツチング技術等により形成する。この場合も下地形状
にしたがって表面が凹凸形状を示す。つぎにシリコン窒
化膜等の表面保護膜２を成長付着させ、パッド１の中央
部分を開口させる。つぎに表面保護膜２開口部に露出し
たパッド１開口部とその周囲の表面保護膜２を覆ってＴ
ｉ−Ｐｄ等の金属薄・膜からなる、中央部が凹凸形状の
バリアメタル層６を積層する。その上に少なくともパッ
ド１開口部を完全に覆い、さらにパッド１開口部の周囲
の表面保護膜２とその上のバリアメタル層６を覆うよう
にＡｕ等のバンブ電極７を電気メツキ法等で形成する。Formed by etching technology, etc. In this case as well, the surface exhibits an uneven shape according to the underlying shape. Next, a surface protection film 2 such as a silicon nitride film is grown and deposited, and the center portion of the pad 1 is opened. Next, cover the opening of the pad 1 exposed in the opening of the surface protective film 2 and the surface protective film 2 around it.
A barrier metal layer 6 made of a metal thin film such as i-Pd and having an uneven central portion is laminated. A bump electrode 7 made of Au or the like is formed thereon by electroplating or the like so as to completely cover at least the opening of the pad 1 and further cover the surface protection film 2 around the opening of the pad 1 and the barrier metal layer 6 thereon. do.
なお、この実施例では、フィールド酸化膜４にて凹凸の
パターンを形成したが、層間絶縁膜５やシリコン基板３
で凹凸のパターンを形成しても何らさしつかえない。In this embodiment, the uneven pattern is formed in the field oxide film 4, but the interlayer insulating film 5 and the silicon substrate 3
There is no problem in forming an uneven pattern.
また用途によってはバリアメタル層６を用いない場合も
あり、フィールド酸化膜４２層間絶縁膜５の一方または
両方とも使用しない場合もある。Furthermore, depending on the application, the barrier metal layer 6 may not be used, and one or both of the field oxide film 42 and the interlayer insulating film 5 may not be used.
両方とも使用しない場合は、シリコン基板３にパッド１
を直接つけることになる。いずれの場合もパッド１開口
部とその下地になる表面が凹凸形状であればよい。また
シリコン基板１は他の半導体基板にも適用できる。If both are not used, place pad 1 on silicon substrate 3.
will be attached directly. In either case, it is sufficient that the opening of the pad 1 and the underlying surface thereof have an uneven shape. Furthermore, the silicon substrate 1 can also be applied to other semiconductor substrates.
発明の効果
以上の実施例から明らかなように、本発明によれば、バ
ンブ電極を有する半導体装置において、バンブ電極に接
触するパッドおよびその下地表面を凹凸形状にすること
により、バンブ電極とパッドの接触面積を広くして接触
抵抗を下げることができ、また接触部分が凹凸形状であ
るため機械的強度も向上した信頼性の高い、高密度実装
が可能な半導体装置が実現できる。Effects of the Invention As is clear from the above embodiments, according to the present invention, in a semiconductor device having a bump electrode, the bump electrode and the pad are made to have an uneven shape by making the pad that contacts the bump electrode and the underlying surface of the bump electrode uneven. The contact resistance can be lowered by increasing the contact area, and since the contact portion has an uneven shape, it is possible to realize a highly reliable semiconductor device that has improved mechanical strength and can be mounted at high density.
第１図は本発明の一実施例の半導体装置の要部断面図、
第２図は従来の半導体装置の要部断面図である。
１・・・・・・パッド、２・・・・・・表面保護膜、３
・・・・・・シリコン基板（半導体基板）、７・・・・
・・バンブ電極。FIG. 1 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a sectional view of a main part of a conventional semiconductor device. 1...Pad, 2...Surface protective film, 3
...Silicon substrate (semiconductor substrate), 7...
...bum electrode.
Claims (1)
パッドと、そのパッドの中央部を開口させて形成された
表面保護膜と、前記パッド開口部とその周辺を覆って形
成されたバンプ電極構造を有する半導体装置において、
前記パッド開口部およびその下地表面が凹凸形状を有す
ることを特徴とする半導体装置。A pad made of a part of a wiring metal layer formed on a semiconductor substrate, a surface protection film formed with an opening in the center of the pad, and a bump formed to cover the pad opening and its periphery. In a semiconductor device having an electrode structure,
A semiconductor device characterized in that the pad opening and its underlying surface have an uneven shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2040004A JPH03242938A (en) | 1990-02-21 | 1990-02-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2040004A JPH03242938A (en) | 1990-02-21 | 1990-02-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03242938A true JPH03242938A (en) | 1991-10-29 |
Family
ID=12568769
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2040004A Pending JPH03242938A (en) | 1990-02-21 | 1990-02-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03242938A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE40819E1 (en) | 1995-12-21 | 2009-07-07 | Micron Technology, Inc. | Semiconductor device with improved bond pads |
| US7859122B2 (en) * | 2008-04-14 | 2010-12-28 | International Business Machines Corporation | Final via structures for bond pad-solder ball interconnections |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5354469A (en) * | 1976-10-28 | 1978-05-17 | Seiko Epson Corp | Semiconductor integrated circuit |
| JPH02180020A (en) * | 1989-01-04 | 1990-07-12 | Nec Corp | Integrated circuit device |
-
1990
- 1990-02-21 JP JP2040004A patent/JPH03242938A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5354469A (en) * | 1976-10-28 | 1978-05-17 | Seiko Epson Corp | Semiconductor integrated circuit |
| JPH02180020A (en) * | 1989-01-04 | 1990-07-12 | Nec Corp | Integrated circuit device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE40819E1 (en) | 1995-12-21 | 2009-07-07 | Micron Technology, Inc. | Semiconductor device with improved bond pads |
| US7859122B2 (en) * | 2008-04-14 | 2010-12-28 | International Business Machines Corporation | Final via structures for bond pad-solder ball interconnections |
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