JPH0324827B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a shading correction device for correcting shading characteristics of a photoelectric conversion element such as a CCD.

A lamp illuminates the surface of the document to be recorded, and the reflected light is guided to a photoelectric conversion element such as a solid-state image sensor or photodiode array through a reflecting mirror or lens.
Recording devices that obtain reproduced images based on the output signals of the photoelectric conversion elements are already widely used.

In this type of recording device, even when reading a document surface with uniform reflection density, the output waveform of the photoelectric conversion element does not become flat. A shading phenomenon, such as a decrease in the output for some pixels, is observed. The causes of this include:

(b) Light attenuation effect by the lens of the optical system The amount of light passing through the lens of the optical system is cosine 4
According to a multiplicative law, the amount of light decreases at the periphery; for example, when the half angle of view is 20 degrees, the amount of light at the periphery is 78% of that at the center.

(b) Non-uniform sensitivity of photoelectric conversion elements Photoelectric conversion elements such as solid-state image sensors such as CCDs and diode arrays may have non-uniform sensitivity due to manufacturing reasons.

(c) Illuminance unevenness and illuminance changes of the irradiation lamp For example, a fluorescent lamp is used as the document irradiation lamp, but the length of the lamp is finite and due to the light emitting mechanism, the luminance is lower at both ends than at the center, so the illuminance is low. Furthermore, as the fluorescent lamp is used, both ends of the lamp turn black, and the illuminance distribution changes depending on how it is installed.

Conventionally, various correction measures have been taken to correct this shading. For example, there is a device that guides reflected light from a uniform reflection density surface to a photoelectric conversion element, A/D converts the output signal, stores it in a storage element, and reads out the stored contents when reading an original to perform shading correction. The accuracy of this correction is quite good, but
There is a problem in that the time that can be spent on the conversion operation of the A/D converter becomes shorter as the suspension driving frequency of the photoelectric conversion element becomes higher, making it impossible to cope with high-speed reading. Another problem is that as the number of pixels of the photoelectric conversion element increases, the capacity of the storage element increases.

Therefore, in order to solve these problems, the present inventors proposed Japanese Patent Application No. 56-124791 (Japanese Patent Application No. 58-12479
No. 27466) (shading correction device), during photoelectric conversion on a uniform reflection density surface, the conversion output of a specific pixel is sampled to obtain the shading correction coefficient of the sampled pixel. The correction coefficients are sequentially determined and applied to the original image signal itself.
Alternatively, high-speed reading is possible by performing calculations on the dither threshold value for binarizing the original image signal by improving halftone reproducibility using the dither method, and obtaining an output after shading correction. In this way, in the method of performing sampling to obtain a correction coefficient and perform correction, if there is an abnormal pixel (for example, Fig. 1 is an example of a pixel with extremely low output) among the pixels of the photoelectric conversion element, , the pixel was not corrected correctly, and depending on the comparison voltage for binarization, a problem occurred in that a black line appeared in the recorded image. In other words, for the shading waveform a in FIG. 1, which partially protrudes downward due to an abnormal pixel, the shading correction coefficient (based on the interpolation method, curve b shown by a broken line in the same figure) is different from the ideal correction coefficient (the curve b shown by the broken line in the figure). A problem has arisen in that the curve c) in the figure differs greatly in abnormal pixels.

As a countermeasure to this problem, a method may be considered in which the shading waveform is corrected by A/D conversion for all pixels, but as already mentioned, this method cannot cope with high-speed reading from the viewpoint of processing speed.
Another method is to interpolate and replace an abnormal pixel with previous and subsequent pixel signals, but this method has the disadvantage that the circuit is complicated and the processing time is long.

The present invention has been made in view of the above points, and
Prior to reading the original, first and second scans are performed on the reflective surface, and the first and second scans on the reflective surface are performed.
The first correction coefficient calculation means calculates a shading correction coefficient regarding the sampling pixel during the second scan, and the output of the photoelectric conversion element obtained during the second scan of the reflective surface is used to calculate the second correction coefficient. The control means causes the correction means to correct based on the shading correction coefficient obtained by the means, and the control means compares the corrected signal obtained from the correction means under the control of the control means with a preset reference voltage. an abnormal pixel detection means for detecting the position of a pixel; a third correction coefficient calculation means for calculating a shading correction coefficient for the abnormal pixel; and a second correction coefficient calculation means for storing the shading correction coefficient calculated by the third correction coefficient calculation means. a storage means, and when reading a document, selects a shading correction coefficient stored in the storage means only for the abnormal pixel, and selects a shading correction coefficient calculated by the second correction coefficient calculation means for other pixels; The present invention provides a shading correction device that can perform a high-speed correction operation even when using a photoelectric conversion element having an abnormal pixel by providing a switching means for applying the correction to the correction means.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is an explanatory diagram showing the main parts of a document reading device with a movable document table. This device irradiates a document 2 placed on a document table 1 with a lamp 3, and makes the reflected light enter a photoelectric conversion element 6 via a reflecting mirror 4 and an imaging lens 5 to obtain an image signal. A white reflective surface 7 is provided in a non-image area in front of the document table 1 . Incidentally, the sub-scanning is performed by moving the document table 1 in the direction of the arrow.

FIG. 3 is a block diagram showing an embodiment of the shading correction device of the present invention which receives the output of the reading device as an input. In the figure, 8 is a photoelectric conversion element 6
A first control circuit 9 outputs a drive clock and a start/stop signal for photoelectric conversion, and 9 outputs the output of the photoelectric conversion element 6 when the white reflective surface 7 is scanned based on the drive clock output from the first control circuit 8. This is a first timing circuit that sets the timing for sampling. 10 is a first timing circuit 9 or a fourth timing circuit 2 to be described later.
11 is a D/A converter that converts digital input into analog output; 12 is sample and hold circuit 1;
0 output image signal Vx and the output of the D/A converter 11
A calculation processing circuit that calculates Vy and 13 is a reference voltage
This is a comparator that compares Vr or Vr' with the output Vo of the arithmetic processing circuit 12. Further, 14 starts operating with the output of the first timing circuit 9 or a fourth timing circuit 20 (to be described later), and depending on the output of the comparator 13, each bit from MSB to LSB of the D/A converter 11 is activated. 15 is a second control circuit for setting the
D/A converter 1 set by control circuit 14 of
Digital inputs to 1 are written one after another.
A memory element such as RAM, 16 is this memory element 15
A second timing circuit 17 outputs a timing signal for writing to the storage element 15, and a third timing circuit 17 outputs a timing signal for reading from the storage element 15. 18 is an interpolation circuit that calculates the shading correction coefficient of a non-sampled pixel by an interpolation method from the shading correction coefficient of the sampling pixel read from the storage element 15; 19 is the timing of calculating and sending out the shading correction coefficient in the interpolation circuit 18; This is a correction timing circuit that sets the Reference numeral 20 denotes a sample and hold circuit 10 for holding signals of abnormal pixels for longer than the processing time.
21 is a counter that counts the drive clock from the first control circuit 8; 22 is a latch that receives the output signal of the comparator 13 and stores the value of the counter 21; and 23 is a A comparator that determines whether the value of the counter 21 and the value of the latch 22 are equal; 24 is a storage element that stores the shading correction coefficient in the abnormal pixel; 25
26 is a fifth timing circuit that outputs a timing signal when writing data into the memory element 24;
This is a sixth timing circuit that outputs a timing signal when reading No. 4. Further, S ₁ to S ₁₀ are switches switched by the first control circuit 8.

Next, the operation of the shading correction device having the above configuration will be explained.

First, the storage operation of the shading correction coefficient will be explained. At this time, switches S ₁ to S ₁₀ are switched to contact a. In the first timing circuit 9, the fourth timing signal outputted from the first control circuit 8 is
Based on the drive clock for the photoelectric conversion element 6 shown in FIG. 1A and the photoelectric conversion start/stop signal shown in FIG. In FIG. 4B, a section P is a storage period for the shading correction coefficient, and a section Q is a period for abnormal pixel detection and document reading. The sample and hold circuit 10 samples the shading waveform output from the photoelectric conversion element 6 at the L level of the sample and hold signal, holds it at the H level, and outputs it to the arithmetic processing circuit 12 . In synchronization with this sample and hold signal, the second control circuit 14
also starts working. Then, first, D/A converter 1
Turn on the MSB of 1. As a result, a 1/2 FS (full scale) signal Vy is output from the D/A converter 11, and this signal Vy and the first sample value of the shading waveform held in the sample and hold circuit 10 are expressed as Vx=V ₁ ( The calculation V ₀ =V ₁ ·Vy (see FIG. 1) is performed in the calculation processing circuit 12. This output V ₀ is compared with the reference voltage Vr in the comparator 13, and when Vr>V ₀ , the H level is
When Vr<V ₀ , an L level is output from the comparator 13. The control circuit 14 is configured so that the output of the comparator 13 is H.
When it is at level, the MSB is left as is and the process proceeds to the lower bits, and conversely, when it is at the L level, the MSB is turned off and the process proceeds to the lower bits. Same operation as below
The second control circuit 14 at this time
The setting digital output is written into the storage element 15.

This operation is performed in synchronization with the internal clock of the second control circuit 14, and an example of the timing chart is shown in FIG. Here, the resolution of the D/A converter 11 is 8 bits. Note that the start signal is generated from the sample and hold signal.

When the settings from MSB to LSB are completed, the second
A conversion completion signal is output from the control circuit 14 to the second timing circuit 16. This causes the second timing circuit 16 to write the setting digital output of the second control circuit 14 into the storage element 15. The above operation is repeated by the number of samples (m times from Vx=V ₁ to Vm) based on the sample-and-hold signal (see FIG. 1).

By the way, the digital setting in the above operation is made to satisfy Vr=V ₀ , that is, Vx·Vy=Vr=constant. Therefore, Vy is the shedding coefficient itself and forms the curve b in FIG. Therefore, the shading correction coefficients for all sampling pixels are written in the storage element 15.

When the storage of the shading correction coefficient for the sampling pixel is completed, the switches S ₁ , S ₂ ,
S ₃ , S ₅ , S ₉ and S ₁₀ are switched to contact b to detect abnormal pixels. This detection is performed while the interpolation circuit 18 obtains shading correction coefficients for non-sampled pixels. Specifically, the data of the shading correction coefficients are read out from the storage element 15 two at a time, and the interpolation circuit 18 performs arithmetic processing. 6th
Since the detailed circuit example of the interpolation circuit 18 is shown in the figure,
Interpolation processing in the interpolation circuit 18 will be explained based on this figure. First, the first data V ₀₁ of the two correction coefficient data is held in the latch 31, and the second data V ₀₂ is held in the latch 32 (V ₀₁ ,
For V ₀₂ , see Figures 1 and 7). The calculation unit 33 calculates the difference between these data V ₀₁ and V ₀₂ (V ₀₁ −
V ₀₂ ) and input it to the calculation circuit 24
is based on the number n of non-sampled pixels between sampling pixels, and the change between pixels △V ₁ = (V ₀₁ −
Find V ₀₂ )/(n+1). These series of calculations are performed between times _t1 and _t2 . Next, at time _t2 when reading of the reflective surface 7 for abnormal pixel detection starts, the switch _S20 is switched to contact a, data _V01 is held in the latch 37, and this is transferred to the D/A
It is output to the converter 11. At the next timing,
At the same time as switch S ₂₀ is switched to contact b, △V ₁ is held in latch 35, and from calculation section 36
V ₀₁ −△V ₁ is output. The latch 37 holds this and outputs it to the D/A converter 11. Latch 37
As a result of updating the memory contents, in the calculation unit 36,
New operation (V ₀₁ −△V ₁ ) −△V ₁ =V ₀₁ −2△V ₁
will be done. Latch 37 holds this again,
Output to D/A converter 11. Furthermore, next, the operation (V ₀₁ −2△V ₁ )−△V ₁ =V ₀₁ −3△V ₁
is performed by the arithmetic unit 36 and output to the D/A converter 11. Thereafter, calculations are similarly repeated in synchronization with the drive clock of the second control circuit 8, and the calculation results are output to the D/A converter 11. The arithmetic processing based on the above interpolation method is carried out by the interpolation timing circuit 1
This is done by the timing signal from 9.

Incidentally, when △V ₁ is held in the latch 35,
Two pieces of correction coefficient data necessary for the next interpolation calculation are read from the storage element 15, and the change amount ΔV ₂ in the next interpolation process is determined by the same calculation as in the case of ΔV ₁ . The reason why the arithmetic processing of ΔV ₁ and the arithmetic processing of ΔV ₂ are performed in parallel in this way is to shorten the processing time by the interpolation circuit 18. Therefore, the interpolation calculation using the newly calculated change amount is also quickly performed.

By the way, when _{performing the above} interpolation operation, as _shown in _{FIG .} change. Therefore,
When Vk ₁ <Vk ₂ , the arithmetic unit 33 is set to Vk ₂ −Vk ₁
Then, the arithmetic unit 36 is switched to Vk ₁ +ΔV at the interpolation circuit timing 19.

Through the above operation, the shading correction coefficient output from the interpolation circuit 18 is transferred to the D/A converter 11.
The sample and hold circuit 10
The reading signal Vx of the reflective surface 7 outputted from the arithmetic processing circuit 12 is calculated, and the calculation result is outputted as a signal _V0 . This corrected signal
V ₀ is compared with the reference voltage Vr' obtained from the tolerance of the shedding correction factor, and when Vr'> V ₀ , the comparator 13 outputs an H level, and the value of the counter 21 at this time, that is, The position of the abnormal pixel is held by the latch 22. At the same time, the timing circuit 20 outputs a hold signal to cause the sample and hold circuit 10 to hold the signal of the abnormal pixel. At the same time, the switches S ₁ , S ₅ , and S ₉ are switched to the a contact, the control circuit 14 starts operating, and the shading correction coefficient for the abnormal pixel is determined.
The data is written into the memory circuit 24 according to the timing signal from the timing circuit 25. Then the switch
S ₁ , S ₅ , and S ₉ are switched to b contacts, and abnormal pixel detection continues again.

When the abnormal pixel detection and correction coefficient storage operations are completed, the switches S ₁ , S ₄ , S ₆ , and S ₇ are switched to the b contacts, and the switch S ₁₀ is switched to the a contact, and the image signal correction operation is performed. This correction operation is similar to the case of abnormal pixel detection described above. That is, the shading correction coefficient output from the interpolation circuit 18 is
The original reading signal Vx is analog-converted by the D/A converter 11 and output from the sample hold circuit 10, and is calculated by the arithmetic processing circuit 12.
The calculation result is output as a corrected signal _V0 .
However, during this operation, if the comparator 23 detects that the value of the counter 21 is equal to the value of the latch 22 that holds the position of the abnormal pixel, the switch _S8 switches to b.
The timing circuit 26 reads out the correction coefficient corresponding to the abnormal pixel from the memory circuit 24 and outputs it to the D/A converter 11.
Correction of abnormal pixels is performed. Then, the normal correction operation is resumed.

By performing the above-described shading correction for each scan, shading can be completely corrected.

In the above embodiment, a case has been described in which a multiplication circuit is used as the arithmetic processing circuit 12 and the image signal is directly corrected. However, for example, when expressing halftones by the dither method, the dither threshold value may be corrected good. The case of correcting the dither threshold will be described below. Taking the 4×4 dither matrix shown in FIG. 8 (0, 8, 2, 10, ... are dither threshold values) as an example, the values before correction of the dither threshold values are shown only for the first row of the dither matrix. The result will be as shown in Figure 9 (a) c. By the way, the output (image signal) of the photoelectric conversion element when imaging a reflective surface with uniform density should be constant as shown by the dashed-dotted line a in Figure 9A, but due to shading, it actually is as shown by the two-dot chain line b. Therefore, if this is binarized using the threshold value before correction, the result will be as shown in the upper column of FIG. 9B, which will be affected by shading. Here, the black circles in FIG. 9B are signals to be printed by binarization, and the white circles are signals not to be printed. In this case, if the dither threshold value in the first row of FIG. 8 is corrected according to the shading and changed from the solid line c to the broken line d, the binarized output will be as shown in the lower column of FIG. 9, A result similar to that obtained by correcting the output b of the photoelectric conversion element shown in FIG. 9A to a can be obtained.

This dither threshold value may be corrected based on the following equation.

Dither threshold value/shading correction coefficient = dither threshold value after correction To execute this, the arithmetic processing circuit 12 shown in FIG. 3 needs to be configured as shown in FIG. 10, for example. In Fig. 10, Vx is an image signal,
It goes without saying that Vy is a shading correction coefficient. This arithmetic processing circuit 12 includes a storage section 1
A group of dither threshold values constituting a dither matrix is stored in advance in 21, and these are sequentially read out and
The analog output Vd is applied to the A converter 122, and its analog output Vd is input to the arithmetic circuit 123, divided by the shading correction coefficient Vy, and the arithmetic result Vd/Vy is input to the non-inverting input terminal of the comparator 124, and the image signal Vx is input to the inverting input terminal of the comparator 124 to obtain a binary signal. Note that since the values of Vx and Vy are required when calculating the shading correction coefficient, the multiplication circuit 125 is configured to output analog values Vx and Vy. That is, when calculating the shading correction coefficient, set the switch SW to a.
The configuration is such that the switch SW is connected to contact b during dither processing.

Incidentally, without using the D/A converter 11 in FIG. 3, the input thereof is directly given to the division circuit 123 in FIG.
The dither threshold value in the storage unit 121 is directly divided by the circuit 12.
3, and if the image signal Vx is modified such as A/D converted and used, it becomes possible to correct the dither threshold value by digital calculation. In this way, the shading correction device can be manufactured easily and inexpensively.

In the above embodiment, the sampling intervals when performing interpolation are set at equal intervals, but the sampling intervals may be fine at both ends of the shading waveform and coarse at the center, or may be changed as appropriate depending on the shading waveform.

Further, although the case where there is one abnormal pixel has been described, when there is a plurality of abnormal pixels, a plurality of latches 22 may be used to obtain the correction coefficient for the abnormal pixel.

Furthermore, if the sampling pixel and the abnormal pixel match, the sampling pixel may be shifted by one pixel as a whole.

Furthermore, in the example, the uniform reflective surface is white,
We have explained an example in which this is provided in a non-image area, but
The present invention is not limited to this.

As described above, according to the present invention, it is possible to realize a shading correction device that can perform a high-speed correction operation even when a photoelectric conversion element having an abnormal pixel is used.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram showing a shading waveform and a shading correction coefficient, Fig. 2 is an explanatory diagram of main parts showing an example of a document reading device with a movable document table, and Fig. 3 is a block diagram showing an embodiment of the present invention. , FIG. 4 is a timing chart for explaining the shading coefficient storage operation, FIG. 5 is a timing chart for setting each bit of the D/A converter, and FIG. 6 is a block diagram showing an example of the detailed configuration of the interpolation circuit. , Fig. 7 is an explanatory diagram showing the calculation of the shading correction coefficient by the interpolation method, Fig. 8 is an explanatory diagram showing an example of a dither matrix, and Fig. 9 is an explanatory diagram showing an example of the dither matrix shown in Fig. 8. FIG. 10 is a configuration diagram of an arithmetic processing circuit in another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Original table, 2...Original, 3...Lamp, 4...Reflector, 5...Imaging lens, 6...Photoelectric conversion element, 8,1
4...Control circuit, 9, 16, 17, 20, 25, 2
6...timing circuit, 10...sample hold circuit, 11...D/A converter, 12...arithmetic processing circuit,
13, 23... Comparator, 15, 24... Storage element, 1
8... Interpolation circuit, 19... Interpolation timing circuit, 21
...Counter, 22...Latch.

Claims (1)

[Claims] 1. A reflecting surface having a uniform reflection density, an optical system that guides reflected light from the reflecting surface to a photoelectric conversion element via an imaging lens, and receiving reflected light from the reflecting surface. a sample and hold circuit that samples the output of the photoelectric conversion element at a predetermined timing; and a first correction coefficient calculation means that calculates a shading correction coefficient for the sampled pixel from the sample value obtained by the sample and hold circuit;
a first storage means for storing the shading correction coefficient obtained by the first correction coefficient calculation means; a shading correction coefficient for the sampling pixel is read from the first storage means when reading a document;
a second correction coefficient calculating means for calculating a shading correction coefficient for all used pixels using an interpolation method;
In the shading correction device, the shading correction device includes a correction means for correcting the output of the photoelectric conversion element based on a shading correction coefficient, and prior to reading the document, a first correction is performed on the reflective surface.
and performing a second scan, causing the first correction coefficient calculating means to obtain a shading correction coefficient regarding the sampling pixel in the first scan of the reflective surface, and obtaining a shading correction coefficient regarding the sampling pixel in the second scan of the reflective surface. The output of the photoelectric conversion element is
A control means that causes the correction means to correct based on the shading correction coefficient obtained by the correction coefficient calculation means of the control means, and a comparison between the corrected signal obtained from the correction means under the control of the control means and a preset reference voltage. abnormal pixel detection means for detecting the position of the abnormal pixel by detecting the position of the abnormal pixel; third correction coefficient calculation means for calculating a shading correction coefficient for the abnormal pixel; and storing the shading correction coefficient calculated by the third correction coefficient calculation means. a second storage means that selects the shading correction coefficient stored in the storage means only for the abnormal pixel when reading a document, and selects the shading correction coefficient calculated by the second correction coefficient calculation means for other pixels; A shading correction device comprising: switching means for selecting and applying to the correction means.