JPH03247045A - Serial communication equipment - Google Patents

Abstract

PURPOSE:To make the transfer comparatively high in speed and to prevent an external interference data from being processed in mistake into a data by providing a means inhibiting data reception during transmission and a means inhibiting new data reception for a prescribed period after the reception data is once received. CONSTITUTION:The equipment is provided with a 1st reception inhibit means inhibiting data reception during data transmission and a 2nd reception inhibit means inhibiting start of new data reception for a prescribed period after the reception data is once received. Moreover, a transmission start means permitting data reception after lapse of a prescribed period in the case of employment at a master side and starting the succeeding data transmission when no new data is received for the prescribed period is provided further to the equipment. Then the collision in 2-way transfer is prevented to avoid mis-transmission and high speed transmission is attained and an external disturbance data is prevented from being processed in mistake into a data.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a serial communication device that transmits information between a group of units dispersed inside and outside the device and a main control unit that controls them;
In particular, it relates to a wireless optical communication device using light (hereinafter abbreviated as a wireless optical communication device).

[Prior Art] Conventionally, for example, copying machines, FAX machines, laser beam printers (hereinafter abbreviated as LBP), etc., use motors.

It consists of an output control section consisting of actuators such as fans and solenoids, and an input control section consisting of switches and sensors. In this case, the input/output control section is mainly C
Each is controlled via 110 ports of PU. These objects to be controlled by human output are distributed within the device and connected by wire harnesses.

Also, are these input/output control objects connected to the main control unit independently (hereinafter abbreviated as parallel connection)?
Alternatively, data is transferred serially from the main control section using serial communication, and after "serial-to-parallel conversion" is performed in each unit, it is independently connected to each target object. However, in both cases, connections were made using electric wires, and information was not transmitted wirelessly using light.

On the other hand, in home appliances, information is transmitted wirelessly using so-called remote controls using light, but only a unidirectional method (transmission in one direction from a transmitting-only device to a receiving-only device) is used. ).

[Problems to be solved by the invention] However, as devices become more multi-functional, the number of objects to be input/output controlled increases, and the number of control lines increases for parallel connection. The disadvantage is that the efficiency of the method also decreases. Furthermore, for example, UAR
Even with the method of reducing the number of control lines by performing serial transfer from the main control unit using serial communication such as T, it may cause malfunctions due to erroneous transfer due to noise generated within the device, or it may be difficult to increase the speed of serial transfer. Along with this, there are various drawbacks such as the control line causing an electric field to be emitted as radiated noise.

On the other hand, wireless information transmission using light, such as in so-called remote controls for home appliances, is a unidirectional method and the transmission speed is close to the second, so for example, copying machines, fax machines,
It cannot be used as is because it cannot keep up with the transmission speed of input/output signals such as BP, and it cannot transmit information in both directions. Furthermore, if optical transmission is performed at a relatively high speed and in both directions, problems such as collision of each light beam or erroneous transmission due to disturbance light may occur, and the presence or absence of the destination communication device may be determined at the main control unit level of the device. It has the disadvantage that it cannot be determined. Furthermore, there is also the disadvantage that adjustments and checks during assembly of the equipment are complicated and inefficient.

The present invention provides a serial communication device that eliminates the above-mentioned conventional drawbacks, prevents collisions in bidirectional transfer, eliminates erroneous transmission, and enables high-speed transmission.

Particularly in optical communication, problems such as collision of respective lights and mistransmission due to disturbance light that occur when transferring data in both directions are solved, and disturbance data is prevented from being converted into data.

[Means for Solving the Problem] In order to solve this problem, the serial communication device of the present invention combines a group of units that physically and functionally organize distributed output signals and human input signals into a plurality of blocks. A device that has a main control section that collectively controls a group of units, and a serial communication device that serially transmits information between the main control section and the group of units, and a serial communication device that prohibits data reception during data transmission. and a second reception prohibition means that prohibits the start of new data reception for a predetermined period after receiving the first received data.

Here, when used on the master side, the apparatus further includes a transmission start means for permitting data reception after the predetermined period has elapsed, and for starting the next data transmission if no new data has been received for a predetermined period.

The device further includes a photoelectric conversion means for converting an electric signal to an optical signal, and serial transmission of information is performed by optical communication using light.

[Function] In such a configuration, by controlling whether or not reception is possible, transfer is made relatively high speed, problems such as miscommunication such as collisions in bidirectional transfer are solved, and disturbance data is prevented from being converted into data. Make it.

Margin below - [Example] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Serial Communication Device of this Embodiment> FIG. 1 is a block diagram of a serial communication device of this embodiment.

Reference numeral 1 designates a frequency divider circuit that divides and outputs the system clock that drives this system, and 2 a multistage frequency divider circuit.

Reference numeral 3 denotes a timing generation circuit for outputting a desired timing signal based on the clock count inputted from the multi-stage frequency divider circuit 2. 4 is a synchronization circuit for synchronizing with the received serial data, and 5 is a frequency division control circuit for restarting the multistage frequency divider circuit 2 at the timing obtained by the synchronization circuit 4. 6 is a demodulation/conversion circuit for demodulating the received modulated data into binary data, and 7 is an error detection circuit for detecting errors due to conversion or noise during demodulation in the demodulation/conversion circuit 6.

8 is an ID data input circuit for inputting an ID number indicating the attribute of the present serial communication device, and 9 is a data input circuit for inputting transmission data of the present serial communication device. 10 is a data output circuit that outputs the received data of this serial communication device.

Reference numerals 11 and 12 denote a positive logic ID data output circuit and a negative logic ID data output circuit that divide the ID data obtained by the ID data input circuit 8 into positive logic data and negative logic data and convert them into data for transmission. Reference numerals 13 and 14 denote a positive logic data output circuit and a negative logic data output circuit that divide the transmission data obtained by the data input circuit 9 into positive logic data and negative logic data and convert them into data for transmission. Reference numeral 15 denotes a data encode circuit that creates binary level data of the transmission data to be transmitted by the serial communication device and outputs it to the 8-bit shift register 16 in accordance with the transmission timing.

16 is an 8-bit shift register for inputting and shift-latching the binary level reception data demodulated by the synchronization circuit 4 and the demodulation conversion circuit 6, and for shifting and outputting the transmission data output from the data decoding circuit 15. be. 17, 18 and 19 are shift data latch circuits that latch the binary level data shifted and inputted by the 8-bit shift register 16 at the timing generated from the timing generation circuit 3. In this embodiment, 3 shift data latch circuits are used for receiving one frame. There are three circuits to perform the turning operation. Reference numeral 20 denotes a comparison and selection circuit which compares the data latched by the shift day clutch circuits 17, 18 and 19 under predetermined conditions and selects necessary data, and determines whether the received data is true or false.

21 is a modulation conversion circuit that adds modulation under predetermined conditions to the binary level transmission data output from the 8-bit shift register 16, and performs inverse conversion of the demodulation conversion circuit 6, and this data is serially This becomes the transmission data. 22
is an AND gate, which controls whether or not to instruct a latch signal for inputting data to the data output circuit 10, depending on the comparison result of the comparison and selection circuit 20.

In this embodiment, the circuit configuration is constructed in 8-bit units for ease of explanation, but it is not particularly necessary to have an 8-bit configuration and may be 16 bits, 32 bits, etc. without any particular limitation.

The operation of the serial communication device shown in FIG. 1 will be explained below. The system clock for this system enters the frequency divider circuit 1, adjusts the clock duty ratio to 50%, and is used as an operating clock for the synchronization circuit 4 and the frequency division control circuit 5. On the other hand, it is also input to the multi-stage frequency divider circuit 2, and in this embodiment, the frequency is divided by "2+1" and each stage is outputted to the timing generation circuit 3, which generates an arbitrary timing to be described later. still,
The internal structures of the circuits shown in 1, 2.3, and 4.5 above are not particularly featured in the present invention, and therefore will not be described in detail. Therefore, it goes without saying that the circuit is not particularly limited, and any circuit that fulfills the purpose described in this specification may be used.

Next, in Figure 0, which describes the input and output of data in this serial communication device, the serial data input to the synchronization circuit 4 is received data input, and is outputted from the data output circuit 10 as received data output. In addition, each input circuit 8
The ID data input and transmission data input input to 9 and 9 become transmission data as serial data output from the modulation conversion circuit 21. The details will be described later, but I
D data input is used when determining the authenticity of received data input.

FIG. 2 is a diagram showing the modulation and demodulation circuit section of FIG. 1 in detail.

First, the operation of the modulation conversion circuit 21 will be explained. Second
In the figure, data (2) output from the shift out terminal of the 8-bit shift register 16 is input to the EXOR 212 in the modulation conversion circuit 21. On the other hand, multistage frequency divider circuit 2
The clock φ32 divided by l/32 is sent to the inverting gate 21.
The signal (2) whose phase has been adjusted by inverting it by
is input to the other side. And EXOR circuit 212
As a result, a serial data signal for transmission (■) is output.

The method of modulation achieved with the above circuit will now be described in detail.

The shift-out data (2) are output one after another using the φ32 clock, and are then EXORed with the inverted signal of the φ32 clock. In other words, if "1" is shifted out, EXO
"10" is output by R, and "01" is output by EXOR if "O" is shifted out. Therefore, under this modulation condition, if “1011
If the transmission data is 000100..., then "to
0110 to 010101100101...". Therefore, the demodulation method on the receiving side is to invert the transmitted data and convert the second data to 1.
All you have to do is latch the data in skips (odd numbers). still,
Regarding the modulation method and demodulation method, for example, even if you latch the next data (even number) from the first transmission data and demodulate it, the result will be the same.The specific method is particularly limited. It would be better if it could be digitally modulated and demodulated.

When the serial data signal for transmission (2) is output from the EXOR circuit 212, it passes through the AND gate 213 and is serially output as transmission data.

However, the presence or absence of output of the transmission data is controlled by the signals indicated by [phase] and ■ in the figure. This signal (2) becomes "βow" when an error is determined based on the comparison result of the comparison selection circuit 20 and the result of the error detection circuit 7, and the output of the transmission data is cut off (details will be described later). teeth,
8-bit shift register 1 by timing generation circuit 3
It becomes "high" only during the period when the signal 6 is shifted out, and output of transmission data is permitted.

A timing chart at this time is shown in FIG.

In FIG. 3, the signal ■ is shown in the state without an error, and the serial data output and the signal ■ are shown.

■, /φ3□, ■, [phase] are the timings at the locations indicated by the symbols in FIG. 2, respectively.

Next, the operations of the demodulation conversion circuit 6 and the modulation error detection circuit 7 will be explained.

In FIG. 2, received data 4 synchronized and inputted by a synchronization circuit 4 is transferred to a D flip-flop 61.
(Hereinafter, flip-flop will be abbreviated as F/F). Note that the multi-stage frequency divider circuit 2 is reset by the frequency divider control circuit 5 synchronized by the synchronization circuit 4, and the initialized count is started. The D-F/F61 is triggered by the clock φ16 whose frequency is divided to 1/16 by the multi-stage frequency divider circuit 2, and the output ■ is the output from the EXOR circuit 12 and the D-F/F71.
is input. D-F/F71 is D-F/F6
It is triggered by the same clock as 1, and the output 2 is input to the other side of the EXOR circuit 72. The D-F/F 61 is controlled by a set terminal, while the D-F/F 71 is controlled by a reset terminal by a signal (2) from the timing circuit 3. And EXOR circuit 72te D-F/F61, D-F
/F71 output results are compared, and the comparison results are JK −
Input to F/F73. The JK-F/F 73 is triggered by the clock φ32 frequency-divided by 1/32 by the multi-stage frequency divider circuit 2, detects an error from the demodulation result, and outputs an error signal (2). That is, in the EXOR circuit 72, each data bit is represented as a set of "0" and "1"; in the example described for the modulation circuit, 1 is represented by "10" and O is represented by "01". Check if there is one, and if not, JK
- Set F/F73 and set error signal ■ to “high”
shall be.

On the other hand, the inverted output (2) of the D-F/F 61 is input to the shift-in terminal of the 8-bit shift register 16. This 8
Since the shift clock of the bit shift register 16 is shifted by the clock φ32 which is frequency-divided by 1/32 by the multi-stage frequency divider 2, the output data of the inverted output of the DF/F 61 is
You'll end up latch shifting all at once.

A timing chart at this time is shown in FIG.

In FIG. 4, ■, φ32. φ, 6. ■、◎、■.

■, ■, ■ are the timings of signals indicated by the same symbols in FIG. 2, respectively.

The above explanation explains the digital modulation/demodulation means that modulates the output data of serial communication under predetermined conditions to produce an output signal, and demodulates the input signal according to predetermined conditions to provide input data, and the input signal of this digital modulation/demodulation means. This is an error detection means that detects an error in accordance with the modulation/demodulation law when demodulating a signal.

Next, the parallel data, signal 2, etc. of the 8-bit shift register 16 shown in FIG. 2 will be explained using FIGS. 5 to 8.

When the received data ■ is shifted and the demodulated data ■ has 8 bits, the latch pulse ■ from the timing generation circuit 3 causes the first
8-bit data is input to the shift data latch circuit 17 and latched.

Next, when 8 bits of the demodulated data (4) are read out and 8 bits are aligned on the next page, the 8-bit data is input to the second shift data latch circuit 18 and latched by the latch pulse (2) from the timing generation circuit 3. Finally, when 8 bits of the demodulated data (3) are read out on the next page, the 8-bit data is input to the third shift data latch circuit 19 and latched by the latch pulse (2) from the timing generation circuit 3.

That is, in this embodiment, space bits, so-called dummy bits, are inserted into the 1 frame so that not all of the demodulated data (2) is made into valid bits, but only a predetermined period of time is determined as valid bits. However, serial communication is performed in a modulated state even with spatial bits.

The data latched in the shift day clutch circuits 17, 18, and 19 are input to a comparison circuit 20 and compared under predetermined conditions. The predetermined conditions in this embodiment are as follows. The demodulated data ■ is “1” as shown in FIG.
, 0.102. I.D.I.

D7. D6. D5. D4. X, X, X,
X, D3. D2. D.I.

00.100. /D1. /D2. /D3. X, X,
X, /D4. /D5. /D6°/D7. /ID2. /
101. /IDO, IDO, X” (7) Enter in order.
L6 (here, Dn means data, /Dn means inverted data, and X means space bit and is "O'° in practice). Therefore, the predetermined condition to be compared is , as shown in FIG.

The comparison is made as above, and the output of each EXOR circuit is
The data are combined into one by the ND gate 201 and output as a data comparison signal @. This data comparison signal 0 is inputted to the NOR gate 202 together with the error signal ``during the demodulation'', and the signal ``dirty'' is output.

In other words, this data comparison signal @ becomes 'high' if there is even a 1-bit comparison error, and the signal ■ becomes high regardless of the state of the error presence signal ■ checked at the time of demodulation.
In order to set it to "I20W", the output of the AND gate 213 is cut off, and the output of the transmission data disappears.

FIG. 7 shows a timing chart of the shift data latch circuit and comparison selection circuit. The timing chart shown in Fig. 7 shows the timing when normal data is received.The signal @ becomes "120w" after receiving the demodulated data (■), and the error signal (■) of the demodulation result also becomes "120w" with no error.
Therefore, the signal ■ becomes "high" and the output of the AND gate 213 becomes enabled, making it possible to output the transmission data, and the AND gate 22 opens due to the signal ■, and the latch pulse from the timing generation circuit 3 is output. (2) is loaded into the data output circuit 10, and the output data is output. In the figure, 2, 2, and 2 are latch pulses from the timing generation circuit 3, which provide load pulses to the shift day latch circuits 17, 18, and 19. As a result, in the figure, 1.
The second and third latch data are latched and the comparison result signal 0 shown in FIG. 6 is generated. The above is an explanation of how to capture received data.

Next, the sweep of transmission data will be explained according to the timing chart of FIG. Although the contents of the transmitted data are not particularly illustrated, each data is latched by outputting a latch pulse in from the timing generation circuit 3 to each data input circuit 8.9 at an arbitrary timing not particularly limited, such as when reception is started, for example. Furthermore, each data output 11 to 14 outputs the ID data and data in the transmission data separately into positive data and negative data (ID2 to IDO, /ID2 to /IDO, D7 to Do in FIG. 7).
, /D7 to /DO), and the select pulses ■, ■, ■ from the timing generation circuit 3 are output to the data encode circuit 15 at respective timings, and output data to the 8-bit shift register 16 is prepared. . On the other hand, although the shift data load signal to the 8-bit shift register 16 is not particularly shown, the OR of the select pulses ■, ■, ■ is output in the timing generation circuit 3, and a total of three 8-bit shifts are performed. The signal is then outputted as a shift-out signal ■ to the EXOR circuit 212 in FIG. On the other hand, if the result of the error signal ■ during reception and the data comparison error signal @ is no error, the transmission permission signal ■ remains "high" until the shift out signal ■ is output as shown in FIG.
continues. However, if the signals ■ and @ are "βOW", the AND gate 213 will not output the transmission data even if the shift-out signal ■ is output.

The above explanation is the processing structure of one frame data in serial communication, including the comparison means that has positive data and negative data in one frame of received data and compares them, and the structure that has spatial bits in one frame. A timing means for determining the timing of valid bits, adding positive data and negative data to the transmitted data,
means for providing space bits and forming transmission data;
These include data error detection means and the like for detecting errors in the comparison means and timing determination means. Note that the circuit described in relation to the processing structure of one frame data of serial communication in this embodiment is just an example and is not particularly limited, and any circuit that executes the purpose may be used. Needless to say, it's a good thing.

<Other Embodiments of Serial Communication Device> Next, a serial communication device of another embodiment will be described.

In the embodiment described above, the number of bits of the serial data to be transmitted and received was treated as 32 bits, but this is for ease of explanation, and the number of bits is not particularly limited. Furthermore, even if one frame of communication data includes positive data and negative data, it goes without saying that all valid bits are not necessary.

Furthermore, similarly, the space bit may be absent, or it may be sufficient if there is one or more bits. Therefore, for example, if the configuration is such that the ID data is only positive, the start bit is 1 bit, the end bit is eliminated, and the data bits are 8 bits for positive and 4 bits for negative, the number of bits for transmitting and receiving serial will be 16 bits. In this embodiment, the number of bits of the serial data to be transmitted and received is set to 32 bits in order to reduce the probability of data transmission error in serial communication.If further improvement in reliability is considered, for example, 40 bits, 40 bits, etc. The number of bits can be increased to 56 bits, 64 bits, etc.

Next, in the embodiment described above, the shift register 16 was operated with 8 bits, but the number of bits of serial data to be transmitted and received (
The number of bits may be the same as the number of bits in one frame.

In other words, it may be configured with a 32-bit shift register. If the shift register 16 were constructed as a 32-bit shift register, the block diagram would be as shown in FIG.

In FIG. 9, the same symbols are used for the same parts as in FIG. 1. In the figure, 16' is a 32-bit shift register,
The data encode circuit 15 and each shift data latch circuit 17, 18, and 19 in FIG. 1 are omitted by using a 32-bit shift register 16'. In terms of operation, the shift data ■ is not processed in 8-bit units, but in 3-bit units.
The operation is similar to that shown in FIG. 1, except that 2 bits are shifted in at once and data is loaded into the comparison and selection circuit 20, and that all bits of transmission data are directly loaded from each data output 11 to 14. becomes.

Furthermore, although the configuration of the above embodiment is a serial communication device on the receiving side of serial communication, that is, on the slave side, there is a group for receiving the output state of the timing pulse from the timing generation circuit 3 in FIG. If you change the order of the group for sending and the group for sending, output the group for sending first and execute the sending operation, then output the group for receiving and execute the receiving operation. Serial communication device on the master side. Therefore, a serial communication device on the sending side of serial communication, that is, on the master side, can be easily realized by the same operation as shown in FIG. As a result, in so-called master-slave serial communication, the transmission timing of the transmission data and the reception timing of the reception data are different for both the master and the slave, so that the transmission and reception signals of this serial communication will not collide. In other words, there is no limit to the number of lines in either the full-duplex system or the half-duplex system.

Furthermore, even in so-called 1:N serial communication where one master and N slaves are used, ID data is added to each serial communication data and can be easily identified, so it is not necessarily 1:1 communication; A serial communication device is used as is. Moreover, since the reception timing and transmission timing of the serial signal for reception and transmission are different, at the optical communication terminal (optical communication connection cut-off) formed by the light emitting element and the light receiving element, the light emission timing of the light emitting element during transmission is different. Even when the light-receiving element on the transmitting side receives the transmitted signal, it does not malfunction even if it appears to have received the received signal from another optical communication terminal, making it suitable for optical communications.

Further, in the embodiment shown in FIG. 1, when a reception signal is received by serial data input, the synchronization circuit 4 immediately accepts the reception signal and immediately starts the reception operation. Therefore, the first
As shown in FIG. If there is a communication error such as an error, serial transmission will not actually be performed, but reception of received data will be prohibited as described above during the period during which it should be transmitted), and if reception is avoided during transmission, further malfunctions will occur. This makes it more suitable for optical communications.

As explained above, (1) The output data of serial communication is modulated according to predetermined conditions and output as an output signal, and the input signal is demodulated according to predetermined conditions and used as input data.

(2) Detect errors such as modulation or noise during demodulation of the input signal.

■ One frame data contains positive data and negative data, which are the same data, and are compared with each other.

■ There is a space bit within one frame data, and the timing of the valid bit is determined.

■ Perform error detection by taking the comparison and timing.

Providing the above check function has the effect of preventing erroneous information transmission of serial communication data such as noise generated in the device, and preventing malfunction of the device.

In addition, the information transmission means of serial communication is replaced by optical wireless transmission (
It also has the effect of preventing erroneous information transmission of serial communication data, such as disturbance light generated within the device when transmitting data in the air (such as with a remote control), and preventing malfunction of the device.

Application example of the present serial communication device> Figure 11 is a diagram showing an example of the configuration of a system using the present serial communication device for optical communication. 100 is the main controller,
Reference numerals 110, 120, and 130 denote unit devices as a block configuration including actuators such as motors, fans, and solenoids, switches, and sensors. Note that although the number of these units differs for each device, three is shown for the sake of explanation. 102 is a drive circuit for optical communication, 102a is a light emitting element, 103 is an amplifier circuit for optical communication, and 103a is a light receiving element that performs photoelectric conversion. Hereinafter, the above 102 and 103 will be collectively referred to as the optical communication terminal 101.

104 is the serial communication device of the above-described embodiment, and when the serial signal 102b is sent to the optical communication terminal 101, the light emitting element 102a emits light to transmit serial data. Further, when optical transmission is received from the unit devices 110 to 130, it is received by the light receiving element 103a, and a serial signal 103b is received. After checking the data mentioned above, if the data is true, serial-parallel conversion is performed and C
Human power is applied to PU105. Further, the data sent from the communication terminal is sent out from the light emitting element 102a after adding the predetermined conditions to the data output from the CPU 105 and subjecting it to disjoint conversion.

On the other hand, each of the units 110, 120, and 130 has an optical communication terminal 101', although not particularly shown in the figure, and performs data transmission with the main controller 100 by light. Note that each unit may have a CPU configuration similar to the main control device 100 depending on its purpose, or may have a solenoid, sensor, etc. directly connected to the data in and data out of the serial communication device 104. .

<Control of Transmission/Reception Timing> In the case of optical communication, the serial communication device 104 requires various measures to prevent disturbances and collisions.

FIGS. 12 and 13 show a transparent frequency division circuit 1 for transparent frequency division of the system clock. 2 is a preferred circuit diagram of a multistage frequency divider circuit 2, a synchronization circuit 4, and a frequency division control circuit 5. FIG. Note that the timing generation circuit 3 will be omitted here because its output timing will be described each time the operation is explained. FIG. 12 particularly shows a specific example of a serial communication device attached to the main control device 100 shown in FIG. 11, and will be abbreviated as master communication device hereinafter. Further, FIG. 13 shows a specific example of a serial communication device attached to the units 110 to 130 in FIG. 1, and is hereinafter abbreviated as a slave communication device.

In this example, the multistage frequency divider circuit 2 divides the frequency by "210" and outputs each stage to the timing generation circuit 3 to generate an arbitrary timing described later. It goes without saying that the circuits shown in FIGS. 12 and 13 are not particularly limited circuits, and may be any circuit that fulfills the purpose described below.

In FIG. 12, when the power is turned on, although not particularly shown, when each circuit is reset and initialized,
The operation of the multi-stage frequency divider circuit starts. Then, the signal [phase] becomes "high", enabling the data sending operation described above, and sending data is output from the AND gate 213, resulting in the serial data output 102b in FIG. 11.

Note that since one input of the AND gate 23 receives an inverted signal of the signal [phase] from the timing generation circuit 3, even if the serial data input signal 103b is input to the synchronization circuit 4, it is ignored. Since this signal [phase] is always "high" only when transmitting data, reception of received data is prohibited while transmitting data is being transmitted. In other words, while data is being received, sending out transmission data is prohibited.

Immediately after the master communication device outputs the transmission data, the signal [phase] becomes "I2ow" and the AND gate 23 opens to enable reception. Normally, when the master communication device outputs transmission data, the slave communication device then inputs reception data. When received data enters D
-F/F43.

At 44, synchronization is achieved with the clock φ2 outputted from the % frequency divider circuit 1, and outputted to the demodulation conversion circuit 6. On the other hand, each output of D-F/F43 and 44 is connected to AND gate 5.
4, passes through the NOT gate 56, and is input to the set terminal of the multistage frequency divider circuit 2. Also, the output of the AND gate 54 enters the J terminal of the J K -F/F 55, and becomes the /Q ratio output "ffow" at the next clock φ2, and the set output of the multistage frequency divider circuit 2 from the AND gate 54 becomes the J K
-F/F55 (7) Timing generation circuit 3 on K terminal
It remains "high" until the set permission signal (2) is input from. Incidentally, the set permission signal [F] from the timing generation circuit 3 is set to "h" immediately before the end of sending the transmission data.
Since "high" is output, all stages of the multi-stage frequency divider circuit 2 are not set even if the received signal is input from immediately after receiving the received data until the next transmission is completed, and the input processing of the received signal is not performed. It won't happen.

Here, the operation of the multistage frequency divider circuit 2 will be explained. The multi-stage frequency dividing circuit 2 is composed of "210" circuits, and the timing generation circuit 3 further performs the frequency division, resulting in a "2+1" configuration.

Therefore, the counter set by the output of "120w" from the NOT gate 56 becomes "FFFH", and after the countdown, the signal [phase] becomes "high" at "7 F F H".
h” and starts transmitting operation. Then, the transmission ends “
At "3FFH", the signal [phase] becomes "βow" and becomes ready for reception, and when the next reception occurs, it becomes "F F F H" again.

That is, the signal (2) is controlled to be "high" only when the counter value is "7XXH" and to be "βOW" thereafter. Therefore, when communication is running normally, 7FFll ~ 3FFII FFFH ~
Repeat steps 7FF)l to 3FF)I.

However, if the received data does not come even after reaching "3 F F H", the countdown continues and the data changes from "O" to "F".
When it returns to ``FFH'' and becomes ``7FFH'' again, the next transmission begins.In addition, if the reception can be received at the transmission timing of the transmission method, it will become ``FFFH'' at the start of reception, so the above normal condition The multi-stage frequency divider circuit 2 is configured as a so-called ring counter, so when the received data is not received, the receiving operation is prohibited by the AND gate 23 after receiving data for a predetermined period. , start executing a new transmission.

Next, using FIG. 13, the differences between the serial communication device on the slave side and FIG. 12 will be explained.

The DF/Fs 41 and 42 synchronize the received data like the DF/Fs 43 and 44, but in the case of a slave, the multistage frequency dividing circuit 2 is composed of "210".

In FIG. 13, when the power is turned on, each circuit is reset and initialized (not particularly shown), and the multi-stage frequency divider circuit 2 is enabled to operate.
Since the /Q ratio output of 2 is "high", the counter remains set and stopped. Upon receiving the received data, the output of the AND gate 51 becomes "high",
Since the /Q ratio output of JK-F/F52 becomes 'Aow', the counter starts counting down. The input signal (■) to the terminal of the JK-F/F52 is output when the count value reaches "O'° by the timing generation circuit 3. Therefore, as in FIG. Even if a received signal is input, all stages of the multistage frequency divider circuit 2 are not set until the transmission of the multistage frequency divider circuit 2 is completed.
When the signal (2) is input to the terminal input of the JK-F/F 52, the /Q ratio output becomes "high" again, so the counter is set in all stages and stops until the next reception is received. In other words, the counter of the slave multi-stage frequency divider circuit 2 counts down only once for - times of reception, performs data reception processing and data transmission processing, and then stops. In other words, 7FFll ~ 3FF)l ~
It becomes 000H.

On the other hand, the AND gate 213 is enabled to transmit by a signal [phase] that is "high" only during the transmission period, as in FIG. 12. In other words, Signal [stock] has a counter of “3XXH”.
It becomes “high” only during ”.Also, as mentioned above,
The transmission data ■ will no longer be output due to the reception data error signal ■.

<Example of transmission of reception error> In the above embodiment, when an error occurs, A, ND gate 2
At step 13, the transmission data becomes “β” due to the reception error detection signal ■.
ow" and the transmission data was not sent. However, if an error occurs as shown in FIG. 14, the content of the data error may be sent as transmission data. In FIG. In order to facilitate this, let us take as an example the 1=1 correspondence between the master and the slave in a communication mobile phone.In addition, if the master and the slave have a 1:N correspondence, the comparison selection circuit 20
Comparison of data of received error detection signal ■ and I
Separate from comparison of D data only, receive error detection signal■
Separately, if the ID data comparison result is input to the AND gate 215 instead of the signal O, only the slave communication device specified in the received data will receive the received data, and if a reception error occurs, the received data will be Only the slave communication device specified by will send the details of the data error in the transmitted data.

The circuit shown in FIG. 14 is a so-called selector circuit, and when the received data error signal ■ is "high", the content of the transmitted data signal ■ is output from the OR gate 216 by the transmission permission period signal [phase] and the transmitted data ■. is sent. On the other hand, when the received data error signal ■ is "120W" (error), only the transmission permission period signal [phase] is output from the OR gate 216 by the AND gate 215, so the transmission data is sent out in a "high" state. Output throughout the period.

Since it is "all high", the communication device on the master side can recognize that there was a data error during data demodulation on the slave side.

FIG. 15 shows a timing chart of each signal on the circuit of FIG. 14. In this example, the data error response is set to "all high", but this is just -
This is just an example, as long as the purpose is achieved, and there is no particular need for it to be "all high".By this, after sending, the master communication device will know the existence of the other party if it receives a reply, and if there is no reply, it will know the existence of the other party. You can tell if there is no other party or if there is a problem with the transmission path.For example, if there is even one slave communication device that can successfully communicate, if there is no reply, it is determined that the unit does not exist, rather than a problem with the transmission path. I can do it.

As explained above, there are measures such as prohibiting data reception while data is being transmitted, and prohibiting the start of a new reception operation for received data until the count of the data acceptance period ends when received data is received. I did it. Furthermore, we have devised a way to prohibit the sending of transmitted data when an error is detected in the received data. With the above improvements, it is possible to perform optical transfer at a relatively high speed, and to solve problems such as collision of respective beams of transfer or mistransmission due to disturbance light when bidirectional transfer is performed.

Furthermore, as shown in Fig. 14, when an error is detected, the content of the data error is sent in the transmission data, so that even if the transmission fails, the presence or absence of the transmission destination can be confirmed. Even in this case, transmission can be prohibited by ID data, and garbled transmission data caused by collision of respective lights for transfer can be prevented.

Next, processing of other communication errors will be explained using FIG. 16.

In FIG. 16, 81 is a counter circuit having a predetermined number of stages, which uses the transmission permission signal [phase] as a clock, and uses the AN
The output signal @ of the D gate 54 is input to reset the counter. Note that the other parts are the same as those shown in FIG. 12. The counter circuit 81 counts up each time the serial communication device transmits in accordance with the transmission permission signal [phase] which becomes "high" when transmitting. However, if received
The count value of the counter circuit 81 is reset by the signal @ from the D gate 54. Therefore, if communication is performed normally, the count value of the counter circuit 81 will not overflow.

However, if reception is not performed continuously, the count increases due to transmission, and eventually the counter circuit 81 overflows and outputs a ripple carry-out (denoted as RCO). This ripple carryout may be used as a communication error signal to reset the system, for example. In addition, each slave communication device does not need to take any particular action when this communication error occurs, but it may be reset periodically when transmission from the master communication device stops (for example, Although not shown, it may be similar to the counter circuit 81 and is not particularly limited).

As explained above, when there is no reception of transmitted data, a count is performed, and when the count reaches a predetermined value, it is determined as a communication error. This prevents the optical communication device from running out of communication, and also allows you to check whether there is a transmission destination or not. It also has the effect of being able to be confirmed.

Next, with reference to FIG. 17, further processing of other communication errors in the communication system will be explained.

In FIG. 17, 90 is the ID of the ID data input circuit 8.
This is a selector circuit that selects the reception synchronization signal @ which is the output of the AND gate 54 according to the data and transmits it to a desired counter circuit in the subsequent stage. 94, 95, and 96 are counter circuits whose clocks are the transmission permission signal [phase], and the output of the selector circuit 90 is input to the clear terminal.

In addition, 97 is an input A for ripple carryout output when the counter circuits 94 to 96 overflow.
It is an ND gate. In addition, the CPU 105 has ripple carry-out and AND signals from the counter circuits 94 to 96.
The output of gate 97 is input.

Counter circuits 94 to 96 are counted up by a transmission permission signal output every time a transmission is made, and when they overflow, the counter ripple carries out (R in the figure).
(denoted by CO) notifies the CPU 105 of this fact. Moreover, when all the counters overflow, this is also determined by the AND gate 97.
Inform U105. On the other hand, since the counter circuits 94 to 96 are cleared in response to the ID data from the ID data input circuit 8 each time they are received, the counter ripple carryout is not output while normal communication is successful. Note that the circuit shown in FIG. 17 is just an example, and the circuit is not particularly limited as long as it can achieve the purpose.

Test Function of the Present Serial Communication Device> Next, a configuration for realizing assembly and maintenance adjustments of the present optical communication device will be explained using FIG. In FIG. 18, 106 indicates the received serial signal 103b and the CP
This is a selector circuit for outputting either of the test serial signals generated from U105 to the serial communication device 104.

Reference numeral 107 is a test manual means for instructing the CPU 105 to enter the test mode. Note that this test input means is not particularly limited, and may be used to receive instructions from an external device, for example. Moreover, the configuration shown in FIG.
This corresponds to the main control device 100 in FIG. 11, and the same parts are indicated by the same reference numerals.

Error Handling and Test Procedures> The CPU 105 performs control according to the flow chart shown in FIG. However, the CPU 105 is
Controls other than those shown in the figures are also performed, but in order to simplify the explanation, only the necessary parts of the program will be described.

Normally, upon entering step SIO, it is checked whether there is a test mode request for the communication device. In the case of communication mode, the process goes to step Sll and step S12. I with S13
Controls the output of D data so that it is accessed in order. Then, in step S14, the ID data to be transmitted is recognized. Note that this ID data is the number for a plurality of counter circuits as shown in FIG. 17, and this is also the number of slaves that perform optical communication. Therefore, the number of IDs shown in the program “N”
N" is determined by the number of slaves that perform optical communication. Here, since it is the same as when the ID is "0", when the ID is "1", when it is "2", ... "NN" The explanation regarding the time will be omitted.

When entering step S15, the ripple carry-out signals from the plurality of counters corresponding to the currently designated ID number are checked. In addition, the ID on the flowchart
Although "none" is written here, after checking whether all errors occur from the output of the AND gate 97, if an error occurs, communication control is stopped and the communication device is reset (not shown). Further, if there is no error, the counter corresponding to the ID to be transmitted is checked, and if there is no overflow, the process goes to step S16, and if there is an overflow, it is determined that there is no communication partner and the process returns to step S11. Incidentally, in step S15, it may be determined only whether there is a communication error or not, and the transmission may be performed regardless of the presence or absence of the other party. and step 516
In S17, each data is called from the memory and output to each pre-allocated port output. Then, in step S18, the end of communication is checked, and if it has ended, step S1
Return to l and repeat again.

Note that in step 5ll-313, the ID numbers to be transmitted next are determined in order, but this is just an example. Prioritize the target as necessary, such as dividing the transmission into groups etc. and determining the order.
The D numbers may be determined in order.

On the other hand, if the test input means 107 instructs to enter the test mode, the process moves to step S20, sets the ID number to the test mote registration number (expressed as Xx in this example), and
In step S21, ID data and transmission data are output. Although the test transmission data is not particularly specified, it may be, for example, test data for instructing each slave communication device, or may indicate other information. Then, in step S22, the end of communication is waited for, and in step S23, it is confirmed that communication has been performed several times. As a result, even if each slave communication device fails in its reception operation, it can receive at least one of the several test mode-in instructions.

Next, the process moves to step S24, and a test operation as the serial communication device is executed. Although this test operation is not specifically illustrated, the purpose is to check the serial communication device itself, and since it differs depending on the equipment in which this serial communication device is used, it is not particularly limited. However, an example is shown below.

The test mode operation is, for example, something like an input/output check called a CPtJ check program, which communicates test serial data output from the CPU as if it were receiving data. device 104
give to As a result, the parallel data and transmission data (serial out data) output by the communication device 104 are transferred to the CP.
U105 checks it. Of course, not only the status when communication is successful, but also abnormal operations are checked.

When the test is completed, the process moves to step S25, and a check is made to cancel the test mode. If it has not been released yet, the process returns to step S24 and the test operation is repeated once again. Also, if the test operation is canceled, step S
Return to ll.

Next, the test mode-in operation on each slave side will be explained using FIG. 20. Note that the test mode operation in this example will be explained separately for the master side and slave side for ease of explanation, but the communication device can operate in any test mode, and there is no particular distinction in terms of hardware. .

In FIG. 20, means 108 and 109 are added for carrying out test operations. Reference numeral 108 is a test mode-in detection means for checking whether the ID data of the received data indicates test mode-in, and is an ID comparison means for comparing the received ID number with the pre-registered ID number "xx". It is a circuit. 109 is I
This is a selection circuit that selects whether the received serial data to be input to the communication device is the one received from the master side or the transmitted serial data outputted by itself according to the result of the D comparison circuit 108. Furthermore, if it is serial data that you have sent, the ID data in that data will not result in a received data error in the comparison result in the comparison and selection circuit 20, so the data manually entered by the transmission data input in this communication device will be the received data output. It begins to appear. In other words, the state of each sensor is output to the actuator with the corresponding output. When checking, a check jig or the like may be attached to the communication device, and for example, inputs from switches may be received by LEDs. Furthermore, even when it is attached to a device, it can be checked without a jig as described above.

The above is the test operation on the slave side. As mentioned above, it may be performed entirely by the heart, but if the slave side also has a CPU, etc. like the master side, it is necessary to perform the same test operation as on the master side. Needless to say, it's a good thing.

As explained above, there is a plurality of counting means for each unique number depending on whether there is a reply from each slave communication device, and if all the count values exceed a predetermined value, it is determined that there is a communication error, or there are multiple counting means. If some of the count values exceed a predetermined value, it is determined that the unit to which the counting means belongs does not exist, thereby making it possible to determine whether there is a communication device as a transfer destination at the level of the main control unit of the device.

Furthermore, when it is determined that there is no slave communication device, that is, there is no unit, the main control means does not send data to that unit, thereby improving communication efficiency.

Also, when it is determined that the unique number specified in the received data is the registration number of the main control means, it immediately stops serial communication and
By entering the test mode alone, there is an effect that adjustment checks can be easily made in assembling equipment.

In addition, when it is determined that the unique number in the transmitted data has sent the registration number of the main control means, it immediately stops serial communication and enters the test mode independently, making it easier to check the adjustment and When transmitting the unique number as the registration number of the main control means, transmitting it multiple times has the effect of saving a communication device that fails to enter the self-diagnosis mode due to a communication error that may occur sporadically.

[Effects of the Invention] According to the present invention, it is possible to provide a serial communication device that can prevent collisions in bidirectional transfer, eliminate erroneous transmission, and perform high-speed transmission.

In particular, in optical communication, problems such as collision of lights and mistransmission due to disturbance light that occur when transferring data in both directions are solved, and disturbance data is prevented from being converted into data.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the serial communication device of this embodiment, FIG. 2 is a diagram showing a detailed circuit example of the demodulation and modulation circuit in FIG. 1, and FIGS. 3 and 4 are the diagrams in FIG. 5 is a diagram showing a detailed circuit example of the comparison and selection circuit shown in FIG. 1, FIG. 6 is a diagram showing the comparison conditions of the comparison circuit, and FIGS.
The figure is a timing chart of the circuit diagram shown in FIG. 5, FIGS. 9 and 10 are diagrams showing modifications of this embodiment, and FIG. 11 is a configuration diagram of a system to which the serial communication device of this embodiment is applied. Fig. 12 is a diagram showing an example of frequency division control when the serial communication device of this embodiment is used on the master side, and Fig. 3 is an example of frequency division control when the serial communication device of this embodiment is used on the slave side. FIG. 4 is a diagram showing an example of a circuit that returns an error in the event of a reception error. FIG. 15 is a timing chart of the circuit diagram shown in FIG. 14. FIG. FIG. 17 is a diagram showing an example of a communication error detection circuit, FIG. 8 is a diagram showing an example of a circuit in test mode on the master side, FIG. 19 is a flowchart showing an example of control of the CPU 105, and FIG. It is a figure which shows the circuit example of the side test mode. In the figure, 1... station frequency divider circuit, 2... multistage frequency divider circuit, 3
...Timing generation circuit, 4...Synchronization acquisition circuit, 5
... Frequency division control circuit, 6... Demodulation conversion circuit, 7...
Error detection circuit, 8... ID data input circuit, 9...
・Data input circuit, 10...Data output circuit, 11゜12.13.14...Each data output circuit for transmission data, 15...Data encoder circuit, 16...
8-bit shift register, 17, 18.19... Latch circuit for each shift data, 20... Comparison selection circuit, 2
1... Modulation conversion circuit, 22. ．． 23...AND gate, 81.94-96...Counter circuit, 90...
Selector circuit, 97...AND gate, 100...
Main control device, 101, 101'... Optical communication terminal, 102... Drive circuit, 102a... Light emitting element, 103... Amplifying circuit, 103a... Light receiving element, 1
04,104'...Serial communication device, 105...
CPU, 81.94-96... Counter circuit, 90.
...Selector circuit, 97...AND gate, 106.
...Selector circuit, 107...Test input means, 10
8... Test mode-in detection means, 109... Select circuit, 110, 120° 130... Unit device.

Claims (3)

[Claims] (1) A device having a unit group in which distributed output signals and input signals are physically and functionally organized into a plurality of blocks, and a main control section that collectively controls the unit group, wherein the main control section and the unit A serial communication device that serially transmits information to and from a group of devices, the device comprising: a first reception prohibition means for prohibiting data reception during data transmission; a second reception inhibiting means for inhibiting the start of a serial communication device. (2) When used on the master side, further comprising a transmission start means that permits data reception after the predetermined period has elapsed and starts the next data transmission if no new data is received for the predetermined period. The serial communication device according to claim 1, characterized in that: (3) Serial communication according to claim 1 or 2, further comprising a photoelectric conversion means for converting an electrical signal and an optical signal, and the serial transmission of information is performed by optical communication using light. Device.