JPH0324640A - Debugging system for information processor - Google Patents

Abstract

PURPOSE:To simply and surely obtain data necessary for the analysis of fault cause by controlling a selector corresponding to a debugging mode to transfer data between a CPU and a main storage by using a cache memory as by-pass and storing trace data in the cache memory. CONSTITUTION:A debugging mode FF 2 outputs a setting signal 103 by a debugging mode signal 102 outputted from a diagnostic processor 1 to control selectors 3, 7, 8. The selector 8 selects cache memory reading data 107 or data in a main storage reading data and main storage writing data 106 are sent from the CPU 5 to the main storage through a data bus 100 and the cache memory 4 is by-passed. On the other hand, the selectors 7, 3 respectively select a cache memory address 109 from the CPU 5 and trace data 104 and the data 104 are written in the memory 4. Thus, trace data necessary for the analysis of a fault cause can be easily and surely acquired in the cache memory 4 without increasing the number of hardwares.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a debugging method for an information processing device, and more particularly to a method for storing trace data used for angular analysis of the cause of a failure when a failure occurs in a central processing unit.

BACKGROUND ART Conventionally, in an information processing device, a dedicated trace memory was installed for analyzing the cause of a failure when a failure occurred in the central processing unit, and the operation history of the central processing unit was stored in the trace memory every clock. .

In such conventional information processing devices, a dedicated trace memory is provided to store the operation history of the central processing unit every clock, which has the disadvantage of increasing the amount of hardware.

Purpose of the Invention The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional system.The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional system. An object of the present invention is to provide a debugging method for an information processing device that can obtain the following information and reduce the amount of hardware.

Structure of the Invention A debugging method for an information processing device according to the present invention is a debugging method for an information processing device having a cache memory, which comprises address supply means for supplying an address to the cache memory in a debug mode, and a bypass means for performing data transfer between a processing device and a main memory by bypassing the cache memory, and storing trace data in the cache memory using an address supplied from the address supply means during the debug mode. It is characterized by the following.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, in the debug mode, the diagnostic processor 1- sends a debug mode signal 102 to the debug mode flip-flop (hereinafter referred to as debug mode FF) 2 to set the debug mode FF2, and also resets the address counter 6. signal 101
Send out.

Selector 3 outputs the output signal from debug mode FF2 [
08, one of the trace signal 104, main memory read data 105 from the main memory (not shown), and main memory write data 10B from the central processing unit 5 is selected, and the debug mode FF2 is set. The trace signal 104 is selected by this.

Further, in the selector 7, either the cache memory address 109 from the central processing unit 5 or the cache memory address l08 from the address counter 6 is selected according to the output signal 103 from the debug mode FF2. By setting , the cache memory address 108 is selected.

Further, the selector 8 selects either main memory read data 105 from the main memory or cache memory read data 107 from the cache memory 4 in accordance with the output signal 103 from the debug mode FF2.
Main memory read data 105 is selected by setting debug mode FF2.

Therefore, in the cache memory 4, the trace data 104 selected by the selector 3 is stored at the address specified by the cache memory address 108 selected by the selector 7.
is stored.

At this time, when main memory access occurs in the central processing unit 5, the main memory read data 105 read from the main memory is manually input to the central processing unit 5 via the selector 8, and written from the central processing unit 5 to the main memory. The loaded main memory write data l0B is sent to the main memory via the data bus l00.

That is, when the debug mode is set to debug mode FF2, the central processing unit i15
cannot be used, and access to the main memory is performed by bypassing the cache memory 4.

The address counter 6 updates the address every time a clock signal (not shown) is input, and the trace signal 10 is sent to the address of the cache memory 4 specified by this address.
4 are stored sequentially.

When the contents of the address counter 6 indicate the maximum address of the cache memory 4 by updating the address, the address counter 6 sends an address count up signal 110 to the diagnostic processor 1.

When the diagnostic processor 1 receives the address count-up signal 110 from the address counter 6, it outputs an execution inhibition instruction signal 111 to the central processing unit 5 and starts reading the contents of the cache memory 4.

In the central processing unit 5, execution of the instruction is stopped by this execution inhibition instruction signal Ilt, and the CPU enters a wait state.

When the diagnostic processor 1 receives all the cache memory read data 107 from the cache memory 4, it outputs an address counter reset signal 101 to the address counter 6, resets all the contents of the address counter 6 to "0", and the central processing unit Execution suppression instruction signal Ut to 5
to resume tracing operation.

In this way, in the debug mode, data transfer between the central processing unit 5 and the main memory is performed by bypassing the cache memory 4, and the trace signal 104 is transferred to the cache memory 4 using the cache memory address 108 from the address counter 6. By storing the trace signal 104 necessary for analyzing the cause of a failure when a failure occurs in the central processing unit 5, it is possible to obtain the trace signal 104 without providing a dedicated trace memory.

Also, since there is no need to provide a dedicated trace memory,
The amount of hardware can be reduced.

Effects of the Invention As explained above, according to the present invention, data transfer between the central processing unit and the main memory is performed by bypassing the cache memory in the debug mode, and trace data is stored in the cache memory. By doing so, it is possible to obtain the trace data necessary to analyze the cause of a failure when a failure occurs in the central processing unit without providing a dedicated trace memory, and the amount of hardware can be reduced. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the structure of an embodiment of the present invention. Explanation of symbols of main parts 1...Diagnostic processor 2...Debug mode flip-flop 3, 7.8...Selector 4...Cache memory 5... ... Central processing unit 6 ... Address counter

Claims (1)

[Claims] (1) A debugging method for an information processing device having a cache memory, which includes address supply means for supplying an address to the cache memory in a debug mode, and data transfer between a central processing unit and a main memory in the debug mode. A debugging method comprising bypass means for bypassing the cache memory, and storing trace data in the cache memory using an address supplied from the address supply means during the debug mode.