JPH03222340A - Circuit board to mount semiconductor device on - Google Patents
Circuit board to mount semiconductor device onInfo
- Publication number
- JPH03222340A JPH03222340A JP1752290A JP1752290A JPH03222340A JP H03222340 A JPH03222340 A JP H03222340A JP 1752290 A JP1752290 A JP 1752290A JP 1752290 A JP1752290 A JP 1752290A JP H03222340 A JPH03222340 A JP H03222340A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- circuit board
- circuit
- parts
- glass
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 239000011521 glass Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 8
- 235000019353 potassium silicate Nutrition 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 238000007772 electroless plating Methods 0.000 claims description 4
- 238000007650 screen-printing Methods 0.000 claims description 2
- 239000004020 conductor Substances 0.000 abstract description 23
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 241000218202 Coptis Species 0.000 description 3
- 235000002991 Coptis groenlandica Nutrition 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000010931 gold Substances 0.000 description 2
- 229910000846 In alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 [産業上の利用分野] 本発明は、半導体装置を実装する回路基板に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a circuit board on which a semiconductor device is mounted.
従来、フェースダウン・ボンディングによる半導体装置
と基板上に形成された突起状電極ハンプとの接合は、第
5図及び第6図に示すように、ボンディングヘッド(図
示せず)に吸着された半導体装置1を、熱と荷重を加え
る熱圧着法により、半導体装置1上に形成されたパッド
(図示せず)と、基板2上の導体回路3に形成された突
起状電極バンプ4(第5図に示すものは金(Au)ハン
プ、第6図に示すものは半田ハンプである)とを接合す
ることにより行なっている。Conventionally, a semiconductor device and a protruding electrode hump formed on a substrate are bonded by face-down bonding, as shown in FIGS. 5 and 6. 1 to a pad (not shown) formed on the semiconductor device 1 and a protruding electrode bump 4 formed on the conductor circuit 3 on the substrate 2 (as shown in FIG. 5) by a thermocompression method that applies heat and load. The one shown is a gold (Au) hump, and the one shown in FIG. 6 is a solder hump).
[発明が解決しようとする課題]
しかしながら、かかる従来例では、突起状電極ハンプ4
は、基板2上の導体回路3に形成しなければならないが
、この製造工程が容易でなく、ドライエツチング又はウ
ェットエツチングによる製法によるため、工程数が多く
、半導体装置1のパッドに対向させるための位置合わせ
精度など問題が多い。[Problems to be Solved by the Invention] However, in such a conventional example, the protruding electrode hump 4
must be formed on the conductor circuit 3 on the substrate 2, but this manufacturing process is not easy and requires a large number of steps because it uses dry etching or wet etching. There are many problems such as alignment accuracy.
本発明は上記問題点に鑑みなされたもので、その目的と
するところは、製造が容易で、半導体装置のパッド部と
の位置合わせ精度も良好な電極部を有する半導体装置実
装用回路基板を提供することにある。The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a circuit board for mounting a semiconductor device that is easy to manufacture and has an electrode portion that has good positioning accuracy with the pad portion of the semiconductor device. It's about doing.
[課題を解決するための手段]
上記課題を解決するため本発明は、基板上に液状ガラス
をスクリーン印刷し、該液状ガラスを硬化させた後、銅
系材料よりなる導体回路を無電解めっき番こより、前記
硬化ガラス上にわたって形成してなる半導体装置実装用
回路基板であって、前記導体回路のガラス上に形成され
た部分は、基板上にフェースダウン・ポンディングされ
る半導体装置のパッド部に対応する位置に形成されてい
ることを特徴とする。[Means for Solving the Problems] In order to solve the above problems, the present invention screen-prints liquid glass on a substrate, cures the liquid glass, and then applies electroless plating to a conductor circuit made of a copper-based material. Accordingly, in the circuit board for mounting a semiconductor device formed over the hardened glass, the portion of the conductor circuit formed on the glass is attached to a pad portion of a semiconductor device that is face-down bonded onto the board. It is characterized by being formed at corresponding positions.
[実施例]
第1図乃至第3図は本発明の一実施例を示し、第1図は
回路基板に半導体装置を実装した状態を示す断面図、第
2図は回路基板の上面図、第3図は半導体装置の裏面図
である。[Embodiment] FIGS. 1 to 3 show an embodiment of the present invention, in which FIG. 1 is a sectional view showing a state in which a semiconductor device is mounted on a circuit board, FIG. 2 is a top view of the circuit board, and FIG. FIG. 3 is a back view of the semiconductor device.
本実施例に係る半導体装置実装用回路基板は、例えばセ
ラミックよりなる基板10上にガラスペースト(液状ガ
ラス)11をスクリー ン印刷し、硬化させる。つぎに
、無電解めっきによりCu。In the circuit board for mounting a semiconductor device according to this embodiment, a glass paste (liquid glass) 11 is screen printed on a substrate 10 made of ceramic, for example, and then hardened. Next, Cu is deposited by electroless plating.
Ni等の銅系材料よりなる導体回路12を形成する。そ
の導体回路12の上層に電解めっきにより金糸材料(ま
たはインジウム合金でも良い)13を堆積する。A conductor circuit 12 made of a copper-based material such as Ni is formed. A gold thread material (or an indium alloy may be used) 13 is deposited on the conductor circuit 12 by electrolytic plating.
ここで、ガラスペースト11に形成された導体回路12
は、ガラスペースト11の厚み分だけ基板lO平面より
突出しており、この突出部分14が、第2図に示すよう
に、半導体装置15のアルミパッド16に接合されるが
、この突出部分14の導体回路12の寸法(大きさ)に
は、次のような制限がある。すなわち、第3図に示すよ
うに、半導体装置15のアルミパッド16の大きさを、
xz(横)Xyz(縦)とし、突出部分14であるとこ
ろのガラスペースト11上の導体回路12の寸法(大き
さ)をx+(横)Xy+(縦)とすると、x、<xz・
yI<yl
の関係を満足しなければならない。ここで、前記X1は
導体回路12と直角方向に形成されたガラスペースト1
1の幅に、ylは導体回路12の幅に等しい。Here, conductor circuit 12 formed on glass paste 11
protrudes from the substrate lO plane by the thickness of the glass paste 11, and this protruding portion 14 is bonded to the aluminum pad 16 of the semiconductor device 15 as shown in FIG. The dimensions (size) of the circuit 12 have the following limitations. That is, as shown in FIG. 3, the size of the aluminum pad 16 of the semiconductor device 15 is
If xz (horizontal) and Xyz (vertical) are the dimensions (size) of the conductor circuit 12 on the glass paste 11, which is the protruding portion 14, are x+ (horizontal) and Xy+ (vertical), then x, < xz・
The relationship yI<yl must be satisfied. Here, the X1 is a glass paste 1 formed perpendicularly to the conductor circuit 12.
1, yl is equal to the width of the conductor circuit 12.
このようにして形成された回路基板に、半導体装置15
を熱圧着によるフェースダウン・ボンディングを行う。A semiconductor device 15 is placed on the circuit board thus formed.
Perform face-down bonding using thermocompression bonding.
このとき、半導体装置15のアルミバンド16と導体回
路12の上層の金糸材料13は、Au−A1拡散により
合金層を形成して接合される。At this time, the aluminum band 16 of the semiconductor device 15 and the gold thread material 13 on the upper layer of the conductor circuit 12 are bonded by forming an alloy layer by Au--Al diffusion.
このように、本実施例においては、導体回路12の突出
部分14が電極部分を構成するので、従来のハンプ形成
工程の省略が図れ、量産が容易となる。また、導体回路
12の突出部分14の形成は、スクリーン印刷法による
ので、半導体装置15のアルミパッド16との位置合わ
せ精度も向上する。さらに、半導体装置15のアルミバ
ンド16と導体回路12は、直接熱圧着されるため、半
導体装置15で発生した熱が導体回路12を伝わって速
やかに放熱される。従って、放熱特性が非常に良く、発
熱量の多いパワーデバイスの搭載用基板に適している。In this manner, in this embodiment, the protruding portion 14 of the conductor circuit 12 constitutes the electrode portion, so that the conventional hump forming process can be omitted and mass production can be facilitated. Furthermore, since the protruding portions 14 of the conductor circuit 12 are formed by screen printing, the alignment accuracy with the aluminum pads 16 of the semiconductor device 15 is also improved. Furthermore, since the aluminum band 16 of the semiconductor device 15 and the conductor circuit 12 are directly bonded by thermocompression, the heat generated in the semiconductor device 15 is transmitted through the conductor circuit 12 and is quickly dissipated. Therefore, it has very good heat dissipation characteristics and is suitable for mounting a power device that generates a large amount of heat.
また、半導体装置15は直接導体回路12と接続されて
いるため、信号伝達距離が非常に短くなり、信号遅延時
間の短縮化が図れる。従って、高速動作するデバイスの
搭載用基板にも適している。Further, since the semiconductor device 15 is directly connected to the conductive circuit 12, the signal transmission distance is extremely short, and the signal delay time can be shortened. Therefore, it is also suitable as a board for mounting devices that operate at high speed.
なお、本発明は上記実施例に限定されるものでないのは
勿論であり、例えば、基板10上に形成されるガラスペ
ースト11は、導体回路12の突出部分14が搭載され
る半導体装置15のアルミパッド16に対向し、このア
ルミパッド16の大きさ以下であれば、どのように印刷
しても良い。Note that the present invention is of course not limited to the above-mentioned embodiments. For example, the glass paste 11 formed on the substrate 10 may be applied to the aluminum of the semiconductor device 15 on which the protruding portion 14 of the conductor circuit 12 is mounted. As long as it faces the pad 16 and is smaller in size than the aluminum pad 16, it may be printed in any way.
例えば、第2図に示す例では、ガラスペースト11は導
体回路12と直交するように形成され、第4図に示す例
では、ガラスペーストllはlll0の中央部に方形に
形成されている。また、アルミパッド16に対向する位
置にそれぞれスボ、ト状に印刷して形成しても良い。For example, in the example shown in FIG. 2, the glass paste 11 is formed to be perpendicular to the conductor circuit 12, and in the example shown in FIG. 4, the glass paste 11 is formed in a rectangular shape at the center of 110. Alternatively, it may be formed by printing grooves and grooves at positions facing the aluminum pad 16, respectively.
上記実施例では、導体回路12はアルミパッド16とA
u−Aj!拡散により接合されているが、導体回路12
の上層に金糸材料13をめっきせず、直接Cu−Aj!
拡散により接合することもできる。In the above embodiment, the conductive circuit 12 is connected to the aluminum pad 16 and the A
u-Aj! Although they are bonded by diffusion, the conductor circuit 12
Without plating the gold thread material 13 on the upper layer of Cu-Aj!
Bonding can also be performed by diffusion.
ただし、下層の銅系材料だけだと接合信頼性は良くない
。However, if only the lower layer copper-based material is used, the bonding reliability will not be good.
[発明の効果1
本発明は上記のように、基板上に液状ガラスをスクリー
ン印刷し、該液状ガラスを硬化させた後、銅系材料より
なる導体回路を無電解めっきにより、前記硬化ガラス上
にわたって形成してなる半導体装置実装用回路基板であ
って、前記導体回路のガラス上に形成された部分は、基
板上にフェースダウン・ボンディングされる半導体装置
のバンド部に対応する位置に形成されていることを特徴
とするので、製造が容易で、半導体装置のパッド部との
位置合わせ精度も良好な電極部を有する半導体装置実装
用回路基板を提供できる。[Effects of the Invention 1] As described above, the present invention screen-prints liquid glass on a substrate, hardens the liquid glass, and then spreads a conductor circuit made of a copper-based material over the hardened glass by electroless plating. In this circuit board for mounting a semiconductor device, the portion of the conductor circuit formed on the glass is formed at a position corresponding to a band portion of a semiconductor device that is face-down bonded onto the substrate. With this feature, it is possible to provide a circuit board for mounting a semiconductor device that is easy to manufacture and has an electrode portion with good alignment accuracy with the pad portion of the semiconductor device.
第1図乃至第3図は本発明の一実施例を示し、第1図は
回路基板に半導体装置を実装した状態を示す断面図、第
2図は回路基板の上面図、第3図は半導体装置の裏面図
、第4図は本発明の異なる実施例を示す上面図、第5図
及び第6図はそれぞれ従来例を示す断面図である。
10・・・基板、11・・・液状ガラス、12・・・導
体回路、
5・・・半導体装置、
■
6・・・パッド。1 to 3 show one embodiment of the present invention, FIG. 1 is a cross-sectional view showing a state in which a semiconductor device is mounted on a circuit board, FIG. 2 is a top view of the circuit board, and FIG. 3 is a semiconductor device mounted on a circuit board. FIG. 4 is a top view showing different embodiments of the present invention, and FIGS. 5 and 6 are sectional views showing conventional examples. DESCRIPTION OF SYMBOLS 10... Substrate, 11... Liquid glass, 12... Conductor circuit, 5... Semiconductor device, ■ 6... Pad.
Claims (1)
ガラスを硬化させた後、銅系材料よりなる導体回路を無
電解めっきにより、前記硬化ガラス上にわたって形成し
てなる半導体装置実装用回路基板であって、前記導体回
路のガラス上に形成された部分は、基板上にフェースダ
ウン・ボンディングされる半導体装置のパッド部に対応
する位置に形成されていることを特徴とする半導体装置
実装用回路基板。(1) A circuit board for mounting a semiconductor device, which is obtained by screen printing liquid glass on a substrate, curing the liquid glass, and then forming a conductive circuit made of a copper-based material over the hardened glass by electroless plating. A circuit for mounting a semiconductor device, wherein the portion of the conductive circuit formed on the glass is formed at a position corresponding to a pad portion of a semiconductor device that is face-down bonded onto the substrate. substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1752290A JPH03222340A (en) | 1990-01-26 | 1990-01-26 | Circuit board to mount semiconductor device on |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1752290A JPH03222340A (en) | 1990-01-26 | 1990-01-26 | Circuit board to mount semiconductor device on |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03222340A true JPH03222340A (en) | 1991-10-01 |
Family
ID=11946282
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1752290A Pending JPH03222340A (en) | 1990-01-26 | 1990-01-26 | Circuit board to mount semiconductor device on |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03222340A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6077725A (en) * | 1992-09-03 | 2000-06-20 | Lucent Technologies Inc | Method for assembling multichip modules |
JP2008072144A (en) * | 2007-11-30 | 2008-03-27 | Matsushita Electric Ind Co Ltd | Wiring substrate |
-
1990
- 1990-01-26 JP JP1752290A patent/JPH03222340A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6077725A (en) * | 1992-09-03 | 2000-06-20 | Lucent Technologies Inc | Method for assembling multichip modules |
JP2008072144A (en) * | 2007-11-30 | 2008-03-27 | Matsushita Electric Ind Co Ltd | Wiring substrate |
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