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JPH0322904Y2 - - Google Patents

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Publication number
JPH0322904Y2
JPH0322904Y2 JP1985136481U JP13648185U JPH0322904Y2 JP H0322904 Y2 JPH0322904 Y2 JP H0322904Y2 JP 1985136481 U JP1985136481 U JP 1985136481U JP 13648185 U JP13648185 U JP 13648185U JP H0322904 Y2 JPH0322904 Y2 JP H0322904Y2
Authority
JP
Japan
Prior art keywords
pattern
chip
pattern surface
reticle mask
patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1985136481U
Other languages
Japanese (ja)
Other versions
JPS62104440U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985136481U priority Critical patent/JPH0322904Y2/ja
Publication of JPS62104440U publication Critical patent/JPS62104440U/ja
Application granted granted Critical
Publication of JPH0322904Y2 publication Critical patent/JPH0322904Y2/ja
Expired legal-status Critical Current

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  • ing And Chemical Polishing (AREA)

Description

【考案の詳細な説明】[Detailed explanation of the idea] 【考案の属する技術分野】[Technical field to which the idea belongs]

本考案は、異なる種類のチツプパターンを有す
る一つのレチクルマスクを用いて、半導体ウエハ
の表面に形成したフオトレジスト層へ、レチクル
マスク上の任意のチツプパターンを縮小して投
影、露光するチツプパターン縮小投影露光装置に
関する。
This invention uses a single reticle mask with different types of chip patterns to reduce and project any chip pattern on the reticle mask onto a photoresist layer formed on the surface of a semiconductor wafer and expose it to light. The present invention relates to a projection exposure apparatus.

【従来技術とその問題点】[Prior art and its problems]

この種の縮小投影露光装置は、10倍または5倍
の大きさでチツプパターンが作られたレチクルマ
スクを縮小レンズを通して、ウエハ上へステツプ
アンドリピート法により投影転写するもので、通
常レチクルマスク上には複数個のチツプパターン
が形成され、これを1シヨツトとしてウエハ上に
転写する。 半導体ウエハ上に形成されるチツプパターン
は、一般には第2図に示すように実用チツプパタ
ーン12の他に、たとえば素子の特性を個々に評
価するための図では対角線を入れて表示した異種
チツプパターン13を1枚のウエハ11に同時に
形成することが多い。しかし従来の縮小投影露光
装置を用いて、ウエハ上に二種以上の異なるパタ
ーンを形成するには、実用チツプパターンのレチ
クルマスクのほかに異種チツプパターンのレチク
ルマスクを個々に準備しなければならず、フオト
マスク製造コストの上昇、露光時のレチクルマス
ク交換による処理能力の低下あるいは異種チツプ
パターンの埋込み精度の低下などを起こす欠点が
あつた。
This type of reduction projection exposure equipment projects and transfers a reticle mask with a chip pattern 10 times or 5 times larger onto the wafer through a reduction lens using a step-and-repeat method. In this method, a plurality of chip patterns are formed and transferred onto a wafer as one shot. Generally, chip patterns formed on a semiconductor wafer include, in addition to a practical chip pattern 12 as shown in FIG. 13 are often formed on one wafer 11 at the same time. However, in order to form two or more different patterns on a wafer using a conventional reduction projection exposure system, it is necessary to separately prepare reticle masks for different chip patterns in addition to reticle masks for practical chip patterns. However, there have been disadvantages such as an increase in photomask manufacturing costs, a decrease in throughput due to reticle mask replacement during exposure, and a decrease in the embedding accuracy of different chip patterns.

【考案の目的】[Purpose of invention]

本考案は、冒頭に述べたように上記の欠点を除
去して異なるチツプパターンが共存する1枚のレ
チクルマスクを用い、必要に応じて半導体ウエハ
上に異なるチツプパターンを形成することができ
るチツプパターン縮小投影露光装置を提供するこ
とを目的とする。
As mentioned at the beginning, the present invention eliminates the above drawbacks and uses a single reticle mask in which different chip patterns coexist, and a chip pattern that allows different chip patterns to be formed on a semiconductor wafer as needed. An object of the present invention is to provide a reduction projection exposure apparatus.

【考案の要点】[Key points of the idea]

本考案は、投射光光源と、パターン面をその光
源より遠い側にしてレチクルマスクを支持する支
持枠と、パターン面のチツプパターンを半導体ウ
エハ上に縮小投影する光学系とを有するチツプパ
ターン縮小露光装置のレチクルマスクのパターン
面に500μm以内に近接し、かつそれに平行に移
動可能の遮光板を備えることにより、レチクルマ
スクの上の任意のチツプパターンのみを投影可能
にして上記の目的を達成する。
The present invention is a chip pattern reduction exposure system that includes a projection light source, a support frame that supports a reticle mask with the pattern surface facing away from the light source, and an optical system that reduces and projects the chip pattern on the pattern surface onto a semiconductor wafer. By providing a light shielding plate that is close to the pattern surface of the reticle mask of the apparatus within 500 μm and is movable in parallel thereto, only an arbitrary chip pattern on the reticle mask can be projected, thereby achieving the above object.

【考案の実施例】[Example of idea]

第1図は本考案の一実施例の使用状態を示し、
レチクルマスク2は、パターン面3を下向きにレ
チクルホルダ4へ真空吸着により装着されてい
る。レチクルマスクのパターン面3から500μm
離れた下方に遮光板5が配置され、操作系の指示
により矢印6の方向に任意位置まで移動させるこ
とができる。これによりレチクルマスクパターン
面の任意のパターン部分のみを紫外線7により縮
小レンズ8を通して半導体ウエハ1の表面のフオ
トレジスト層へ投影露光させることができる。 第3図、第4図は本考案によるチツプパターン
縮小投影露光装置に用いるレチクルマスク2の、
パターン面3における実用チツプパターン31と
評価用の異種チツプパターン32の配置例であ
る。異種チツプパターン32を投影するときには
マスクを遮光板5で覆わないで実用チツプパター
ン31と共に投影し、他のウエハ面領域には異種
チツプパターン32を遮光板31で覆つて実用チ
ツプパターンのみを投影する。従つて、遮光すべ
き異種チツプパターン32を図示のようにチツプ
パターンの周辺に配置することが、遮光板の移動
を単純化する上に望ましい。 本考案による投影露光装置では、縮小レンズ8
の縮小比を例えば1/5にすることにより、1/10縮
小比の場合に比しマスク上の一つのチツプパター
ン面積を1/4にして、マスク上の実用チツプパタ
ーンの数を減少させず、マスク上に異種チツプパ
ターンが共存しても露光作業時間が増大しないよ
うにすることができる。 第5図はレチクルマスク2のパターン面3から
遮光板5裏面までの距離を変えたときのウエハ上
の光のまわり込み量を示す。レチクルマスク2の
パターン面3から遮光板5までの距離が上述のよ
うに500μmであるから、光のまわり込み量はウ
エハ上で100μmであり、隣接するパターンへの
影響は見られなかつた。
FIG. 1 shows the state of use of an embodiment of the present invention,
The reticle mask 2 is attached to the reticle holder 4 by vacuum suction with the pattern surface 3 facing downward. 500μm from pattern surface 3 of reticle mask
A light shielding plate 5 is arranged at a lower part and can be moved to an arbitrary position in the direction of an arrow 6 according to instructions from an operating system. Thereby, only an arbitrary pattern portion of the reticle mask pattern surface can be projected and exposed to the photoresist layer on the surface of the semiconductor wafer 1 by the ultraviolet rays 7 through the reduction lens 8. 3 and 4 show a reticle mask 2 used in a chip pattern reduction projection exposure apparatus according to the present invention.
This is an example of the arrangement of a practical chip pattern 31 and a different type of chip pattern 32 for evaluation on the pattern surface 3. When projecting the different types of chip patterns 32, the mask is not covered with the light shielding plate 5 and is projected together with the practical chip pattern 31, and the different types of chip patterns 32 are covered with the light shielding plate 31 on other wafer surface areas to project only the practical chip patterns. . Therefore, it is desirable to arrange the different types of chip patterns 32 to be light-shielded around the chip patterns as shown in the figure in order to simplify the movement of the light-shielding plate. In the projection exposure apparatus according to the present invention, the reduction lens 8
For example, by reducing the reduction ratio to 1/5, the area of one chip pattern on the mask can be reduced to 1/4 compared to a reduction ratio of 1/10, without reducing the number of practical chip patterns on the mask. Therefore, even if different types of chip patterns coexist on the mask, the exposure operation time can be prevented from increasing. FIG. 5 shows the amount of light that wraps around the wafer when the distance from the pattern surface 3 of the reticle mask 2 to the back surface of the light shielding plate 5 is changed. Since the distance from the pattern surface 3 of the reticle mask 2 to the light shielding plate 5 is 500 μm as described above, the amount of light that wraps around the wafer is 100 μm, and no influence on adjacent patterns was observed.

【考案の効果】[Effect of the idea]

本考案によれば、レチクルマスクのパターン面
直下にチツプパターンの一部を遮光できる移動可
能の遮光板を500μm以内に近接して配置するこ
とで、実用チツプパターンのほかに異種チツプパ
ターンを形成したレチクルマスクを用いて半導体
ウエハ上に異種チツプパターンを任意の位置に投
影でき、不必要の場合には異種チツプパターンを
遮蔽することにより少ない光のまわり込みで実用
チツプパターンのみのシヨツトを投影できる。こ
れにより従来技術で問題であつたレチクルマスク
交換に伴う処理能力の低下および異種チツプパタ
ーンの埋込み精度の低下を防止でき、フオトマス
ク製造コストを低減できる。
According to the present invention, by arranging a movable light-shielding plate that can block part of the chip pattern directly below the pattern surface of the reticle mask within 500 μm, different types of chip patterns can be formed in addition to practical chip patterns. Different types of chip patterns can be projected onto a semiconductor wafer at arbitrary positions using a reticle mask, and by shielding different types of chip patterns when unnecessary, shots of only practical chip patterns can be projected with less light going around. As a result, it is possible to prevent a decrease in processing capacity due to reticle mask exchange and a decrease in embedding accuracy of different chip patterns, which were problems in the prior art, and it is possible to reduce photomask manufacturing costs.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例の使用状態を示す断
面図、第2図は半導体ウエハ上の異種チツプパタ
ーンの形成例の平面図、第3図、第4図は本考案
による投影露光装置に用いるレチクルマスク上の
チツプパターンの二つの例を示す平面図、第5図
はレチクルマスクのパターン面から遮光板裏面ま
での距離とウエハ上でのまわり込み量との関係線
図である。 1:半導体ウエハ、2:レチクルマスク、3:
パターン面、4:レチクルホルダ、5:遮光板、
7:紫外線、8:縮小レンズ、31:実用チツプ
パターン、32:異種チツプパターン。
FIG. 1 is a cross-sectional view showing an example of the use of an embodiment of the present invention, FIG. 2 is a plan view of an example of forming different types of chip patterns on a semiconductor wafer, and FIGS. 3 and 4 are projection exposure apparatuses according to the present invention. FIG. 5 is a diagram showing the relationship between the distance from the pattern surface of the reticle mask to the back surface of the light-shielding plate and the amount of wraparound on the wafer. 1: Semiconductor wafer, 2: Reticle mask, 3:
pattern surface, 4: reticle holder, 5: light shielding plate,
7: Ultraviolet rays, 8: Reduction lens, 31: Practical chip pattern, 32: Different types of chip patterns.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 投射光光源と、パターン面を該光源より遠い側
にしてレチクルマスクを支持する支持枠と、前記
パターン面のチツプパターンをウエハ上に縮小投
影する光学系とを有するものにおいて、レチクル
マスクのパターン面に500μm以内に近接し、か
つ該パターン面に平行に移動可能の遮光板を備え
たことを特徴とするチツプパターン縮小投影露光
装置。
A projection light source, a support frame that supports a reticle mask with a pattern surface on a side farther from the light source, and an optical system that reduces and projects a chip pattern on the pattern surface onto a wafer, the pattern surface of the reticle mask A chip pattern reduction projection exposure apparatus characterized by comprising a light shielding plate that is close to the pattern surface within 500 μm and is movable parallel to the pattern surface.
JP1985136481U 1985-09-06 1985-09-06 Expired JPH0322904Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985136481U JPH0322904Y2 (en) 1985-09-06 1985-09-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985136481U JPH0322904Y2 (en) 1985-09-06 1985-09-06

Publications (2)

Publication Number Publication Date
JPS62104440U JPS62104440U (en) 1987-07-03
JPH0322904Y2 true JPH0322904Y2 (en) 1991-05-20

Family

ID=31039635

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985136481U Expired JPH0322904Y2 (en) 1985-09-06 1985-09-06

Country Status (1)

Country Link
JP (1) JPH0322904Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2688816B2 (en) * 1987-09-01 1997-12-10 三菱電機株式会社 Matrix-type display device manufacturing method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55132039A (en) * 1979-04-02 1980-10-14 Mitsubishi Electric Corp Forming method for repeated figure
JPS55140838A (en) * 1979-04-23 1980-11-04 Hitachi Ltd Mask preparing apparatus
JPS55165629A (en) * 1979-06-11 1980-12-24 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS58419B2 (en) * 1971-04-14 1983-01-06 チバ・ガイギ− アクチエンゲゼルシヤフト Method for producing bishydantoin compounds

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58419U (en) * 1981-06-25 1983-01-05 富士通株式会社 reticle

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58419B2 (en) * 1971-04-14 1983-01-06 チバ・ガイギ− アクチエンゲゼルシヤフト Method for producing bishydantoin compounds
JPS55132039A (en) * 1979-04-02 1980-10-14 Mitsubishi Electric Corp Forming method for repeated figure
JPS55140838A (en) * 1979-04-23 1980-11-04 Hitachi Ltd Mask preparing apparatus
JPS55165629A (en) * 1979-06-11 1980-12-24 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS62104440U (en) 1987-07-03

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