JPH03226852A - Data processor - Google Patents

Abstract

PURPOSE: To accelerate a data processing by executing a diagnostic test parallelly in plural storage cards through a shared interface. CONSTITUTION: An information processing network system 16 is provided with two processors 18 and 20 for respectively executing an operation to data, generating commands and relating data and performing transfer to a main memory unit and from the main memory unit and an arbitration link 22 joins the two processors 18 and 20. Also, an interface connects the processors 18 and 20 to the main memory unit provided with the plural storage cards 24, 26 and 28. Then, the processors 18 and 20 start the parallel, that is simultaneous, diagnostic test in the plural storage cards 24, 26 and 28 through the shared interface. Thus, the data processing is accelerated.

Description

DETAILED DESCRIPTION OF THE INVENTION A. INDUSTRIAL APPLICATION The present invention relates to an information handling system including a multiprocessing device linked to a plurality of storage cards of a main storage device via a shared interface, and inter alia: The present invention relates to a means for performing processor-initiated diagnostic functions in memory while minimizing traffic at the interface.

B. Prior Art and Problems In recent years, the performance of information processing devices has been considerably improved, particularly with regard to increasing the speed of data processing.

Increasingly, information processing networks employ multiple processing devices that share a common interface for transmitting data between a processor and a main memory, usually consisting of multiple storage cards. The current trend is toward larger main storage devices that use more of these storage cards. Improvements in storage subsystems have not kept pace with improvements in processors. This becomes especially apparent when using multiple parallel processors in an information processing network.

Accordingly, modifications have been made to system or network architectures to compensate for main memory being relatively slow operating compared to processing units.

Attempts have been made to separate the processor from the main memory storage card using cache memory and other techniques.

When a computer system is turned on, it is not always ready for use, but rather undergoes a final preparation known as an initial program load (IPL). In addition to installing an initial program into the computer system, this procedure will involve final testing of the computer Φ system, including diagnostic testing of the memory array in main memory.

The memory array is comprised of individual storage locations or cells, each capable of storing a bit representing either a logic one or a logic zero. The diagnostic test seeks to ensure that the cells can accurately store logic 1s and logic 0s, respectively, and that no paired cells are shorted together.

In information processing networks that utilize multiple processors and multiple storage cards that make up the main memory, traditional approaches to memory diagnostic testing utilize one or more processors to test predetermined data patterns and
It generates data storage commands identifying particular sections of the memory array and sends them to main memory via an interface. The data pattern is written to a selected section of the memory array and later read and returned to the processor by a fetch command issued by the processor.

The retrieved data pattern is compared to the original pattern to verify proper functionality of the section of the memory array.

Of course, since all memory arrays must be tested, main memory interfacing can be quite time consuming and requires significant processor overhead.

In fact, memory diagnostic tests typically consume 90-95% of the rPL hardware Φ test time. This problem is caused in part by the number of independent data patterns required to test memory integrity, but the essential factor is the processor and interface required to access the memory. Over
It's in the head.

The processor under test must access the storage cards sequentially, without any overlap, so
This problem increases in proportion to the number of storage cards forming the main storage device.

Among recent improvements in memory testing techniques are self-test storage devices. For example, US Pat. No. 4,1187,330 (Kumagal) discloses a self-diagnostic circuit for detecting defects formed on the same chip as the memory array. dataφ
The data to be stored in the array is also applied to the self-diagnostic circuit, which subsequently reads the data from the memory array and performs a data comparison in the self-diagnostic circuit. In U.S. Pat. No. 4,757,503 (Hayes et al.), a test generator formed on an integrated circuit of a random Create a sequence of patterns. The data in each column of one storage array is compared to the data in the corresponding column of the other storage array, and if there is a mismatch, an error signal is generated.

No. 4,782,48e (Lipcon et al.) discloses a self-test memory in which a central processing unit writes test patterns to all memory instruction banks simultaneously through conventional shared storage control logic. It has been disclosed.

Next, for each memory board, the contents of the reference 0 memory bank are compared to the contents of corresponding locations in the remaining memories and banks.

Although these approaches have been found to be satisfactory under certain conditions, they do not address the need for rapid diagnostic testing of multiple storage cards in networks where such cards interact with multiple processors via a shared interface. It is not possible. Furthermore, since they need to compare different arrays with each other or the logic for each chip, the cost is
This can be prohibitive for multi-chip storage cards.

C0 SUMMARY OF THE INVENTION AND SOLUTION It is an object of the present invention to provide an information processing network in which processing devices can initiate parallel or simultaneous diagnostic tests on multiple storage cards via a shared interface.

Another object of the present invention is to reduce the number of times a processor (or card 9 tester) must access a memory array during manufacturing testing and initial program load testing. The aim is to shorten the time required for these tests.

Another object is to provide an information processing network in which diagnostic tests initiated by processors of a memory array can proceed without delays or interruptions due to traffic in the memory or asynchronous memory reclamation operations.

To achieve the above and other purposes, bit O
an arrangement for manipulating coded data; a memory having a memory array for storing bit-encoded data; and a memory coupled to the processing arrangement and the memory for transmitting bit-encoded data between the processing arrangement and the memory. A process is provided for diagnostic testing of a memory array performed in a data processing system comprising a transmitting interface. This process involves using processing arrangement 2 to generate a compare command to store the bit-encoded data and address information corresponding to the selected location in the memory array; generating a data conflict pattern to be stored in a selected location;
and transmitting the data pattern to the memory, in response to the command and address information, storing the data pattern in a first register of the memory, writing the data pattern to the selected location in the memory array, and selecting the data pattern. Load data into the second register of memory from the first and second registers.
includes the step of comparing the data in the registers.

If the data in the first and second registers are the same,
The integrity of the array is checked. Differences between the data in these registers will identify errors.

Preferably, the data processing system includes multiple processing units and the memory includes multiple storage cards, with the processing units and cards sharing a common main storage interface. At least one of the processing units includes conventional logic processing circuitry for providing storage commands for storing data in the memory array and retrieval commands for retrieving data from the memory array.
Logic circuitry is included to generate a 'compare' command and send the compare command through the interface to the storage card for diagnostic testing of the storage card.

Each of the storage cards includes a holding register for holding a predetermined data session pattern provided by the processing unit along with a comparison command. Additionally, each storage card includes logic circuitry that writes a data pattern to a specified location in the memory array identified by the compare command.

The data pattern is further read from the memory array into the storage card's readback register, and the contents of the readback register are compared with the contents of the holding register. If there is no match, an error message is sent to the processor via the interface.

Compared to diagnostic tests according to conventional approaches that are managed by a processor, tests according to the present invention require a significant reduction in time. Primarily by performing diagnostic tests within main memory.
Each processor is freed up to perform other tasks for approximately the entire time required to test the memory array. These other tasks may also include initiating other diagnostic tests associated with other cards of the multiple storage cards. The number of cycles required to test each memory location or cell decreases with the time occupied by the interface between the processor and the storage card. Once each of the storage cards receives the comparison command and the accompanying data Φ pattern, the storage cards
Since it is used to implement disconnection test functionality, there is no disruption or other performance degradation due to interface traffic or asynchronous memory reclamation operations.

D. Embodiments Referring now to the drawings, FIG. 1 depicts an information processing network 1B for storing and performing selected operations on bitsha coded data. The system includes circuitry 18 and 18, respectively, for performing operations on data and generating instructions and associated data to cause transfers to and from main memory. Two processing units identified at 20 are included. The arbitration link 22 is
It combines two processing units and is used in conjunction with arbitration logic resident in both processing units to assign priority to either processor in connection with access to the interface. It is clear that the arrangement of processing units in this network can be constituted by a single processing unit or by multiple processing units provided with multiple arbitration links for point-to-point connection of all processing units.

The interface connects the processing unit to a main memory including multiple storage cards such as those shown at 24.26.28. For example, the storage card 24 includes a buffer 30, a holding register 32, a memory array 34 for storing bit number encoded data, a compare register 36, and a status register 3.
8 and a logic circuit element B-40 including a comparison circuit. Data stored in the memory array is also loaded into a holding register 32 and a compare register 36 for comparison with data later read from the memory array using comparison circuitry.

Storage card 26 is similar to storage card 24 and includes a buffer 42, a holding register 44, a memory array 46, a compare register 48, a status register 50 . It also includes a logic circuit element 52 including a comparison circuit. Similarly, the storage card 28 includes a buffer 54, a holding register 56, a memory Φ
array 58, comparison register 6o1 status register 62,
and a logic circuit element 64. These components are substantially identical to their counterparts in storage card 24 and perform similar functions. Of course, main storage can be comprised of any number of storage cards, such as storage cards 24.2B and 28.

The interfaces linking the processor and storage cards include a data bus 66 and a command/address bus 7, which are coupled to all of the processing units and storage cards and transmit data in parallel with other buses 7, respectively.
8 and a communication bus 7o. The data bus 6B carries what may be conveniently called working information, ie information of most immediate interest to the users of the system. Command/address bus 68 provides control information related to commands to retrieve, store, or otherwise perform specific operations, and currently stores or stores data. Address information is transmitted, including a byte-aligned starting address and the address length in the required number of bits.

Communication bus 70 is utilized to send status information from one of the storage cards to one of the processing units, while simultaneously sending work information to the processing unit via the data bus. The communication bus 70 is also used by the storage card to inform the processing unit that the storage card requires service, i.e., is subject to an internal error top condition, etc.

-18= Communication lines 72, 74 and 6 allow the storage card to send status information to the communication bus 70 and, via one of the communication lines 78 and 80, to a suitable processing device. . Context information is sent in only one direction, from one of the storage cards to one of the processing devices.

Command lines 82 and 84 send command and address information to bus 68, from where information is sent by communication lines 86, 88 and 90 to the appropriate storage card. The transfer of commands is unidirectional (processor to storage card), and the arrows at each end of command lines 82 and 84 indicate that each processing unit indicates the address of access to the remaining processing units during the transmission of the command. This indicates that it is possible to inform about the byte length.

Data lines 92 and 9 between processor and bus 66
4 and the data lines 9B, 98, and 100 between the storage card and the data bus accommodate the transmission of working information in both directions. The interface is also used to control the data bus 66. Data paths not shown in FIG. 111 are included. For further explanation of the interface, see 1.
Filed December 40, 989, and assigned to the assignee of this application, ``Hlgh Performa, nce''
Shared Maln Storage Inter
See US patent application Ser. No. 445,320 entitled ``face''.

Clock oscillator +02 is processing unit ■820,
And, a timing signal is applied to the storage cards 24-, 2B, and 28. The timing signal is composed of individual timing conflict pulses that occur at a predetermined timing frequency and form a uniform lock cycle.

When the information handling system is turned on, the hardware is tested and a predetermined initial program is loaded into the memory array prior to input from a prospective user. This procedure, known as the initial program load (IPL), includes a diagnostic test of the memory array.

Of course, to ensure user satisfaction, the hardware, including the memory array, must be tested to fully verify its reliability, and in the shortest possible time. ,
It is desirable to complete the initial program O load. As previously mentioned, diagnostic testing of memory arrays requires up to 95% of the time required to test hardware.

The current trend toward larger main storage capacities, whether through the addition of additional storage cards, larger storage cards, or both, is changing the approach to testing memory arrays. This will increase the need to improve.

In accordance with the present invention, testing of memory arrays is more effectively performed by migrating certain control logic from the processing unit to the storage card. A conventional processor-controlled approach to diagnostic testing is illustrated in the timing diagram of FIG. The processor issues a storage command in the first cycle in preparation for transferring the data pattern to the selected storage card in clock cycle two. A data fist pattern is a predetermined series of logical 1s designed to test the integrity of a memory array.
and logic O. The selected storage card begins accessing its memory array in the second clock cycle.

That is, access to the memory array is provided by two control lines, a row address strobe (RAS) and a column address strobe (cAS). The row address strobe initiates access to the data array by going active at the beginning of the second clock conflict cycle, while the column address strobe goes active at the start of the fourth clock cycle. become a state. When CAS is activated, data write patterns are written to selected locations in the array. The row address strobe and column address strobe then become inactive.

In connection with FIGS. 2 and 3, it is desirable to note that as a matter of harmony with other lines, N RAS and CAS are elevated when activated. In reality, RAS and CAS are 3'negatively active'' and therefore become active when their levels are low.

2 In cycle 7, the processor issues a repeat command. The row address strobe and column address strobe become active again in cycles 8 and 9, respectively. In cycle 10, data is read from the array and cycle! At I, it is transferred to the processor. The captured data is compared with the original data in clock Φ cycle 12.

FIG. 3 illustrates a diagnostic test for a memory array according to the present invention. The initial steps (up to step 5) performed on one of the storage cards 24 are similar to the step-by-step approach of traditional approaches, with the key difference being that the processing unit (e.g., processor 1) As previously mentioned, in clock cycle 4, a data pattern is written to a selected location in a memory array (e.g., the memory array of storage card 34). On the one hand, in cycle 4, the data pattern is written to the holding register 32. In the eighth clock cycle, 23- this data pattern is read back and written to the comparison register 3.
Sent to 6. In the next cycle, the contents of the compare register and the contents of the holding register are compared by the logic circuitry. If the comparison results in no difference between the contents of registers 32 and 36, then the integrity of the array is verified with respect to data pattern and selected location. On the other hand, in response to a difference in any of the bit positions, an error condition is stored in status register 38 and an error message is applied to processor 18 via communication bus 70.

The timing diagram of FIG. 3 is based on a predetermined data pattern written to a single location in the memory array. In fact, the logic circuitry resident on each storage card (40.52, Ei4, respectively) makes it possible to simultaneously write data patterns to multiple locations across multiple chips of its associated storage card. This is a feature that dramatically reduces the time required to test memory arrays.

Therefore, the circuitry resident on the storage card will slightly increase the testing speed of the 24 memory array. However, the above examples assume in each case that the processors do not need time to compete for the use of the interface, so the efficiency is increased beyond this comparison. In a multiprocessor configuration where multiple processors share a common interface used for memory array diagnostic testing, each included processor:
It must compete with other processors to utilize the main memory interface. For a conventional test number sequence (FIG. 2), the processor processes the data twice: once to store the data pattern on the storage card, and once to retrieve the data from the array.
interface must be accessed. In contrast, processor 18 can test the array with only one access to the main memory interface.

Therefore, the diagnostic test of a memory array according to the present invention requires only half the interface usage, ie, one cycle to issue a comparison command, whereas the conventional sequence would require two clocks. Another advantage is that cycle interface usage is required. For example, when the processing device 18 issues a comparison command to one of the storage cards, the processing device
It is freed up for other activities to occur, including issuing a comparison command to one of the other memory cards. Therefore, it is possible to simultaneously test multiple memory arrays of multiple storage cards.

Another advantage is that the memory array is normally in an inactive state and in order to be in a charging state, i.e.
This arises from the fact that a certain number of clock cycles are required before data is ready to be read from or written to the memory array. Of course, the number of cycles required will vary depending on the nature of the array and the cycle time, but in any case it will increase the time required to access the array. In a traditional test sequence, memory = 26
- It is necessary to access the content array to first store data in the memory array and later retrieve the data from the memory array when the row address strobe and column address strobe become inactive. become. On the other hand, if the comparison function is performed on the storage card,
There is no need to reactivate the row address conflict strobe to control activation of the memory array.

Another advantage compared to traditional sequences is that
This means that asynchronous events such as memory reclamation do not interfere with diagnostic testing of the storage card. Such events can delay conventional testing, especially if they occur between a store command and a retrieval command. Thus, an information processing network according to the present invention in which storage cards in main memory test a memory array in response to commands from a processing unit reduces the time and interface utilization required for testing. Become.

7 E9 Effects of the Invention As described in section 2, according to the present invention, it is possible to execute diagnostic tests in parallel on a plurality of storage cards, and speeding up of data processing is achieved.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of an information processing network in which multiple processing devices are associated via a shared interface with a main storage device that includes multiple storage cards. FIG. 2 is a timing diagram depicting conventional testing of a memory urn array during an initial program load. FIG. 3 is a timing diagram similar to FIG. 2 depicting testing of a memory array in accordance with the present invention. 16... Information processing network 18. 20... Processing device, 22... Arbitration link 24
．． 26.28...Multiple storage card 30...Buffer, 32...Holding register 34...Memory array,
36... Comparison register 8 38... Status register, 42... Buffer, 4B... Memory array, 50... Status register, 54... Buffer 58... Memory array, 62. ...Status register, 66...Data bus 68...Command/address 70...Communication bus 72.74.76.78. 82.84... Directive 92.94.9Et, 98. 102...Clock excellent 80...Communication line, 8B, 88. 100...Data oscillator. 40...Logic circuit element 44...Holding register 48...Comparison register 52...Logic circuit element 56...Holding register 60...Comparison register 84...Logic circuit element/basin 90...・Communication Raikai Line

Claims (9)

[Claims] (1) at least one that operates on bit-encoded data;
a processing unit, a memory having a memory array for storing bit-encoded data, and an interface coupled to the processing arrangement and the memory for transmitting the bit-encoded data between the processing arrangement and the memory. , a comparison command, and means for generating address data corresponding to a selected location of the data array in which the data is to be stored; means in the processing arrangement for transmitting the data pattern; first intermediate data holding means for receiving the data pattern from the processing arrangement; and second intermediate data holding means, wherein the data pattern is stored in the memory. data manipulation means in the memory for testing the integrity of the data pattern after it has been stored in the array; write data at the selected position, read the data at the selected position into the second intermediate data holding means, and write the data at the selected position into the first intermediate data holding means and the second intermediate data holding means.
a bit-coded data processing system comprising: means for comparing the data in the intermediate data holding means of the second holding means and displaying an error if the data in the second holding means is not the same as the data in the first holding means; (2) the memory includes a plurality of storage cards each having a data array, a holding register for receiving a data pattern from one of the processing units, and a comparison circuit for comparing the contents of the holding register and the comparison register; 2. The system of claim 1, wherein the holding register and the comparison register form first and second intermediate data holding means, respectively. (3) the interface includes a data bus for transmitting data patterns and a command/address bus for transmitting comparison commands and address information;
System according to claim 2, characterized in that the bus and the command/address bus are shared by the processing arrangement and all storage cards. (4) each of said storage cards includes a status register, and said means responsive to a comparison command registers an error in the status register if the data in the first and second holding means are not the same; System according to claim 3, characterized in that it displays. (5) the interface further includes a communication bus for transmitting an error indication in the associated one of the status registers from the associated storage card to the processing arrangement, and the communication bus is connected to the processing arrangement; System according to claim 4, characterized in that it is shared by all storage cards. (6) at least one that manipulates bit-encoded data;
a processor, a memory each having a plurality of memory arrays for storing bit-encoded data, and an interface connected to the processing arrangement and the memory for transmitting the bit-encoded data between the processing arrangement and the memory; A data processing system comprising: (a) utilizing a processor to generate a comparison instruction and address information corresponding to a selected location in a first memory array; (b) sending the command and address information to the memory via the interface; (c) sending the data pattern to the memory via the interface; (d) sending the command and address information to the memory via the interface; Responsive to the address information, storing the data pattern in the first register, storing the data pattern in the selected location of the array while simultaneously maintaining a record of the data pattern in the first register, and storing the data pattern in the first register; (e) performing at least a portion of step (d), subsequent to storing to the array, reading data from the selected location and comparing the data contained in the first register with the data read from the array; At the same time, steps (a)-- for another memory array
(d); and a process for testing a plurality of memory arrays. (7) The method further includes the step of generating an error indication if the data contained in the second register is not the same as the data contained in the first register after comparing the data. 7. The process of claim 6. (8) The steps of storing the data pattern in the first register and array, loading the data into the second register, and comparing the data are all performed in memory-resident logic circuitry; 8. Process according to claim 7, characterized in: 9. The step of generating an error indication includes generating an error indication in a status register of a memory and transmitting the error indication to a processing arrangement via an interface. The process described in.