JPH03226809A - Constant-voltage circuit - Google Patents
Constant-voltage circuitInfo
- Publication number
- JPH03226809A JPH03226809A JP2021575A JP2157590A JPH03226809A JP H03226809 A JPH03226809 A JP H03226809A JP 2021575 A JP2021575 A JP 2021575A JP 2157590 A JP2157590 A JP 2157590A JP H03226809 A JPH03226809 A JP H03226809A
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- Prior art keywords
- voltage
- circuit
- transistor
- constant
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Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は定電圧回路に係り、特にPN接合素子を利用し
て低電圧の出力電圧を一定レベルに保持する定電圧回路
に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a constant voltage circuit, and more particularly to a constant voltage circuit that uses a PN junction element to maintain a low output voltage at a constant level.
従来の技術
低い電圧で安定した基準電圧として使用できる出力電圧
を得る定電圧回路としてPN接合を利用したバンドギャ
ップツェナーが知られている。2. Description of the Related Art A bandgap Zener using a PN junction is known as a constant voltage circuit that obtains an output voltage that can be used as a stable reference voltage at a low voltage.
従来のバンドギャップツェナーを用いた定電圧回路には
第5図に示すような構成のものがあった。A conventional constant voltage circuit using a bandgap Zener has a configuration as shown in FIG.
入力端子1と端子3との間に電源l不接続され入力端子
1は定電流源4を介して出力端f2と接続される。出力
端子4と端子3との門に抵抗R+。A power source l is disconnected between input terminal 1 and terminal 3, and input terminal 1 is connected to output terminal f2 via constant current source 4. Resistor R+ at the gate between output terminal 4 and terminal 3.
R2、R3,PN接合を構成するNPNトランジスタQ
1よりなる直列回路5.差動増幅器6.制御用素子であ
るNPN1〜ランジスタQ2が接続される。R2, R3, NPN transistor Q forming the PN junction
A series circuit consisting of 15. Differential amplifier6. NPN1 to transistor Q2, which are control elements, are connected.
直列回路5の抵抗R1どR2との接続点は差動増幅器6
の入力となるトランジスタQ3のベースに接続され、直
列回路5の抵抗R2とR3との接続点は抵抗R4を介し
て力と差動増幅器6のもう一方の入力となるトランジス
タQ4のベースと接続される。差動増幅器6の出力は制
御用素子であるトランジスタQ2のベースと接続され、
差動増幅器6の出力に応じて出力電圧Vcを一定となる
ように制御する。The connection point between the resistors R1 and R2 of the series circuit 5 is the differential amplifier 6.
The connection point between the resistors R2 and R3 of the series circuit 5 is connected to the base of the transistor Q4 which becomes the other input of the differential amplifier 6 via the resistor R4. Ru. The output of the differential amplifier 6 is connected to the base of a transistor Q2, which is a control element.
The output voltage Vc is controlled to be constant according to the output of the differential amplifier 6.
このとき、トランジスタQ1のベース−エミッタ間電圧
VBEはトランジスタの直流電流増幅率hFEに対して
第7図に示すような変動を示す。At this time, the base-emitter voltage VBE of the transistor Q1 exhibits a variation as shown in FIG. 7 with respect to the DC current amplification factor hFE of the transistor.
このため、通常であれば出力電圧Vcもこれに応じて第
6図に破線で示すような特性となってしまう。Therefore, normally, the output voltage Vc would also have characteristics as shown by the broken line in FIG. 6 accordingly.
第5図に示寸回路では補正用の抵抗R4を挿入すること
により、VBEのhFEによる変シJを補正して出力電
圧Vcの特性を第6図に一点鎖線で示すような特性にし
て出力電圧Vcの変動を小さくしていICQ
直列回路5に流れる電流を1+、抵抗R2の両端の電圧
をΔVBEとすると、
Vc = (R1+R2+R3> ・△VBE/R2十
VBE
ここで差動増幅器6のトランジスタQ3 、 Q4のエ
ミッタ間の電圧を△■BEO,トランジスタQ4のベー
スに流れ込む電流をTB4とすると、△VBE、=(△
VBE〇−R4i4B)となり、したがって、
Vc、=(△VB EO−R4i4B >(R1+R2
+R3)/R2+Vs E
ここで、トランジスタQ4 、Qsのエミッタ電流の和
を■2.トランジスタQ4の直流電流増幅率をhFE<
とすると、
B 4 = I2 /2hFE4
となる。In the sizing circuit shown in Fig. 5, by inserting a correction resistor R4, the change in VBE due to hFE is corrected, and the characteristics of the output voltage Vc are changed to the characteristics shown by the dashed line in Fig. 6. If the current flowing through the ICQ series circuit 5 is 1+ and the voltage across the resistor R2 is ΔVBE by reducing the fluctuation of the voltage Vc, then Vc = (R1+R2+R3> ・ΔVBE/R20VBE Here, the transistor Q3 of the differential amplifier 6 , If the voltage between the emitter of Q4 is △■BEO, and the current flowing into the base of transistor Q4 is TB4, then △VBE, = (△
VBE〇-R4i4B), therefore, Vc, = (△VB EO-R4i4B > (R1+R2
+R3)/R2+Vs E Here, the sum of the emitter currents of transistors Q4 and Qs is 2. Let the DC current amplification factor of transistor Q4 be hFE<
Then, B 4 = I2 /2hFE4.
このため、Vc’=(△VBEO−R4I2/2、hr
: E 4 ) (R1+R2+R3) /R2→−
BE
と表わせる。Therefore, Vc'=(△VBEO-R4I2/2, hr
: E 4 ) (R1+R2+R3) /R2→-
It can be expressed as BE.
VBEはhFEにより第7図に示すように変動する。上
式を見ると第1項にhFE4が含まれている。ここでh
FE4はVBEと正負の関係が逆の項で、しかb、分子
に含まれているためhFE4の小さい部分でVcの補正
に効くことがわかる。VBE varies depending on hFE as shown in FIG. Looking at the above equation, hFE4 is included in the first term. Here h
Since FE4 is a term with an opposite positive/negative relationship to VBE and is included in the numerator, it can be seen that a small portion of hFE4 is effective in correcting Vc.
発明が解決しようとする課題
しかるに、従来の定電圧回路ではPN接合素子の電圧V
BEが変動した場合、差動増幅器6の入力に設けた抵抗
R4によって補正しており、その補正の特性は第5図に
一点鎖線で示ずように直流電流増幅率hFEが小さい領
域に対しては有効となるがhFEの大きい領域では効果
がなくなり、逆にhFEの大ぎい領域で補正を有効にき
かせるとhFEの小さい領域で効果がなくなるため、P
N接合素子の電圧の変動の補正がせまい範囲でしか行な
えない等の問題点があった。Problems to be Solved by the Invention However, in the conventional constant voltage circuit, the voltage V of the PN junction element
When BE fluctuates, it is corrected by the resistor R4 installed at the input of the differential amplifier 6, and the characteristics of the correction are as shown by the dashed line in Fig. 5 in the region where the DC current amplification factor hFE is small. is effective, but becomes ineffective in areas where hFE is large, and conversely, if correction is applied effectively in areas where hFE is large, it becomes ineffective in areas where hFE is small, so P
There have been problems such as correction of voltage fluctuations of the N-junction element can only be made within a narrow range.
本発明は上記の点に鑑みてなされたもので広い範囲で安
定した出力電圧が得られる定電圧回路を提供することを
目的とする。The present invention has been made in view of the above points, and an object of the present invention is to provide a constant voltage circuit that can obtain a stable output voltage over a wide range.
課題を解決するための手段
本発明はPN接合素子と少なくとも2つの抵抗とよりな
る直列回路の両端に出力電圧の全部又は一部を印加し、
2つの抵抗のうち一方の抵抗の両端の電圧を差動増幅器
の2つの入力端子間に印加し、差動増幅器の差動出力に
より出力電圧を一定に制御する定電圧回路において、前
記PN接合素子の電圧変動に応じて前記直列回路への印
加電圧を前記出力電圧が一定になるように補正する補正
回路を具備してなる。Means for Solving the Problems The present invention applies all or part of the output voltage to both ends of a series circuit consisting of a PN junction element and at least two resistors,
In a constant voltage circuit in which a voltage across one of two resistors is applied between two input terminals of a differential amplifier, and the output voltage is controlled to be constant by the differential output of the differential amplifier, the PN junction element A correction circuit is provided for correcting the voltage applied to the series circuit in accordance with voltage fluctuations so that the output voltage becomes constant.
作用
基準となるPN接合素子の電圧が変動しても補正回路に
よりその変動に応じて直列回路への供給電流が補正され
、出力電圧は一定に保持される、。Even if the voltage of the PN junction element, which serves as a reference for operation, fluctuates, the correction circuit corrects the current supplied to the series circuit in accordance with the fluctuation, and the output voltage is held constant.
実施例
第1図は本発明の第1の実施例の回路図を示す1゜端子
1.3間には入力電圧が印加され、端子2゜3より出力
定電圧Vcが取り出される。端子1は定電流源4を介し
て端子2に接続される。Embodiment FIG. 1 shows a circuit diagram of a first embodiment of the present invention. An input voltage is applied between 1° terminals 1 and 3, and an output constant voltage Vc is taken out from terminals 2° and 3. Terminal 1 is connected to terminal 2 via constant current source 4 .
端子2と端子3との間には直列回路5.差動増幅器6.
制御回路7.制御素子となるPNP1〜ランジスタQ2
が互いに並列に接続される。直列回路5はPN接合素子
を構成するNPNI〜ランジスタQ+、抵抗R+ 、R
2、R3、R5、R6よりなり、NPN1〜ランジスタ
Q+のエミッタを端子3に接続し、NPNトランジスタ
Q1の]レクタど端子2どの間に抵抗R+ 、R2、R
3、Rs 。A series circuit 5 is connected between terminal 2 and terminal 3. Differential amplifier6.
Control circuit 7. PNP1 to transistor Q2 as control elements
are connected in parallel with each other. The series circuit 5 includes NPNI to transistor Q+, resistor R+, and R, which constitute a PN junction element.
2, R3, R5, and R6, the emitters of NPN1 to transistor Q+ are connected to terminal 3, and resistors R+, R2, and R are connected between the [rector of NPN transistor Q1 and terminal 2].
3. Rs.
R6を端子2の側から抵抗Rs 、R+ 、R2R3,
R6の順で直列に接続してなる。NPNトランジスタQ
1のベースは抵抗R3と抵抗R6との接続点に接続され
、ベースエミッタ間でPN接合を構成する。Connect R6 from the terminal 2 side with resistors Rs, R+, R2R3,
They are connected in series in the order of R6. NPN transistor Q
The base of the resistor 1 is connected to the connection point between the resistor R3 and the resistor R6, and a PN junction is formed between the base and emitter.
抵抗R2の端子2側の一端は差動増幅器6の入力端子と
なるNPNI−ランジスタQ3のベースに接続され、抵
抗R2のPN接合素子側の一端は差動増幅器6の入力端
子となるNPNI−ンランジスタQ4のベースに特性補
正用抵抗R4を介して接続される。One end of the resistor R2 on the terminal 2 side is connected to the base of the NPNI transistor Q3 which becomes the input terminal of the differential amplifier 6, and one end of the resistor R2 on the PN junction element side is connected to the base of the NPNI transistor Q3 which becomes the input terminal of the differential amplifier 6. It is connected to the base of Q4 via a characteristic correction resistor R4.
制御素子であるPNPIヘランジスタQ2はコレクタが
端子2に接続され、エミッタが端子3に接続され、その
ベースに差動増幅器6の出力が入力され、端子2,3間
の電圧を制御する。A PNPI helanistor Q2, which is a control element, has its collector connected to terminal 2, its emitter connected to terminal 3, and the output of the differential amplifier 6 inputted to its base, thereby controlling the voltage between terminals 2 and 3.
制御回路7は検出用NPN+−ランジスタQs。The control circuit 7 is a detection NPN+- transistor Qs.
カレントミラー回路8.制」用NPNトランジスタQ6
よりなる。検出用NPNトランジスタQ5のベースは直
列回路5のPN接合素子であるトランジスタQ1のコレ
クタに接続され、1〜ランジスタQ5の]レクタはカレ
ン1〜ミラ一回路8に接続される。制御用N P N
l−ランジスタQ6のベースはカレントミラー回路8に
接続され、コレクタは直列回路5の抵抗R5と抵抗R1
との接続点に接続される。Current mirror circuit8. NPN transistor Q6 for
It becomes more. The base of the detection NPN transistor Q5 is connected to the collector of the transistor Q1, which is a PN junction element of the series circuit 5, and the collectors of the transistors Q1 to Q5 are connected to the current circuits 8. Control N P N
The base of the l-transistor Q6 is connected to the current mirror circuit 8, and the collector is connected to the resistor R5 and the resistor R1 of the series circuit 5.
connected to the connection point.
ここで、端子2.3間の出力電圧をVc、抵抗R+ 1
.R2,R3、Rs 、 トランジスタQ1を流れる
電流を1+、トランジスタQ1のベース−エミッタ間電
圧をVe E 、差動増幅器6を構成するトランジスタ
Q3 、Q4のエミッタ電流の和をI2.トランジスタ
Q4のベース電流をIB4゜トランジスタQ3.Q4の
エミッタ間の電圧の差をΔVe E O、抵抗R2の両
端の電圧をΔVBE。Here, the output voltage between terminals 2 and 3 is Vc, and the resistance R+1
.. R2, R3, Rs, the current flowing through the transistor Q1 is 1+, the base-emitter voltage of the transistor Q1 is Ve E, and the sum of the emitter currents of the transistors Q3 and Q4 forming the differential amplifier 6 is I2. The base current of transistor Q4 is changed to IB4°transistor Q3. The voltage difference between the emitters of Q4 is ΔVe E O, and the voltage across resistor R2 is ΔVBE.
トランジスタQ1とトランジスタQ5との電流比をn+
、カレントミラー回路8の入力出力電流比をn2と覆る
と、
Vc = (R1+R2+R3+R5) It +Rs
11’ −1−VB E
(1)ρ
■1−△VBE/R2(2)
ま ノ〔、△VBE −△V[3EO−R41B4
(3)となるため、11−(△Vs EO−R4
184)/ R2(4)
さらに、It ’ =1+ ’hFE6 /n+ n
26)
hFE6はトランジスタQ6の直流電流増幅率である。The current ratio between transistor Q1 and transistor Q5 is n+
, when the input-output current ratio of the current mirror circuit 8 is replaced by n2, Vc = (R1+R2+R3+R5) It +Rs
11'-1-VB E
(1) ρ ■1-△VBE/R2 (2) Mano[, △VBE -△V[3EO-R41B4
(3), so 11-(△Vs EO-R4
184)/R2(4) Furthermore, It' = 1+'hFE6/n+n
26) hFE6 is the DC current amplification factor of transistor Q6.
したがって、Vc=
(△Ve E 0−R4Is 4 >、 (R1+R2
@−R3+ R5) / R2+ R5・I】 ・hF
E6/n+n2+VsE ’
(5)ここで、1〜ランジスタQ4の直流電流増幅率を
hFE4とすると、
Is 4 = 12 /2hF R4(7)よって
、Vc=
(△Ve E O−’R4・12 /2hFE4 )(
R1+R2+R3+R5)/R2+R5I+ 0hr
Es /n+ n2 +Vs E (8)VB
Eは直流電流増幅率hFEの変動に対して第7図に示す
ように変動することが知られており、式(8)に示すよ
うに第1項にはhFE4第2項にはhFE6が現われて
おり、hFEが変動してVBEが変動してもこれに伴っ
て、hFE4゜hFE6が変動し、VBEの変動分を補
うことにより出力電圧Vcを一定に保持している。Therefore, Vc= (△Ve E 0−R4Is 4 >, (R1+R2
@-R3+ R5) / R2+ R5・I] ・hF
E6/n+n2+VsE'
(5) Here, if the DC current amplification factor of 1 to transistor Q4 is hFE4, then Is 4 = 12 /2hF R4 (7) Therefore, Vc = (△Ve E O-'R4・12 /2hFE4 ) (
R1+R2+R3+R5)/R2+R5I+ 0hr
Es /n+ n2 +Vs E (8)VB
It is known that E changes as shown in Figure 7 in response to changes in the DC current amplification factor hFE, and as shown in equation (8), hFE6 appears in the first term and hFE6 appears in the second term. Therefore, even if hFE fluctuates and VBE fluctuates, hFE4° hFE6 fluctuate accordingly, and the output voltage Vc is held constant by compensating for the fluctuation in VBE.
制御回路7は第2項にかかわってバラリ、従来の抵抗R
4による補正(第6図−点鎖線)で十分でないhFEの
高い部分での補正が行なえる。したがって、hFEの変
動に対する出力電圧Vcの特性は第6図に実線で示すよ
うになり、hFEの変動によらず常に一定の出力電圧を
得ることができる。The control circuit 7 is related to the second term and is variable, so the conventional resistance R
4 (FIG. 6 - dot-dashed line) can correct the portions where hFE is high. Therefore, the characteristics of the output voltage Vc with respect to changes in hFE are as shown by the solid line in FIG. 6, and a constant output voltage can always be obtained regardless of changes in hFE.
第2図は本発明の第2の実施例の回路図を示す。FIG. 2 shows a circuit diagram of a second embodiment of the invention.
第1図と同一構成部分には同一符号をイ」シ、その説明
は省略する。本実施例は第1の実施例における抵抗R5
、Rsを抵抗R+ 、R3とで共用した構成で、第1の
実施例に比し、部品点数を減らすことができる。Components that are the same as those in FIG. 1 are designated by the same reference numerals, and their explanations will be omitted. This example is the resistor R5 in the first example.
, Rs are shared by the resistors R+ and R3, and the number of parts can be reduced compared to the first embodiment.
第3図は本発明の第3の実施例の回路図を示す。FIG. 3 shows a circuit diagram of a third embodiment of the invention.
第1図、第2図と同−禍成部分には同−右号を何し、そ
の説明は省略する。本実施例は補正回路7を制御用素子
である1ヘランジスタQ7と検出回路9とで構成したも
ので、1〜ランジスタQ7のコレクタを抵抗R+ 、’
R2との接続点に接続してなり、端子2,3間の電圧を
検出回路9により検出して、トランジスタQ7を制御し
て、直流回路5の供給電流を制御している。The same numbers as those in FIGS. 1 and 2 are used for the same parts, and the explanation thereof will be omitted. In this embodiment, the correction circuit 7 is composed of a 1-transistor transistor Q7, which is a control element, and a detection circuit 9. The collectors of the transistors 1 to Q7 are connected to resistors R+,'
The detection circuit 9 detects the voltage between the terminals 2 and 3, controls the transistor Q7, and controls the current supplied to the DC circuit 5.
第4図は本発明の第3の実施例の回路図である。FIG. 4 is a circuit diagram of a third embodiment of the present invention.
図中、第1図、第2図、第3図と同一構成部分には同一
符号を付し、その説明は省略する。In the drawings, the same components as in FIGS. 1, 2, and 3 are designated by the same reference numerals, and their explanations will be omitted.
本実施例は端子3とトランジスタQ2のエミッタとの接
続点を抵抗R7を介してトランジスタQ1のエミッタと
接続した構成とする。補正回路7は定電流?l!10及
び1〜ランジスタQ8で構成して、トランジスタQ8の
エミッタをトランジスタQ1のエミッタと抵抗R7との
接続点に接続し、トランジスタQ8のベースに定電流源
10を接続してなる。In this embodiment, the connection point between the terminal 3 and the emitter of the transistor Q2 is connected to the emitter of the transistor Q1 via a resistor R7. Is the correction circuit 7 a constant current? l! The emitter of the transistor Q8 is connected to the connection point between the emitter of the transistor Q1 and the resistor R7, and the constant current source 10 is connected to the base of the transistor Q8.
トランジスタQ8は直列回路5の電圧が変動しても1−
ランジスタQ1のエミッタと抵抗R7との1
接続点に一定の電流を供給し、出力電圧Vcを一定に保
持する。Transistor Q8 remains 1- even if the voltage of series circuit 5 fluctuates.
A constant current is supplied to one connection point between the emitter of the transistor Q1 and the resistor R7, and the output voltage Vc is held constant.
なお、回路は上記の実施例に限ることはなく、トランジ
スタの極性を変えた構成のものも考えられる。Note that the circuit is not limited to the above embodiment, and a structure in which the polarity of the transistors is changed may also be considered.
発明の効果
上述の如く、本発明によればPN接合素子の印加電圧変
動に応じて直列回路に流れる電流を補正する補正回路を
設けることによりPN接合素fの印加電圧の変動による
出力電圧の変動を補正できるため、出力電圧の変動を少
なくでき、安定した出力電圧が得られる等の特長を有す
る。Effects of the Invention As described above, according to the present invention, by providing a correction circuit that corrects the current flowing through the series circuit in accordance with changes in the voltage applied to the PN junction element, fluctuations in the output voltage due to changes in the voltage applied to the PN junction element f can be suppressed. Since the output voltage can be corrected, fluctuations in the output voltage can be reduced and a stable output voltage can be obtained.
第1図は本発明の第1の実施例の回路図、第2図は本発
明の第2の実施例の回路図、第3図は本発明の第3の実
施例の回路図、第4図は本発明の第4の実施例の回路図
、第5図は従来の一例の回路図、第6図は出力電圧特性
図、第7図はPN接合素子電圧特性図である。
5・・・直列回路、6・・・差動増幅器、7・・・補正
回路。
21 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, FIG. 3 is a circuit diagram of a third embodiment of the present invention, and FIG. FIG. 5 is a circuit diagram of a fourth embodiment of the present invention, FIG. 5 is a circuit diagram of a conventional example, FIG. 6 is an output voltage characteristic diagram, and FIG. 7 is a PN junction element voltage characteristic diagram. 5...Series circuit, 6...Differential amplifier, 7...Correction circuit. 2
Claims (1)
路の両端に出力電圧の全部又は一部を印加し、該2つの
抵抗のうち一方の抵抗の両端の電圧を差動増幅器の2つ
の入力端子間に印加し、該差動増幅器の差動出力により
該出力電圧を一定に制御する定電圧回路において、 前記PN接合素子の電圧変動に応じて前記直列回路に流
れる電流を前記出力電圧が一定になるように補正する補
正回路を具備したことを特徴とする定電圧回路。[Claims] All or part of the output voltage is applied to both ends of a series circuit consisting of a PN junction element and at least two resistors, and the voltage across one of the two resistors is applied to a differential amplifier. in a constant voltage circuit that controls the output voltage to be constant by the differential output of the differential amplifier, the current flowing through the series circuit depending on the voltage fluctuation of the PN junction element is applied between the two input terminals of the differential amplifier. A constant voltage circuit characterized by comprising a correction circuit that corrects the output voltage to be constant.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2157590A JP2754824B2 (en) | 1990-01-31 | 1990-01-31 | Constant voltage circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2157590A JP2754824B2 (en) | 1990-01-31 | 1990-01-31 | Constant voltage circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH03226809A true JPH03226809A (en) | 1991-10-07 |
JP2754824B2 JP2754824B2 (en) | 1998-05-20 |
Family
ID=12058832
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2157590A Expired - Lifetime JP2754824B2 (en) | 1990-01-31 | 1990-01-31 | Constant voltage circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2754824B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013191095A (en) * | 2012-03-14 | 2013-09-26 | Mitsumi Electric Co Ltd | Band gap reference circuit |
-
1990
- 1990-01-31 JP JP2157590A patent/JP2754824B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013191095A (en) * | 2012-03-14 | 2013-09-26 | Mitsumi Electric Co Ltd | Band gap reference circuit |
Also Published As
Publication number | Publication date |
---|---|
JP2754824B2 (en) | 1998-05-20 |
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