JPH0322610A - Synchronizing pulse generating circuit - Google Patents

Abstract

PURPOSE:To evade the detection of a synchronizing signal for a narrow pulse width such as noise by devising the circuit such that the circuit synchronizes with an input signal having a sufficiently wide frame pulse width, outputs the synchronizing signal and does not detect the synchronizing signal at a narrow pulse width. CONSTITUTION:A signal at a 1st input terminal 1 and a signal at a 2nd input terminal are inputted to a 1st latch circuit 5, an output signal of the latch circuit 5 and a signal of the input terminal 2 are inputted to a 2nd latch circuit 6, an output signal of the latch circuit 6 and an output signal of the latch circuit 5 and a signal at the input terminal 2 are inputted to a logic circuit 7, and the 1st and 2nd outputs of the logic circuit 7 are used as the signal of the 1st and 2nd output terminals 3, 4. That is, a data D input of the latch circuit 15 is supplied to the input terminal 11 and the clock C input is supplied to the input terminal 12 respectively, two inputs to a NOR 16 are given to the 1st output Q1 and the 3rd output Q3 of the latch circuit 15 and the output of the NOR 16 is connected to one input of the AND 17, the input terminal 12 is connected to the other input and the output of the NOR 16 is connected to the output terminal 13 and the output of the AND 17 is connected to the output terminal 14, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization pulse generation circuit, and particularly to a synchronization pulse generation circuit that is less sensitive to narrow pulses caused by noise or the like.

[Conventional technology]

Conventionally, as this type of synchronous pulse generation circuit, there has been a circuit as shown in FIG. 4, for example. In FIG. 4, it is composed of a latch circuit 34 and a two-man power NOR 35, and has a first input terminal 31, a second input terminal 32, and an output terminal 33.
It has

The latch circuit 34, ie, the D-type flip-flop, has a D-type input connected to the first input terminal 31, a clock input connected to the second input terminal 32, and a Q output connected to the single input terminal of the NoR 35.

An example of this latch circuit 340 is a circuit as shown in FIG. 5(a) or FIG. 7.

In Fig. 7, the input terminal 61 is the D input, and the input terminal 62 is the D input.
There is a flip-flop 65 which has a C input, a signal via an inverter 64 as a CB input, and an output terminal 63 as a Q output.

In FIG. 5(a), a flip-flop 412>1 having D input, C input, and CB manual Q output is shown, and its specific circuit is as shown in FIG. 5(b). Input terminals 42, 43, and 44 are D input and C input, respectively. C.B.
input, output terminal 45 as Q output, inverter 48
, 49, 50, P, N channel MOS} transistor 46
．． It has 47.

Next, regarding the operation of the circuit shown in Fig. 4, see Fig. 10 (
As shown in a), for example, a signal with a long period (hereinafter referred to as a frame pulse) is input to the l-th input terminal 3l, and the second
By inputting a signal with a short period (hereinafter referred to as a clock pulse) to the input terminal 32 of , the output terminal 33K can obtain an output signal synchronized with the frame pulse and the lock pulse.

1. As shown in FIG. 10(b), the first input terminal 3l
When a narrow pulse width generated by noise or the like is input to the output terminal 3 3 K, the same '4i pulse waveform as the input terminal 31 is outputted.

[Problems to be Solved by the Invention] The conventional synchronous pulse generation circuit described above generates an output equivalent to a narrow pulse width in synchronization with narrow pulse widths generated by noise, etc., causing internal circuits to malfunction. There were drawbacks.

An object of the present invention is to provide a synchronization pulse that can output a synchronization signal in synchronization with an input signal having a sufficiently wide frame pulse width, and prevent the synchronization signal from being detected in response to a narrow pulse width such as noise. The purpose of this invention is to provide a generating circuit.

[Means to solve the problem]

The configuration of the present invention is as follows. A second input signal causes the first input signal and the second input signal to be input to a first latch circuit in accordance with a homogeneous pulse generation circuit that detects synchronization. and the second input signal are input to a second latch circuit, and the output signal of the second latch circuit, the output signal of the first latch circuit, and the input signal of the second is input to a logic circuit, and the first and second outputs of the logic circuit are used as first and second output terminals.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit block diagram showing a synchronization pulse generation circuit of the present invention.

As shown in FIG. 1, the configuration of the present invention uses a synchronization pulse circuit that detects synchronization between two input signals to output the signal at the first input terminal 1 and the signal at the second input terminal 2 to the second input terminal 2. The output signal of the first latch circuit 5 and the signal of the second input terminal 2 are input to the second latch circuit 6, and the output signal of the second latch circuit 6 and the signal of the second input terminal 2 are input to the second latch circuit 6. The output signal of the latch circuit 5 of Jl and the signal of the second input terminal 2 are input to the logic circuit 7, and the first output and the second output of the logic circuit 7 are input to the first and second output terminals 3. , 4 signals.

FIG. 2 is a circuit diagram showing a synchronizing pulse generating circuit according to a first embodiment of the present invention. In the vg2 diagram, latch circuit 15
The data (D) of human power is connected to the input terminal 11, the clock (C) input is connected to the input terminal 12, and the two inputs of the two-power NOR 16 are connected to the first output Q1 and the third output of the latch circuit 15. Q3, connect the output of the two-man power NOR16 to one of the two-man power AND17, connect the input terminal 12 to the other input, connect the output of the two-man power NOR16 to the output terminal 13, and the output of the two-man power AND17. They are connected to the output terminals 14, respectively.

Here, regarding the latch circuit l5, for example, FIG.
) and a circuit as shown in FIG.

That is, the circuit 15 has the circuit block configuration shown in FIG. 6, and the flip-flops 57, 58, and 59 in FIG. 6 have the circuit configuration shown in FIG. 5(b). Flip●Flops 57, 58i59 are connected in cascade in three stages, input terminal 51 is D input, input terminal 52 is C input, output terminal 55 is Q3 output, terminal 53 is Q1 output, terminal 54 is Q2 output, and >B , the signal via the inverter 56 is used as the CB input.

Next, the operation will be explained using FIG. 8(a) and FIG. 8(b).

In FIG. 8(a), similarly to the conventional example, a frame pulse is input to the first input terminal l1 in FIG.
The input terminal l2 of the clock (C) valve, R. 'k input f. Here, the width of the low level of the frame pulse is assumed to be two clocks. This frame pulse is the latch circuit 15
Generates sQ1 output and Q3 output through 2-man power NO.
R16 and two output signals AND17Ki frame pulse and clock pulse K synchronization t can be obtained.

Further, in FIG. 8(b), a frame pulse and a clock pulse are inputted in the same manner as in FIG. 8(a). Here, the width of the low level of the frame pulse is assumed to be l clocks.

This frame pulse generates a Ql output and a Q3 output via the latch circuit 15, but the
The output of No. 17 does not change at the low level.

In this way, pulses synchronized with the frame pulse and the clock pulse can be detected at the output terminals 13 and 14.

Furthermore, if the width of the frame pulse is one clock or less, no pulse for detecting synchronization is generated, so waveforms with narrow pulse widths such as noise are not detected.

Next, a synchronization pulse generation circuit according to a second embodiment of the present invention will be explained.

FIG. 3 is a circuit diagram showing a synchronous pulse generating circuit according to a second embodiment of the present invention. In FIG. 3, the data input of the latch circuit 25 is connected to the input terminal 2l, the clock input is connected to the input terminal 22, and the two inputs of the two-manufactured NAND 26 are connected to the first output Q1 of the latch circuit 25 and the first output Q1 of the latch circuit 25. 3, and connect the input of the i/parter 28 to the input terminal 2.
2 and connect the 2-man power NA to one input of the 2-man power OR27.
Connect the output of ND26, and connect the inverter 2 to the other input.
The output of the two-man power NAND 26 is connected to the output terminal 23, and the output of the two-man power OR 27 is connected to the output terminal 24.

Here, the latch circuit 25 is constituted by a circuit as shown in FIG. 5(b) and FIG. 6, for example.

Next, the operation will be explained using FIG. 9(a) and FIG. 9(b). In FIG. 9(a), similarly to the first embodiment, a frame pulse is input to the first input terminal 21, and a clock pulse is input to the second input terminal 22. Here, the width of the high level of the frame pulse is assumed to be equal to the clock. This frame pulse generates the %Q1 output and Q3 output via the latch circuit 25, and the two-man NAND2
6, the two-man OR 27, and the imperter 28, it is possible to obtain an output signal synchronized with the frame pulse and the clock pulse.

Similarly to Fig. 9(a), as shown in Fig. 9(b),
Input frame pulse and clock pulse. here,
The width of the high level of the frame pulse is one clock. This frame pulse is passed through the latch circuit 25 to Q1
Output, Q, and output are generated, but 2-man power NAND26 and 2
The output of the human power OR2 7 remains at the high level 11 and does not change.

In this way, the output terminals 23 and 24 can detect the synchronization of the frame pulse and clock pulse. Moreover, if the width of the frame pulse is one clock or less, no pulse for detecting the cycle is generated, so a waveform with a narrow pulse width that is exclusively used for noise is not detected.

〔Effect of the invention〕

As explained above, the present invention has the advantage that a synchronization signal can be detected only in synchronization with an input signal having a sufficiently wide frame pulse width, and the synchronization signal is not detected in response to a narrow pulse width such as noise. There is.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the synchronous pulse generation circuit of the present invention, Figure 2 is a circuit diagram showing the first embodiment of the present invention, Figure 3 is a circuit diagram showing the @2 embodiment of the present invention, Figure 4 is a circuit diagram showing a conventional synchronous pulse generation circuit;
Figure (b) is a circuit block diagram showing a latch circuit,
Figure 6 is a circuit diagram showing a composite latch circuit in which latch circuits are connected in cascade, Figure 7 is a circuit diagram showing a latch circuit that takes clock input into consideration, and Figures 8(a) and 8(b) are from this page. FIGS. 9(a) and 9(b) are waveform diagrams showing the operation of the circuit according to the first embodiment of the invention, respectively. lO diagram (a), 1st
FIG. 0(b) is a waveform chart showing the operation of the conventional example. 1, 2.11, 12, 21, 22.31, 32.42,
43, 44, 51, 52, 61.62... Input terminal, 3, 4, 13, 14, 23, 24, 33
．． 45, 55. 63... Output terminal, 5, 6, 34... Latch circuit, 7...
・Logic circuit, 15, 25, 41, 57, 58, 59.6
5...Flip●Flop, 28, 48
, 49, 50, 56. 64...
Inverter, 17...2-man power AND, 26...
...2-person NAND, 27...2-person OR
, 16.35...2-person power NOR, 46.47.
...MOS} transistor.

Claims (1)

[Claims] In a synchronization pulse generation circuit that detects synchronization using first and second input signals, the first input signal and the second input signal are input to a first latch circuit, and the first latch circuit and the second input signal are input to a second latch circuit, and the output signal of the second latch circuit, the output signal of the first latch circuit, and the second input signal are logically combined. A synchronizing pulse generating circuit, characterized in that the first and second outputs of the logic circuit are used as first and second output terminals, respectively.