JPH03218039A - Mounting method of semiconductor element - Google Patents
Mounting method of semiconductor elementInfo
- Publication number
- JPH03218039A JPH03218039A JP2013417A JP1341790A JPH03218039A JP H03218039 A JPH03218039 A JP H03218039A JP 2013417 A JP2013417 A JP 2013417A JP 1341790 A JP1341790 A JP 1341790A JP H03218039 A JPH03218039 A JP H03218039A
- Authority
- JP
- Japan
- Prior art keywords
- bump electrodes
- semiconductor element
- electrode terminals
- mounting board
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 47
- 238000000034 method Methods 0.000 title claims description 9
- 230000000694 effects Effects 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/8114—Guiding structures outside the body
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ＩＣチップ等の半導体素子の表面に突出して
形成されたバンプ電極を実装基板上の電極端子に直接接
続（フェースダウンボンデイング）して半導体素子を実
装基板上に実装する方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is a method for directly connecting bump electrodes formed protruding from the surface of a semiconductor element such as an IC chip to electrode terminals on a mounting board (face-down bonding). The present invention relates to a method for mounting a semiconductor element on a mounting board.
ＩＣチップ等の半導体素子を実装基板上に実装する場合
に、半導体素子の電極パッド上に凸状のバンプ電極を形
成し、このバンプ電極を実装基板上に形成されている電
極端子上に直接接続することが行われている。When mounting a semiconductor element such as an IC chip on a mounting board, a convex bump electrode is formed on the electrode pad of the semiconductor element, and this bump electrode is directly connected to the electrode terminal formed on the mounting board. things are being done.
実装基板上の電極端子は、従来、平坦に形成されていた
。このため、半導体素子上のバンプ電極を実装基板上の
電極端子に正確に位置合せしなければ、バンプ電極材料
や予備ハンダが電極端子の周辺部にはみ出し、隣接する
電極端子同士を短絡させるおそれがあった。Conventionally, electrode terminals on a mounting board have been formed flat. For this reason, if the bump electrodes on the semiconductor element are not accurately aligned with the electrode terminals on the mounting board, there is a risk that the bump electrode material or preliminary solder will protrude around the electrode terminals, causing a short circuit between adjacent electrode terminals. there were.
また、半導体素子の集積度が高くなるほど、実装基板上
に形成される電極端子のサイズ及びピッチ間隔は小さく
なる。このため、高集積化が進むほどバンプ電極と電極
端子とを非常に高い精度で位置合せする必要が生ずる。Furthermore, the higher the degree of integration of semiconductor elements, the smaller the size and pitch of the electrode terminals formed on the mounting substrate. Therefore, as the degree of integration increases, it becomes necessary to align bump electrodes and electrode terminals with extremely high precision.
しかし、そのような高い精度での位置合せには、それな
りの時間が必要であり、実装に要する時間が長くなると
共に、高精度で高価な位置合せ装置を必要とする。この
ため、実装コストが高いものとなっていた。However, alignment with such high precision requires a certain amount of time, increases the time required for implementation, and requires a highly accurate and expensive alignment device. For this reason, the implementation cost has been high.
そこで、上述の事情に鑑み、本発明は実装に要する時間
を短縮し、実装コストを低減すると共に、半導体素子の
電子回路に接続されるバンプ電極及び電極端子の信頼性
を向上させることを目的としている。Therefore, in view of the above circumstances, the present invention aims to shorten the time required for mounting, reduce mounting costs, and improve the reliability of bump electrodes and electrode terminals connected to the electronic circuit of a semiconductor element. There is.
上述の目的を達成するため、本発明による半導体素子の
実装方法においては、半導体素子上の一部のバンプ電極
をその他のバンプ電極よりも高く形成すると共に、この
一部のバンプ電極の頂部を受容する凹部をこれらのバン
プ電極に対応して実装基板上に形成されている一部の電
極端子に形成しておき、この凹部に一部のバンプ電極の
頂部を挿入することにより半導体素子を実装基板に対し
て位置合せし、半導体素子を実装基板に対して実装する
こととしている。In order to achieve the above object, in the semiconductor device mounting method according to the present invention, some bump electrodes on the semiconductor device are formed higher than other bump electrodes, and the tops of the some bump electrodes are Recesses are formed in some of the electrode terminals formed on the mounting board to correspond to these bump electrodes, and by inserting the tops of some of the bump electrodes into these recesses, the semiconductor element is mounted on the mounting board. The semiconductor element is then mounted on the mounting board.
このようにすることにより、一部のバンプ電極の項部か
一部の電極端子に形成されている凹部からはみ出さない
程度の大まかな位置合せをした後に、半導体素子を実装
基板に対して軽く押し付けるだけで、半導体素子上のバ
ンプ電極が実装基板上の電極端子に対して高精度に位置
合せされる。By doing this, after roughly aligning the bump electrodes so that they do not protrude from the recesses formed in some of the electrode terminals, the semiconductor element can be placed lightly against the mounting board. By simply pressing, the bump electrodes on the semiconductor element are aligned with the electrode terminals on the mounting board with high precision.
また、この位置合せに関与する一部のバンプ電極の高さ
が他のバンプ電極よりも高くなっているので、位置合せ
が完了するまでの間に互いに接触するバンプ電極と電極
端子の数が少なくなる。Also, because the height of some bump electrodes involved in this alignment is higher than other bump electrodes, the number of bump electrodes and electrode terminals that come into contact with each other until alignment is completed is reduced. Become.
また、上述の位置合せに関与する一部のバンプ電極をそ
の密集度が疎な部分から選べば、上述した位置合せが完
了するまでの間に互いに接触するバンプ電極と電極端子
の数がさらに減少する。In addition, if some of the bump electrodes involved in the above-mentioned alignment are selected from areas where they are less dense, the number of bump electrodes and electrode terminals that come into contact with each other until the above-mentioned alignment is completed can be further reduced. do.
また、上述した位置合せに関与する一部のバンプ電極及
び電極端子を、半導体素子の電子回路に接続されない位
置合せ専用のバンプ電極及び電極端子とすることにより
、半導体素子の電子回路に接続され該電子回路との電気
信号等の授受に関与する全てのバンプ電極及び電極端子
は、その位置合せが完了するときまで相互に接触しなく
なり、その損傷が防止される。In addition, by making some of the bump electrodes and electrode terminals involved in the alignment described above into alignment-only bump electrodes and electrode terminals that are not connected to the electronic circuit of the semiconductor element, it is possible to connect the bump electrodes and electrode terminals to the electronic circuit of the semiconductor element. All the bump electrodes and electrode terminals involved in transmitting and receiving electrical signals and the like to and from the electronic circuit do not come into contact with each other until their alignment is completed, and damage to them is prevented.
なお、一部の電極端子に凹部を形成する代わりに、一部
のバンプ電極の頂部をそれぞれ受容する凹部を実装基板
に形成し、この凹部内に一部の電極端子を形成しておく
こととしてもよい。Note that instead of forming recesses in some of the electrode terminals, recesses that receive the tops of some of the bump electrodes are formed on the mounting board, and some of the electrode terminals are formed in these recesses. Good too.
以下、本発明の実施例について第１図〜第３図を参照し
つつ、説明する。Embodiments of the present invention will be described below with reference to FIGS. 1 to 3.
第１図は本発明が適用される実装基板とその電極端子に
対して大まかに位置合せされた半導体素子とを示してお
り、第２図はそれらの実装後の状態を示している。FIG. 1 shows a mounting board to which the present invention is applied and a semiconductor element roughly aligned with its electrode terminals, and FIG. 2 shows their state after mounting.
図示したように、半導体素子１にはその表面から突出し
て複数のバンプ電極２ａ、２ｂが形成されている。そし
て、一部のバンプ電極２ａの高さはそれ以外のバンプ電
極２ｂよりも高くなっており、バンプ電極２ａはその他
のバンプ電極２ｂよりも半導体素子１表面からの突出量
が大きくなっている。As illustrated, a plurality of bump electrodes 2a and 2b are formed on the semiconductor element 1, protruding from the surface thereof. The height of some of the bump electrodes 2a is higher than the other bump electrodes 2b, and the bump electrodes 2a protrude more from the surface of the semiconductor element 1 than the other bump electrodes 2b.
他方、半導体素子１が実装される実装基板３には、半導
体素子１上のバンプ２ ａ ｓ ２ ｂに対応して複数
の電極端子５ａ，５ｂが形成されている。On the other hand, a plurality of electrode terminals 5a and 5b are formed on the mounting substrate 3 on which the semiconductor element 1 is mounted, corresponding to the bumps 2a s 2b on the semiconductor element 1.
そして、一部の電極端子２ａに対応して形成されている
電極端子５ａには、その表面にバンプ２ａの少なくとも
頂部を受容する凹部４が形成されている。この凹部４は
外周部から中心部に向かって徐々に深くなるように形成
されており、該中心部が最も深くなっている。The electrode terminals 5a formed corresponding to some of the electrode terminals 2a have recesses 4 formed on their surfaces to receive at least the tops of the bumps 2a. The recess 4 is formed so as to become gradually deeper from the outer periphery toward the center, and is deepest at the center.
このような凹部４を有する電極端子５ａは、例えば次の
ようにして形成される。まず、実装基板３の電極端子５
ａが形成される部分に窪みを形成する。この窪みは半導
体素子１上に形成されているバンプ２の少なくとも頂部
（図では下端部）を受容し得る程度の大きさに形成され
る。そして、この窪みに選択的に金属メッキや真空蒸着
等を施して電極端子５ａが形成される。このようにして
形成された電極端子５ａは、その表面にバンプ電極２ａ
の少なくとも頂部を受容する凹部４を有することとなる
。The electrode terminal 5a having such a recess 4 is formed, for example, as follows. First, the electrode terminal 5 of the mounting board 3
A depression is formed in the portion where a is formed. This depression is formed in a size large enough to receive at least the top (lower end in the figure) of the bump 2 formed on the semiconductor element 1. Then, electrode terminals 5a are formed by selectively applying metal plating, vacuum deposition, etc. to these depressions. The electrode terminal 5a thus formed has a bump electrode 2a on its surface.
It has a recess 4 for receiving at least the top of the.
このように形成された実装基板３に対して、半導体素子
１を実装する場合、半導体素子１上のバンプ電極２ａ、
２ｂと実装基板３上の電極端子５ａ％ ５ｂとの位置合
せが図示しない位置合せ装置により行われるが、この位
置合せは、第１図に示したように、バンプ電極２ａの頂
部が電極端子５ａの凹部４内からはみ出さない程度の大
まかな位置合せで足りる。なぜなら、バンプ電極２ａの
頂部が電極端子５ａの凹部４内に納まる範囲内に位置合
せされていれば、この位置合せの後に半導体素子１を実
装基板３に対して軽く押し付けることにより、バンプ電
極２ａは電極端子５ａの凹部４の表面に沿って案内され
、凹部４の中心部に向かって自動的に移動するからであ
る。そして、第２図に示したように、一部のバンプ電極
２ａが電極端子５ａの中央部に位置合せされると同時に
、その他のバンプ電極２ｂが対応する電極端子５ｂに当
接する。この場合、実装基板３に最初に当接したバンプ
電極２ａは実装基板３に接したままその上を摺動ずる。When mounting the semiconductor element 1 on the mounting board 3 formed in this way, the bump electrodes 2a on the semiconductor element 1,
2b and the electrode terminal 5a on the mounting board 3 is performed by an alignment device (not shown). As shown in FIG. It is sufficient to roughly align the position so that it does not protrude from the inside of the recess 4. This is because if the top of the bump electrode 2a is aligned within the range that fits within the recess 4 of the electrode terminal 5a, then by lightly pressing the semiconductor element 1 against the mounting board 3 after this alignment, the bump electrode 2a This is because the electrode terminal 5a is guided along the surface of the recess 4 and automatically moves toward the center of the recess 4. Then, as shown in FIG. 2, some of the bump electrodes 2a are aligned with the center portions of the electrode terminals 5a, and at the same time, other bump electrodes 2b abut on the corresponding electrode terminals 5b. In this case, the bump electrode 2a that first came into contact with the mounting board 3 slides on the mounting board 3 while remaining in contact with it.
したがって、電極端子５ ａ ｓ５ｂを含め実装基板３
上に形成されている配線パターンにバンプ電極２ａは接
触し、この接触により該配線パターンは損傷を受けるこ
とになる。このように、配線パターンがバンプ電極との
接触により受ける損傷を少なくするため、本発明におい
ては、一部のバンプ電極２ａをその他のバンプ電極２ｂ
よりも半導体素子１の表面から突出させることとしてい
る。このようにすることにより、全てのバンプ電極を同
じ高さで形成した場合に比べ、位置合せが完了するまで
の間に配線パターンに接触するバンプ電極の数を減らす
ことができ、この接触によりバンプ電極及び配線パター
ンが受ける損傷を減らすことができる。したがって、バ
ンプ電極２ａ、２ｂ及び電極端子５ａ、５ｂの信頼性を
全体的に向上させることができると共に、実装の歩留ま
りを向上させることができる。Therefore, the mounting board 3 including the electrode terminals 5a and 5b
The bump electrode 2a comes into contact with the wiring pattern formed above, and this contact damages the wiring pattern. In this way, in order to reduce damage to the wiring pattern due to contact with bump electrodes, in the present invention, some bump electrodes 2a are replaced with other bump electrodes 2b.
It is made to protrude from the surface of the semiconductor element 1 more than the surface of the semiconductor element 1. By doing this, compared to the case where all bump electrodes are formed at the same height, it is possible to reduce the number of bump electrodes that come into contact with the wiring pattern until alignment is completed, and this contact makes it possible to reduce the number of bump electrodes that contact the wiring pattern. Damage to the electrodes and wiring patterns can be reduced. Therefore, the reliability of the bump electrodes 2a, 2b and the electrode terminals 5a, 5b can be improved overall, and the mounting yield can be improved.
なお、他のバンプ電極２ｂよりも高く形成される一部の
バンプ電極２ａを、第３図に示したように半導体素子１
の四隅等のバンプ電極の密集度が疎な部分から選ぶこと
とすれば、バンプ電極２ａが実装基板３上に形成される
配線パターンと接触する頻度を更に減らすことができる
。Note that some of the bump electrodes 2a formed higher than other bump electrodes 2b are placed on the semiconductor element 1 as shown in FIG.
If bump electrodes are selected from areas where the density of bump electrodes is sparse, such as the four corners of , it is possible to further reduce the frequency with which the bump electrodes 2a come into contact with the wiring pattern formed on the mounting board 3.
また、本発明においては、一部のバンプ電極２ａに対応
して実装基板３上に形成される一部の電極端子５ａのみ
に、バンプ電極２ａの頂部を受容する凹部４を形成して
いる。このように、凹部４が形成される電極端子を一部
のものに限定することにより、全ての電極端子を実装基
板の窪みに形成する場合に比べ、該窪みに形成される電
極端子の数を減らすことができる。電極端子を含め実装
基板上に形成される配線パターンは、実装基板上の窪み
等の段差部上に形成される箇所で断線が生じやすいが、
上述のように実装基板３の窪みに形成される電極端子５
ａの数が制限されることにより、配線パターンの断線危
険箇所が減少する。Further, in the present invention, the recesses 4 for receiving the tops of the bump electrodes 2a are formed only in some of the electrode terminals 5a formed on the mounting board 3 corresponding to some of the bump electrodes 2a. In this way, by limiting the number of electrode terminals in which the recesses 4 are formed to some, the number of electrode terminals formed in the recesses can be reduced compared to the case where all the electrode terminals are formed in the recesses of the mounting board. can be reduced. The wiring pattern formed on the mounting board, including electrode terminals, is prone to breakage at locations formed on stepped parts such as recesses on the mounting board.
The electrode terminal 5 formed in the recess of the mounting board 3 as described above
By limiting the number of a, the number of potential disconnection points in the wiring pattern is reduced.
さらに、上述した位置合せに関与する一部のバンプ電極
２ａ及び電極端子５ａを、半導体素子３上に形成されて
いる電子回路に接続されない位置合せ専用のバンプ電極
及び電極端子として形成しておけば、半導体素子の電子
回路に接続され該電子回路への電気信号等の授受に関与
するその他のバンプ電極２ｂ及び電極端子５ｂは、その
位置合せが完了するときまで相互に接触しなくなり、接
触による損傷が防止される。また、半導体素子の電子回
路に接続される電極端子に凹部を形成する必要がなくな
るので、該電子回路への電気信号等の授受に関与する配
線パターンから、段差部に形成されているために断線が
生じる危険性のある箇所がなくなる。Furthermore, if some of the bump electrodes 2a and electrode terminals 5a involved in the above-mentioned alignment are formed as bump electrodes and electrode terminals exclusively for alignment that are not connected to the electronic circuit formed on the semiconductor element 3. The other bump electrodes 2b and electrode terminals 5b that are connected to the electronic circuit of the semiconductor element and are involved in sending and receiving electrical signals, etc. to the electronic circuit do not come into contact with each other until the alignment is completed, and damage due to contact occurs. is prevented. In addition, since there is no need to form a recess in the electrode terminal connected to the electronic circuit of the semiconductor element, there is no need to form a recess in the electrode terminal connected to the electronic circuit. There are no areas where there is a risk of damage occurring.
上述のようにして半導体素子１が実装基板３に対して位
置合せされた後、例えば、実装基板３が加熱されて電極
端子５ａ、５ｂに施された予備ハンダ（図示せず）がリ
フローされ、バンプ電極２ａ、２ｂとこれらに対応する
電極端子５ａ、５ｂとが相互に接続される。この場合、
リフローされた予備ハンダの表面張力がバンプ電極２
ａ ｓ２ｂ及び電極端子５ａ、５ｂの相互間に作用し、
この表面張力の作用により、一層正確な位置合せが自動
的に行われる。なお、予備ハンダが施されていない場合
であっても、加熱によりバンプ電極２ａ，２ｂを溶融さ
せれば同様の効果が得られる。After the semiconductor element 1 is aligned with the mounting board 3 as described above, for example, the mounting board 3 is heated and the preliminary solder (not shown) applied to the electrode terminals 5a and 5b is reflowed. Bump electrodes 2a, 2b and corresponding electrode terminals 5a, 5b are connected to each other. in this case,
The surface tension of the reflowed preliminary solder increases the bump electrode 2.
acting between a s2b and the electrode terminals 5a and 5b,
This surface tension effect automatically provides more accurate alignment. Note that even if preliminary soldering is not applied, the same effect can be obtained by melting the bump electrodes 2a, 2b by heating.
上述した実施例においては、一部のバンプ電極２ａの頂
部を受容する凹部４を実装基板上の電極端子５ａに形成
しているが、一部のバンプ電極２ａの頂部を受容する凹
部を実装基板３の表面に形成し、この凹部中央部にバン
プ電極２ａに対応して形成される電極端子を配すること
としても、上述した例と同様の作用・効果を得ることが
できる。In the embodiment described above, the recesses 4 that receive the tops of some of the bump electrodes 2a are formed in the electrode terminals 5a on the mounting board; 3, and an electrode terminal formed corresponding to the bump electrode 2a is disposed in the center of the recessed part, and the same operation and effect as in the above-mentioned example can be obtained.
以上説明したように、本発明によれば従来のように高精
度で高価な位置合せ装置を必要とせず、比較的安価な位
置合せ装置を用いることができる。As described above, according to the present invention, a relatively inexpensive alignment device can be used instead of requiring a highly accurate and expensive alignment device as in the prior art.
また、位置合せ装置による位置合せは、大まかなもので
足りるので、位置合せ装置による精密な位置合せを必要
としていた従来に比し、位置合せ装置による位置合せに
必要とされる時間が短くなる。Furthermore, since only rough alignment is required by the alignment device, the time required for alignment by the alignment device is shorter than in the past, which required precise alignment by the alignment device.
したがって、実装に要する時間及びコストを低減するこ
とができる。さらに、実装基板上に形成され半導体素子
の電子回路に接続される電極端子やバンプ電極の損傷を
低減できるので、電極端子やバンプ電極の信頼性が向上
し、高い信頼性をもって半導体素子を実装基板に実装で
きると共に、その歩留まりも向上する。Therefore, the time and cost required for implementation can be reduced. Furthermore, damage to the electrode terminals and bump electrodes formed on the mounting board and connected to the electronic circuit of the semiconductor element can be reduced, so the reliability of the electrode terminals and bump electrodes is improved, and the semiconductor element can be mounted on the mounting board with high reliability. It can be implemented in many ways, and the yield rate is also improved.
第１図は本発明が適用される実装基板とその電極端子に
対して大まかに位置合せされた半導体素子とを示した図
、第２図はそれらの実装後の状態を示した図、第３図は
半導体素子上のバンプ電極の配置を示した図である。
１・・・半導体素子、２ａ、２ｂ・・・バンプ電極、３
・・・実装基板、４・・・凹部、５ａ，５ｂ・・・電極
端子。FIG. 1 is a diagram showing a mounting board to which the present invention is applied and a semiconductor element roughly aligned with its electrode terminals, FIG. 2 is a diagram showing their state after mounting, and FIG. The figure shows the arrangement of bump electrodes on a semiconductor element. 1... Semiconductor element, 2a, 2b... Bump electrode, 3
... Mounting board, 4... Recessed part, 5a, 5b... Electrode terminal.
Claims (1)
ンプ電極を実装基板上の複数の電極端子に直接接続して
前記半導体素子を前記実装基板上に実装する方法であっ
て、 前記半導体素子上の一部のバンプ電極をその他のバンプ
電極よりも高く形成すると共に、この一部のバンプ電極
に対応して前記実装基板上に形成された一部の電極端子
に前記バンプ電極の頂部を受容する凹部を形成しておき
、 前記凹部に前記一部のバンプ電極の頂部を挿入すること
により前記半導体素子を前記実装基板に対して位置合せ
し、 前記半導体素子を前記実装基板に対して実装することを
特徴とする半導体素子の実装方法。 ２、前記一部のバンプ電極はその密集度が疎な部分から
選ばれることを特徴とする請求項１記載の半導体素子の
実装方法。 ３、前記一部のバンプ電極及び一部の電極端子はそれぞ
れ位置合せ専用のバンプ電極及び電極端子であることを
特徴とする請求項１又は２記載の半導体素子の実装方法
。 ４、前記一部の電極端子に前記凹部を形成しておく代わ
りに、前記一部のバンプ電極の頂部を受容すると共に、
前記一部の電極端子がそれぞれ中央部に配される凹部を
前記実装基板に形成しておくことを特徴とする請求項１
、２又は３記載の半導体素子の実装方法。[Scope of Claims] 1. A method of mounting the semiconductor element on the mounting board by directly connecting a plurality of bump electrodes formed protruding from the surface of the semiconductor element to a plurality of electrode terminals on the mounting board. Some bump electrodes on the semiconductor element are formed higher than other bump electrodes, and the bumps are formed on some electrode terminals formed on the mounting board corresponding to the some bump electrodes. A recess is formed to receive the top of the electrode, and the semiconductor element is aligned with the mounting board by inserting the top of the part of the bump electrode into the recess, and the semiconductor element is mounted on the mounting board. 1. A method for mounting a semiconductor device, characterized in that the device is mounted on a semiconductor device. 2. The method of mounting a semiconductor device according to claim 1, wherein the part of the bump electrodes is selected from a part where the density of the bump electrodes is sparse. 3. The semiconductor device mounting method according to claim 1 or 2, wherein the part of the bump electrodes and the part of the electrode terminals are bump electrodes and electrode terminals dedicated to positioning, respectively. 4. Instead of forming the recesses in the part of the electrode terminals, receiving the tops of the part of the bump electrodes,
Claim 1, wherein a recess is formed in the mounting board in which each of the electrode terminals is disposed in the center.
, 2 or 3. The method for mounting a semiconductor device according to .
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013417A JPH03218039A (en) | 1990-01-23 | 1990-01-23 | Mounting method of semiconductor element |
| AU69822/91A AU645283B2 (en) | 1990-01-23 | 1991-01-22 | Substrate for packaging a semiconductor device |
| CA002034703A CA2034703A1 (en) | 1990-01-23 | 1991-01-22 | Substrate for packaging a semiconductor device |
| US07/644,587 US5214308A (en) | 1990-01-23 | 1991-01-23 | Substrate for packaging a semiconductor device |
| KR91001104A KR950001365B1 (en) | 1990-01-23 | 1991-01-23 | Substrate for packaging a semiconductor device, packaging structure and method |
| EP91100818A EP0439134A2 (en) | 1990-01-23 | 1991-01-23 | Substrate for packaging a semiconductor device, packaging structure and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013417A JPH03218039A (en) | 1990-01-23 | 1990-01-23 | Mounting method of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03218039A true JPH03218039A (en) | 1991-09-25 |
Family
ID=11832560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013417A Pending JPH03218039A (en) | 1990-01-23 | 1990-01-23 | Mounting method of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03218039A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08330360A (en) * | 1995-05-31 | 1996-12-13 | Nec Corp | Semiconductor device and its manufacture |
| JP2006237280A (en) * | 2005-02-25 | 2006-09-07 | Sony Corp | Semiconductor device and its manufacturing method |
| US7307349B2 (en) | 1999-02-24 | 2007-12-11 | Rohm Co., Ltd. | Semiconductor device of chip-on-chip structure, assembling process therefor, and semiconductor chip to be bonded to solid surface |
| JP2008147317A (en) * | 2006-12-08 | 2008-06-26 | Matsushita Electric Ind Co Ltd | Electronic component mounting method |
| JP2011181953A (en) * | 2011-05-16 | 2011-09-15 | Fujitsu Ltd | Semiconductor device and method of manufacturing the same |
| JP2018107371A (en) * | 2016-12-28 | 2018-07-05 | 日亜化学工業株式会社 | Light-emitting device and manufacturing method thereof |
| WO2021251434A1 (en) * | 2020-06-10 | 2021-12-16 | 株式会社村田製作所 | Solid-state battery |
-
1990
- 1990-01-23 JP JP2013417A patent/JPH03218039A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08330360A (en) * | 1995-05-31 | 1996-12-13 | Nec Corp | Semiconductor device and its manufacture |
| US7307349B2 (en) | 1999-02-24 | 2007-12-11 | Rohm Co., Ltd. | Semiconductor device of chip-on-chip structure, assembling process therefor, and semiconductor chip to be bonded to solid surface |
| JP2006237280A (en) * | 2005-02-25 | 2006-09-07 | Sony Corp | Semiconductor device and its manufacturing method |
| JP2008147317A (en) * | 2006-12-08 | 2008-06-26 | Matsushita Electric Ind Co Ltd | Electronic component mounting method |
| JP2011181953A (en) * | 2011-05-16 | 2011-09-15 | Fujitsu Ltd | Semiconductor device and method of manufacturing the same |
| JP2018107371A (en) * | 2016-12-28 | 2018-07-05 | 日亜化学工業株式会社 | Light-emitting device and manufacturing method thereof |
| WO2021251434A1 (en) * | 2020-06-10 | 2021-12-16 | 株式会社村田製作所 | Solid-state battery |
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