JPH03209695A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce a power consumption by making a voltage control circuit which controls the voltage of an internal power source bus non-acting when the lowering of a power source voltage is detected and it is equal to or less than a threshold value set in advance and switching it so as to flow a current from a power source terminal to the internal power source bus directly. CONSTITUTION:When a voltage VCCE of an external power source terminal 1 is +4.5V, for instance, an IC acts. The IC is designed in this way and when the VCCE is +3.3 - +4V, the output voltage of a reference voltage generating circuit 2 becomes +3.3V and an active loading type differential amplifier 3 is a non-acting condition. Moreover, when the VCCE is lowered and becomes +3.3V or less, since an output from the circuit 2 is zero, the VCCE is impressed on an internal bus 6 directly and the IC is made a working condition. Thus, the power consumption of if the whole IC is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit device, and more particularly to an integrated circuit device incorporating a power supply circuit, particularly a voltage control circuit.

[Conventional technology]

Conventionally, this type of integrated circuit device uses a circuit that originally operates at low voltage, such as a static memory, at a standard power supply voltage, for example, 5V. It had built-in.

As integrated circuit devices such as memory devices become more highly integrated, the operating voltages of their constituent circuit elements are becoming increasingly lower, and therefore devices with built-in voltage control circuits of this type tend to be used more and more. .

A voltage control circuit is a circuit that adjusts and stabilizes the power supply voltage supplied from an external source to provide an appropriate operating voltage to circuit elements such as transistors that make up an integrated circuit. .

Referring to FIG. 4, the conventional voltage control circuit of this type is
An external power supply terminal 1, a reference voltage generation circuit 2, an active load type differential amplifier 3 loaded with a current mirror circuit, an output P-channel MOS transistor Q51, and a voltage-controlled power supply are connected to each internal circuit element. It consisted of an internal power supply bus 6.

In FIG. 4, the reference voltage generating circuit 2 includes a plurality of MOS transistors Q22 .
Q23 to Q2n are connected in series to serve as a reference voltage source, and between this and external power supply terminal 1, there is an M that operates as a constant current source.
This is a well-known type to which an OS transistor Q21 is connected. A connection point N1 between the two is connected to an active load type differential amplifier 3 whose load is a well-known current mirror circuit.

Active load type differential amplifier 3 includes N-channel MOS transistors Q31. One Q3 of the differential amplifier consisting of Q32
The drain current of P-channel MOS transistor Q34. The output current of the current mirror circuit and the train current of the other Q31 of the differential amplifier are supplied to the gate of Q51, which is a common load. Further, Q33 is a differential amplifier whose source resistance is an active constant current source.

Features include high gain, arbitrary setting of output voltage, and applicability to integrated circuits.

Next, the output P-channel MOS transistor Q51 has its source connected to the external power supply terminal 1 and its drain connected to the internal power supply bus 6, forming a well-known series regulator circuit. As described above, the drain output voltage of Q31 of the active load type differential amplifier 3 is applied to the gate, so this voltage controls the voltage VCC+ of the drain side, that is, the internal power supply bus 6. Further, this VCol is the Q of the other side of the active load type differential amplifier 3.
Added to 32 gates. Therefore, the output voltage vc
c l is the reference voltage v applied to the gate of Q31
It was to be compared with N1 and controlled as a whole to be at the same voltage.

[Problem to be solved by the invention]

In the conventional integrated circuit device described above, an operating current of about several mA always flows as a constant current required due to the operating principle of the differential amplifier, which is a main component of the built-in voltage control circuit. For this reason, the data retention current of memory devices and the like, which originally consume almost no current, has been increased. This was a major drawback, making it unsuitable for use in devices such as static memories, which are particularly characterized by low data retention currents.

Furthermore, the memory device and the like have a function of switching between an operating state and a standby state in response to a chip selection signal (C3) from a central processing unit (CPU) that controls the memory device. In this standby state, the voltage control circuit consumes several mA of operating current for the differential amplifier, which increases the current during standby, as described above.

[Means to solve the problem]

The integrated circuit device of the present invention includes an integrated circuit and a power supply circuit that supplies power to the integrated circuit, wherein the power supply circuit is connected to a first power supply that supplies power to the integrated circuit components. a voltage control means for adjusting an externally supplied voltage to a required voltage and supplying it to the power supply bus; and a voltage detecting means for detecting when the externally supplied voltage becomes equal to or less than a predetermined voltage threshold. and a switching means for disconnecting the voltage control means from the external power supply and switching to supply power directly from the external power supply to the power supply bus according to the detection result of the voltage detection means.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention. 1st
In the figure, the reference voltage generating circuit 2 includes a plurality of MOS transistors Q22, . Q23~Q2
This is a well-known device in which a MOS transistor Q21 which operates as a constant current source is connected between this and the external power supply terminal 1, which is connected in series to serve as a reference voltage source. The connection point N1 between the two is connected to an active load type differential amplifier 3 whose load is a current mirror circuit, and a voltage detection circuit 4 comprising a P-channel MOS transistor Q41 and an N-channel MOS transistor Q42.

The gates and drains of the MOS transistors Q41 and Q42 of the voltage detection circuit 4 are connected in common, the source of Q41 is connected to the external power supply terminal 1, and the source of Q42 is grounded.

Here, the design threshold voltage V of the P-channel MOS transistor such as Q41 is -0.7V. Also,
Q411) The gate channel width is much larger than that of Q42, for example, about 100 times. Its output terminal N2 is connected to the gate of an N-channel MOS transistor Q33, which is a source measurement current source of the active load type differential amplifier 3, and to the gates of P-channel MOS transistors Q52 and Q53 of the switch circuit 5.

The switch circuit 5 includes a P-channel MOS transistor whose source is connected to the external power supply terminal 1) and a transistor Q51. Q5
2. The output of the active load type differential amplifier 3 is connected to the gate of Q51. Also, Q51.
The drain of Q53 is connected to internal power supply bus 6.

Next, the operation of this embodiment will be explained.

In FIG. 1, the voltage V at external power supply terminal 1. The minimum value of CE, that is, the minimum operating voltage of this integrated circuit device is +4.5
V, the voltage of the internal power supply bus 6 of the integrated circuit device vcc I
is designed for +3.3v.

First, the case where VCCE is +4.5V or more will be explained.

Node N1 of reference voltage generation circuit 1 is a reference voltage output, and its voltage is +3 when VCCE is +4.5V or higher.
．． It is 3V. The output of node N1 is applied to the gate of Q31, which is the reference voltage input terminal of active load type differential amplifier 3. The active load type differential amplifier 3 is substantially similar to that described in the prior art section. Sunahachi, N
channel MOS) transistor Q31. The drain current of one Q32 of the differential amplifier consisting of Q32 is connected to a P-channel MOS transistor Q34. The input current of the current mirror circuit consisting of Q35 is used, and the output current of the current mirror circuit and the train current of the other Q31 of the differential amplifier are supplied to the gate of Q51, which is a common load.

Also, Q31. Q33 on the source side of Q32 uses the source resistance of a differential amplifier as an active constant current source. However, as mentioned above, the gate of Q3B is connected to the voltage detection circuit 4.
It is connected to node N2, which is the output terminal of , and is turned on and off by this signal.

The output P-channel MOS transistor Q51 has a source connected to the external power supply terminal 1 and a drain connected to the internal power supply bus 6. As described above, the drain output voltage of Q31 of the active load type differential amplifier 3 is applied to the gate, so this voltage controls the voltage VCCI on the drain side, that is, the internal power supply bus 6. Further, this VCCI is applied to the gate of the other one Q32 of the active load type differential amplifier. Therefore, the reference voltage applied to the gate of Q31 ■8. The voltage is compared with 3.3V, and the voltage is controlled as a whole so that the voltage is the same.

The voltage VNI at node N1 is also applied to Q41. It is input to the gate of Q42. At this time, if the external power supply voltage VCCE, the threshold voltage VT of Q41, and the voltage vNl at N1 satisfy the following relationship, Q41 is turned on.

VCCE V7 ≧vN1,', VCC4≧VNI + l Vt l...
・・・・・・・・・・・・・・・・・・・・・・・・
...1 Pass through the above, VNI = 3jV, l Vt
Since l =0.7V, Q41 is turned on if VCCE is 4V or more.

Here, VCCB is set to +4.5v or more, so
Q41 is naturally turned on.

Further, Q42, which is an N-channel MOS transistor, is turned on if the gate voltage is equal to or higher than its threshold voltage. In this case as well, if a general value of 0.7V is adopted, the gate voltage is VNI = 34V, which sufficiently exceeds the threshold voltage of Q42 and turns on.

Therefore, the MOS) transistor Q41 of the voltage detection circuit 4.
Both Q42 are turned on. By the way, as is well known, the drain current in the saturation region of a MOS transistor is proportional to the channel width of the gate. Furthermore, the train resistance is inversely proportional to the gate channel width. Therefore, Q41
The voltage at the drain side of both Q42 and node N2, which is the output terminal of the voltage detection circuit 4, is determined by the ratio of their drain saturation currents or the ratio of their resistances.

As mentioned above, the channel width of the gate of Q41 is
Since it is very large compared to that of 2, in this case, Q42
The influence of Vccε can be ignored, and it is almost determined only by Q41 that VCCε is approximately +4.5V. This is the high level output of the voltage detection circuit 4.

The output of the node N2, that is, the output of the voltage detection circuit 4, is first applied to the gate of the N-channel MOS transistor Q33, which is the source measurement current source of the active differential amplifier 3, to turn it on and to output the active load. The differential amplifier 3 is put into operation. At the same time, the P channel MO of switch circuit 5
8) Since it is also added to the gates of transistors Q52 and Q53, turn them off. The drain of Q52 is connected to the gate of the output P-channel MOS transistor Q51, and when Q52 is off, the voltage control operation of Q51 is not affected, so the voltage vccl of the internal power supply bus 6 is normal. It is maintained at +3.3■.

Next, external power supply voltage V. A case where CE decreases to +4v or less will be explained.

First, when VCCE is +3.3v or more, the output voltage of the reference voltage generation circuit 2, that is, the voltage of the node N1 is
It is maintained at +3jV. On the other hand, the P-channel MOS transistor Q41 of the voltage detection circuit 4 has a
Since the condition of the formula, VCCE≧VNI+l VT, is no longer satisfied, it is turned off. Furthermore, since the N-channel MOS transistor Q42 remains on,
The voltage at node N2 becomes the ground potential, that is, Ov. This is the low level output of the voltage detection circuit 4. As a result, first, the source constant current source Q33 of the active load type differential amplifier 3 is turned off, so that the active load type differential amplifier 3 becomes inoperative and no current flows. At the same time, Q52 of the switch circuit 5 is turned on, so vcct is applied to the gate of the output P-channel MOS transistor Q51, which becomes the same as the source voltage, so it is turned off. Furthermore, Q53 of the switch circuit 5 is also
At the same time, it turns on and the external power supply voltage ■. o6 will be applied to the internal power supply bus 6 via Q53. Therefore, the voltage vcc l of the internal power supply bus 6 is
The voltage is maintained at the same voltage as t and changes.

Furthermore, when the external power supply voltage VCCE decreases to +3.3V or less, the voltage between the source and drain of the transistor Q21, which is the constant current source of the reference voltage generation circuit 2, becomes reverse polarity and no current flows. Current consumption also becomes zero. At this time, the active load type differential amplifier 3 is still in an inactive state, that is, current consumption is zero. This is a typical data retention voltage of 2 to 3
It will be appreciated that the current consumption of the entire integrated circuit device is therefore very low.

Further, a reference voltage generation circuit, which is a component of this embodiment,
Various modifications can be made to amplifier circuits such as active load type differential amplifiers, voltage detection circuits, switch circuits, etc.
Of course, the invention can be applied without departing from the spirit of the invention.

Next, a second embodiment of the present invention will be described.

FIG. 2 is a circuit diagram of a second embodiment of the invention. Second
In the figure, an external power supply terminal 1, a reference voltage generation circuit 2, an active load type differential amplifier 3, and a switch circuit 5 are almost the same as those in the first embodiment shown in FIG. 1 except for the details. Therefore,
Here, we will focus on explaining the parts that are different from the first embodiment to avoid duplication.

Referring to FIG. 2, the active load type differential amplifier 3 is controlled by a chip selection signal (CS) from a central processing unit (CPU) that is combined with the integrated circuit device of this embodiment and controls it. ) is executed. However, in Figure 2, C
The display of PU is omitted. Here, C8 is required when a plurality of memory devices are used simultaneously to increase address capacity, and has a function of switching each memory device between an operating state and a standby state. In this embodiment, C8 is a high level signal with a positive number of V and a low level signal with a ground potential.

In other words, when C8 is at high level, the operating state is
When the level is low, the standby state is selected.

Next, the voltage detection circuit 4 is a part that is largely different from the first embodiment. The voltage detection part consisting of P-channel MO3) transistor Q41 and N-channel MO3) transistor Q42 is the same as in the first embodiment, but in addition,
A complementary inverter circuit 41 consisting of a P-channel MOS transistor Q43 and an N-channel MO3) transistor Q44 is followed by a complementary inverter circuit 42 consisting of C45 and C46. Note that the inverter circuit 4
2 obtains power from an internal power supply bus 6.

As mentioned above, the switch circuit 5 is almost the same as the first embodiment, except that the above-mentioned C8 is applied to the gate of the gate control transistor Q52 of the output transistor Q51, and Bypass transistor Q
The output of the inverter circuit consisting of C45 and C46 is applied to the gate of C53, and the channel width of the gate of C51 is much larger than that of C53, for example, about 100 times. Things are different.

Next, the operation of this embodiment will be explained.

In FIG. 2, first, the voltage V at external power supply terminal 1
CCε is set to be at least +4.5v, which is the minimum operating voltage.

Moreover, the chip selection signal C8 is at a high level, that is,
It is assumed that the operating state is selected. Furthermore, the design value of the internal power supply bus 6 is +3.3V as in the first embodiment.

Therefore, the output voltage of the reference voltage generation circuit 2 is +3.3V at the node N1, and the output voltage of the reference voltage generation circuit 2 is +3.3V at the node N1.
Each voltage is applied to the voltage detection circuit 4.

The active load type differential amplifier 3 receives the high level C8,
Since the source measurement current source transistor Q33 is turned on, it is in an operating state. At the same time, switch circuit 5
Since C52 is off, the output transistor Q
51 performs a voltage control operation by the active load type differential amplifier 3 to maintain the internal power supply voltage VCCI at +3.3V.

In this case, the output signal of the node N2 of the voltage detection circuit 4 is
Therefore, the output signal of the node N3, which is the output terminal of the inverter circuit 41, is at the low level, and the output signal of the node N4, which is the output terminal of the inverter circuit 42, is at the high level.

However, as described above, since the inverter circuit 42 is connected to the internal power supply bus, the high level signal at the node N4 is VCCI, that is, +3.3.

This high level signal at node N4 is applied to the gate of P-channel transistor Q53 of switch circuit 5. As a result, the gate and drain of Q53 are equivalently short-circuited and connected as a diode, so that Q53 operates in the saturation region. Therefore, Q5B is V. When CIl knee VCCI is equal to or higher than the threshold voltage vT, it is in an on state. The source voltage of Q53 is VCC4,
In other words, since it is H, 5V or more, Q53 maintains the on state. Therefore, in this case, both voltage control output transistors Q51 and Q53 become conductive.

However, as mentioned above, the channel width of the gate of Q51 is much larger than that of Q53, so Q41 and Q41 of the voltage detection circuit 4 explained in the first embodiment are
Since the operation of Q53 has almost no effect, the voltage of the internal power supply bus 6 is determined by the operation of Q51.

Next, a case will be described in which the chip selection signal C8 is at a low level, that is, in a standby state.

It is assumed that the external power supply voltage VCCE remains at +4.5V or higher.

In this case as well, the output voltage of the reference voltage generation circuit 2 is +3jV at the node N1, and is applied to the active load type differential amplifier 3 and the voltage detection circuit 4, respectively.

The active load type differential amplifier 3 receives the low level C8,
Since the source measurement current source transistor Q33 is turned off, it becomes inactive and no current flows. At the same time, Q52 of the switch circuit 5 is turned on, and the output transistor Q51 is turned off since VCCE is applied to its gate.

Further, the operation of the voltage detection circuit 4 is based on the above-mentioned high level C8.
This is exactly the same as in the case of the inverter circuit 42.
The output signal of node N4, which is the output terminal of , becomes high level. As a result, the gate and drain of Q53 are equivalently short-circuited and connected as a diode, so that Q53 operates in the saturation region and maintains an on state. Therefore, the external power supply voltage VCeE is connected to the internal power supply bus 6 via Q53.
will be applied to Therefore, the voltage V of the internal power supply bus 6. ct is kept at VcctlV↑1 while changing.

Therefore, in this standby state, the current of the active load type differential amplifier is cut off, so that the current consumption of the integrated circuit becomes extremely small.

Next, a case where the external power supply voltage VCCE decreases while the chip selection signal C8 remains low will be described.

As explained in the first embodiment, first, VCCE is +3
．． In the case of 3V or more, the output voltage of the reference voltage generator, path 2, ie, the voltage at node N1, is kept at +3jV. As described above, in this case, the force signal at the node N2 of the voltage detection circuit 4 is at a low level, and therefore the output signal at the node N3, which is the output terminal of the inverter circuit 41, is at a high level, which is the output terminal of the inverter circuit 42. Node N
The output signal of No. 4 becomes low level, that is, the ground potential. Therefore, Q53 of the switch circuit 5 is turned on because the gate voltage has a higher negative potential than the source voltage, and the external power supply voltage VCCE is then applied to the internal power supply bus 6. Furthermore, the external power supply voltage V. o
6 is lowered to +3.3v or less, this is the same as in the first embodiment, so the explanation will be omitted.

In this second embodiment, a static memory device is cited as a typical example of an integrated circuit device to which it is applied.

In this case, the internal power supply bus 6 is divided so that one side is used exclusively for the memory cell array and is supplied with power from the bypass transistor Q53, and the other one is used for other circuits and is supplied with power from the voltage control output transistor Q51. You can also do it. The advantage of this is that the current consumption during standby is almost exclusively for data retention in the memory cell array, so that the negative layer power consumption is reduced. Furthermore, by applying a higher external power supply voltage to the memory cell array instead of the internal power supply voltage, there is an advantage that data retention reliability can be further increased.

Next, a third embodiment of the present invention will be described.

FIG. 3 is a circuit diagram of a third embodiment of the present invention. Third
In the figure, an external power supply terminal 1, a reference voltage generation circuit 2, and an internal power supply bus 6 are almost the same as those in the first and second embodiments except for the details. Further, the voltage detection circuit 4 is almost the same as that in the second embodiment. Therefore, here, the first and second
We will focus on explaining the parts that are different from the embodiment, and will avoid duplication.

In this third embodiment, a voltage drop circuit 7 composed of a plurality of series-connected diodes D71 to D7n is used in place of the active load type differential amplifier in the first and second embodiments.

Further, the switch circuit 5 is composed only of a P-channel MOS transistor Q53.

Next, the operation of this embodiment will be explained.

In FIG. 3, first, the voltage V at external power supply terminal 1
CCE shall be at least +4.5V, which is the minimum operating voltage.

Further, the output voltage of the reference voltage generation circuit 2 is assumed to be +3.3V at the node N1, and is applied to the voltage detection circuit 4. Therefore, the output of the node N4, which is the output terminal of the voltage detection circuit 4, is at a high level, that is, essentially the internal power supply voltage VCCI, and is applied to the gate of the P-channel MOS lanciter Q53. Keep it on.

Next, a case where the external power supply voltage VCCE decreases will be explained. As explained in the first and second embodiments, first, when VCCB is +3.3V or more, the output signal of the node N4, which is the output terminal of the inverter circuit 42 of the voltage detection circuit 4, becomes low level. Therefore, the switch circuit 5
Q53 continues to be on and the external power supply voltage VCCE
will be added to the internal power supply bus 6.

Furthermore, the case where the external power supply voltage VCCE decreases to +3.3v or less is also the same as in the first and second embodiments, so the explanation will be omitted.

As described above, power is supplied to the internal power supply bus 6 from the external power supply terminal 1 via the voltage drop circuit 7. Therefore, the internal power supply voltage vcc I has a value lower than the external power supply voltage VCCE by the voltage drop of the voltage drop circuit 7.

The value of this voltage drop can be freely set depending on the number of diodes connected in series in the voltage drop circuit 7, the current supply capacity determined by the PN junction area, etc.

The operating current of the reference voltage generation circuit 2 is related to the voltage detection circuit 4 and the load capacitance such as the input capacitance of the active load type differential amplifier in the first and second embodiments. The reason for this is the external power supply voltage V. The follow-up characteristic of the reference voltage output vN1 with respect to fluctuations in CE depends on the time constant determined by these capacitances and the output resistance of the reference voltage generation circuit 2, and this output resistance increases as the operating current of the reference voltage generation circuit 2 increases. Therefore, in order to obtain appropriate tracking characteristics, the larger the load capacity, the more
This is because it is necessary to increase the operating current.

In this third embodiment, as is clear from the above description, the load on the reference voltage generation circuit 2 is only the voltage detection circuit 4. Therefore, there is no need to consider the active load type differential amplifier, which has a relatively heavy load, so there is an advantage that the operating current is smaller than the designed one. Therefore, there is an advantage that the negative layer current consumption can be reduced as a whole of the integrated circuit device.

〔Effect of the invention〕

As explained above, according to the present invention, a drop in the power supply voltage supplied from the outside is detected, and when the voltage falls below a preset threshold, the voltage control circuit for controlling the voltage of the internal power supply bus is turned off. operation, and by switching to supply current directly from the external power terminal to the internal power bus.
This has the advantage of providing an integrated circuit device such as a static memory that significantly reduces current consumption when the external voltage drops below the data retention voltage.

[Brief explanation of drawings]

FIGS. 1, 2, and 3 illustrate the first embodiment of the present invention. FIG. 4 is a circuit diagram showing the second and third embodiments, respectively, and FIG. 4 is a circuit diagram showing an example of a voltage control circuit built into a conventional integrated circuit device. 1... External power supply terminal, 2... Reference voltage generation circuit, 3
...active load type differential amplifier, 4...voltage detection circuit,
5... Switch circuit, 6... Internal power supply bus, 7...
・Voltage drop circuit, 41.42... Inverter circuit.

Claims (1)

[Claims] 1. In an integrated circuit device having an integrated circuit and a power supply circuit that supplies power to the integrated circuit, the power supply circuit includes: a first power supply that supplies power to the integrated circuit component; a voltage control means for adjusting an externally supplied voltage to a required voltage and supplying it to the power supply bus; and a voltage detecting means for detecting when the externally supplied voltage becomes equal to or less than a predetermined voltage threshold. and a switching means for disconnecting the voltage control means from an external power supply and switching to supply power directly from the external power supply to the power supply bus according to the detection result of the voltage detection means. circuit device. 2. The integrated circuit device according to claim 1, wherein when the externally supplied voltage is equal to or higher than the voltage threshold, the voltage control means is put into an operating state, and when it is below, it is put into an inoperative state. 3. The integrated circuit device according to claim 1, wherein the voltage control means is controlled to be in an active state or a non-active state by a signal for selecting an active state or a standby state of the integrated circuit. 4. The integrated circuit device according to claim 1, 2 or 3, wherein the integrated circuit includes a memory circuit and a control circuit thereof;
An integrated circuit device characterized in that a second power bus to which external power is constantly supplied is connected to the memory circuit, and the first power bus is connected to the control circuit. 5. The integrated circuit device according to claim 1, wherein the voltage control circuit comprises at least one diode.