JPH0320850A - Input/output controller - Google Patents

Abstract

PURPOSE:To prevent an underrun error or an overrun error from occurring by outputting a direct memory access request at a preset cycle to a host device according to the setting of an access cycle setting part. CONSTITUTION:For example, an access cycle for appropriate direct memory access transfer is calculated based on the number and the capability of an input/output controller 100 in which the host device 1 is connected to a system bus 2. And the setting of the access cycle is performed as necessary on the access cycle setting part 200 of each input/output controller 100. Consequently, each input/output controller 100 can output the direct memory access request at the optimal cycle. Thereby, the underrun error and the overrun error can be prevented from occurring.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is connected to a host device via a system bus,
This article relates to an input/output control device that controls direct memory access transfer using a system bus for input/output devices. (Prior Art) FIG. 2 shows a block diagram of a conventional general information processing device.

In the figure, a CPU (central processing unit) l is connected to a system bus 2 and controls the entire device. This system bus 2 includes an MM (main memory) 3 and
an address decoder 4, a KBC (keyboard controller) 5, a CRTC (CRT controller) 6,
PRC (printer controller) 7 and DMAC (
Direct memory access controller) 8 and FDC
(floppy disk controller) 9 is connected.

KB (keyboard) 11 is connected to KBC5, and CR
A CRT (cathode ray tube) 12 is connected to the TC6, a PR (printer) 13 is connected to the PRC7, and a floppy disk device l4 is connected to the FDC9. On the other hand, an I/O bus 16 is connected to the system bus 2 via an I/O buffer 10. This I/O bus 1
6 includes an input/output device section l5 consisting of several input/output devices.
is connected. The input/output device section 15 includes an HDC (
hard disk controller) 17, TRC (communication control interface) 18 and other input/output devices 19
is connected.

In the device with the above configuration, the operator monitors the CRT 12 while operating the KBII, and the results of predetermined information processing are displayed on the P.
The data is printed out by the R13, and stored in the floppy disk device 14 as necessary. Further, necessary data is read and written using the HDD 20 connected to the HDC 17, and predetermined processing is executed. Furthermore, information is exchanged with an external device (not shown) via a communication line 18a connected to the TRC 18. Also,
When the CPU 1 attempts to access any device via the system bus 2, an address signal output from the CPU I is input to the address decoder 4, and the address decoder 4 performs control (not shown) based on the address. Selectively operate either device via the line.

The I/O buffer 10 is connected to the system bus 2 and the I/O bus 1.
It consists of a driver receiver, etc. that connects to 6. By the way, in the information processing device configured as described above,
When the CPU 1 reads out and uses predetermined data from the input/output device section 15, for example, the HDD 20, the data is
Once, the memory access is transferred to MM3 via DMAC8. Figure 3 shows a concrete block diagram of a conventional input/output device. The figure is a concrete block diagram of an input/output device 2l including an HDD 20 connected to an I/O bus 16. This input/output device 2l is connected to the I/O bus 16.
The configuration is such that a BM (puffer memory) 22 and an HDDLS I (hard disk drive integrated circuit) 23 are connected to the DC 17 via a local bus 24. This input/output device 2l uses the HDDLSI 23, developed exclusively for high-speed access to hard disks, to temporarily store data on the HDD 20 in the BM 22, and
The DMAC8 shown in the figure is the BM22 shown in this Figure 3.
It operates to transfer data stored in MM3 to MM3 by direct memory access. In addition, the DMAC8 transfers the data stored in the MM3 to the BM22,
It also performs the operation of writing to the HDD 20. As described above, the configuration shown in FIG. 3 enables high-speed direct memory access transfer.

(Problem to be Solved by the Invention) By the way, each input/output device making up the input/output device section l5 shown in FIG. Output the request. Figure 4 shows an explanatory diagram of the DMA load factor. As shown in FIG. 4, if T is the access period for outputting direct memory access requests from a certain input/output device, and t is the DMA time during which direct memory access transfer is performed, then the DMA load factor is t/ It can be expressed as T (%). The DMA time t is the execution time for the DMAC 8 shown in FIG. 2 to actually execute direct memory access transfer. That is, when each input/output device making up the input/output device section l5 in FIG.
Each time, the AC 8 occupies the system bus 2 shown in FIG. 2 for a DMA time t, and direct memory access transfer is executed. In addition, B of the input/output device 21 shown in FIG.
The storage capacity of M22 is selected in consideration of the access cycle T mentioned above. Here, if the overall DMA load factor of the input/output device section 15 increases and the time that the DMAC 8 occupies the system bus 2 becomes longer, the operating time of the CPU itself increases, for example, access to the PRC7 or FDC9 in FIG. The available time is reduced.

FIG. 5 shows an explanatory diagram of the system bus occupancy state due to DMA transfer.

For example, if the input/output device A shown in FIG. 5(a) and the input/output device B shown in FIG. If the DMA time is t, the same figure (d)
As shown in , the operating time of the CPU itself is T-2t.
becomes. If there are three input/output devices, it will be T-3t. Furthermore, when executing an I/O command, a ready latency time during which the CPU waits for a response, an INTA cycle time during which the CPU 1 stops operating to accept an interrupt, etc. are required. Therefore, the remaining time after subtracting these amounts is the time during which CPU 1 can operate. This operating time of CPU 1 determines the so-called CPU throughput, and if this time does not exceed a certain level, the second
The PRC7 and F.R.C. shown in the figure. There is also a risk that an underrun error or overrun error may occur when accessing DC9, etc. Furthermore, for example, as shown in FIG. 5(C), if an input/output device whose access cycle for outputting direct memory access requests is T', which is shorter than T, is added, the CPU
Not only is the operational time of the I significantly reduced, but
The direct memory access requests of each input/output device A, B, and C compete with each other, and there is a possibility that an underrun error or an overrun error may occur in the direct memory access transfer operation of the DMAC 8 shown in FIG. 2 itself.

The present invention was made with attention to the above points, and when adding input/output devices, etc., the DMA load factor increases and the CPU
In order to eliminate the problem of reduced throughput and further prevent underrun errors and overrun errors during DMAC operation, the period for outputting direct memory access requests of each input/output device is adjusted according to the system capacity. The purpose is to provide an input/output control device that can be configured arbitrarily. (Means for Solving the Problems) An input/output control device of the present invention is connected to a host device via a system bus, and controls direct memory access transfer of the input/output device using the system bus. an access cycle setting unit that arbitrarily sets a cycle for outputting direct memory access requests for the direct memory access transfer; and a direct memory access request to the host device at a set cycle according to the settings of the access cycle setting unit. The present invention is characterized in that it includes an access request output unit that outputs an access request.

(Operation) In the above device, for example, the host device calculates in advance an appropriate access cycle for direct memory access transfer based on the number and capacity of input/output devices connected to the system bus. Then, the access cycle is set at any time in the access cycle setting section of each input/output control device. As a result, each input/output control device outputs a direct memory access request at an optimal cycle, thereby preventing underrun errors and overrun errors. The access cycle is reset, for example, when adding input/output devices or changing the design of the system.

(Example) <Main parts of the device and general operation> The present invention will be explained in detail below using the example shown in the drawings. FIG. 1 is a block diagram of the main parts of the input/output control device of the present invention. The illustrated input/output control device 100 is connected to a host device 1 via a system bus 2. As shown in FIG. In this diagram, I/O
Illustrations of buses, etc. are omitted. This input/output control device 100 is controlled by a central control section 101. The central control unit 101 includes a sub CPU 101' and a sub DMAC.
IO1'' is installed.

Furthermore, as an access request output unit in the present invention, DP
A DMA boat interface (I) 113 is provided, and a timer circuit 200 is provided therein as an access cycle setting section in the present invention.

In addition to this, the input/output control device 100 includes an address decoder circuit 103 and a data driver/receiver circuit 106.
is provided.

A detailed explanation of the operation of this circuit will be given later, but here, its general operation will be explained very briefly.

The central control unit 101 includes a sub CPU 101' and a sub DMACIOI''.
i' controls the entire input/output control device 100, and
C101'' is a circuit that controls the direct memory access operation of the input/output control device 100. Note that the DMAC8 is used in cascade mode. When the signal M-DREQ100a for direct memory access request is output to D
The system bus 2 is notified by the M A C 8 and the host device 1 approves it with a request signal from the DMAC 8.
is occupied and DM. DMA acknowledge signal M-DA from AC 8 to input/output control device 100
C K 100b is returned. Input/output control device 10
0 outputs a signal MEMR100c requesting to read data from MM3 or a signal MEMW100d requesting writing data to MM3, along with a write address and write data or a read address. Direct memory access transfer is executed by DMAC8.

Note that inside the input/output control device 100, the direct memory access signal DMAR generated by the DPI 113 is
E Q 101c is a sub DM of the central control device 101
Enter ACIOI'. Sub DM AC 101
' in response to its DMAREQIO1c,
Signal MEM that is the basis of MR100c and MEMW100d
Outputs RD101a or MEMWR10lb.
The flip-flop (F
/F) The circuit 205 includes MEMRD101a and MEMW.
This circuit outputs DMAREQ 101c at a set access cycle based on signals such as R10lb and signals 2008 and the like output from the timer circuit 200 at a set access cycle.

Note that a predetermined access cycle is set in the timer circuit 200 by the central control unit 101 according to a procedure described later.

<Overall configuration of the device> Now, we will proceed with the explanation starting from the overall configuration of the apparatus of the present invention.

FIG. 6 is a block diagram showing the overall configuration of the input/output device of the present invention.

In the figure, the system bus 2 includes the C
．． A host device 1 such as P U 1 is connected.

Furthermore, this system bus 2 includes an MM (main memory) 3.
, a DMAC (direct memory access controller) 8 and an I/O bus 16 are connected. Note that the I/O bus 16 and the system bus 2 are connected to each other.
The illustration of the O buffer has been omitted. The I/O bus l6 includes an input/output control device 1 related to the present invention.
00 is connected. This input/output control device 100 includes a central control section 101 and an address latch circuit 102, which were previously explained using FIG.
, address decoder circuit 103, local memory l0
4. Address driver circuit l05, data driver/receiver circuit 106, IOC (IO controller) 10
7, a data driver/receiver circuit 108, an arbiter circuit 109, a PPI (program passport interface) 114, and a DPI (DMA boat interface) 113.

The central control unit 101 and the address latch circuit 102 are connected by an address signal line 130. Further, from the central control unit 101 to the address latch circuit 102,
It is connected to receive an address latch enable signal 101e that becomes active when the address signal is valid. Further, the address latch circuit 102, the address decoder circuit 103, the address driver circuit 105, and the local memory 104 each have an address signal line
31. Address driver circuit 1
05 is an address signal output by the central control unit 101,
This is a circuit that outputs to the engineering/0 bus 16.

Central control unit 101 and data driver/receiver circuit 10
6 is a data signal line 1 that can transmit data bidirectionally.
Connected by 40. Also, data driver/receiver circuit l06, data driver/receiver circuit l0
8, arbiter circuit 109, PPI114, DPI113
They are connected by a data signal line 141 that allows bidirectional data transmission.

The IOC 107 and the arbiter circuit 109, and the arbiter circuit 109 and the local memory 104 are also connected by data signal lines 143 and 142, which are capable of bidirectional data transmission, respectively. The IOC 107 is a circuit for controlling the HDD 20. The address decoder circuit 103 includes the central control unit 101
This circuit receives an address signal outputted by the circuit via the address signal line 131 and outputs a chip select signal for each circuit. The figure shows a signal MM-MAPADR10 that activates the output signal of the address decoder circuit 103 when the central control unit lot accepts the address signal output when accessing the MM3 via the system bus 2.
Only 3a is shown. This signal MM-MAPADR
103a is connected to input to DPI 113. A L E 101e output from the central control unit 101 to the address latch circuit 102 is a signal that controls the address latch circuit 102 to latch the address signal when the central control unit 101 outputs the address signal. be. The data driver/receiver circuit 106 and the data driver/receiver circuit 108 are each composed of a tri-state puffer or the like capable of bidirectional data transmission. The data driver/receiver circuit 106 includes a data transfer direction control signal 106a and an enable signal 106.
It is wired so that b is input. This data transfer direction signal 106a is an I
O R 120a and M E M R D 101a,
The two signals, both low active, are connected to the AND gate 1.
It is generated by inputting 10. That is, if the transfer direction control signal 106a output from the AND gate 110 is at a low level, data is transferred from the data signal line 141 to the data signal line 140, and the transfer direction control signal 1
If 06a is at high level, data is transferred in the opposite direction.

It should be noted that the IOR 120a and the IOW 120b are both signals output during command read/write operations of the host device 1 etc. via the PPI 114.

On the other hand, the enable signal 106b includes the data enable signal 111a output from the central control unit 101 and the DPI+1
A signal obtained by inverting the signal M-D A C K 100b outputted from gate 3 by inverter 112 is input to gate 1l.
! to accept and generate. Data enable signal 111a
is row active, M-D A C K 100
b is also a row active signal. Therefore, the data enable signal 111a or M-D A C K 10
0b is supplied to the data driver/receiver circuit 106 via the O7 gate 111, the data driver/receiver circuit 106 connects the data signal lines 140 and 14
1, and the central control unit 101
PI 114 and data driver/receiver circuit 108
data is read from the local memory 104 via the data signal line 141, and data output from the central control unit 101 is transferred to the data driver/receiver circuit 108 or the PP.
Enables operations to transfer to I114 and DPI113. On the other hand, during direct memory access transfer,
The enable signal 106b becomes high level.

Therefore, during that time, the data driver/receiver circuit 106
The operation of will stop. On the other hand, M-DACK 100
b is connected to be input to the address driver circuit 105 and the data driver/receiver circuit 108,
During this time, both circuits 105 and 108 operate, and data can be exchanged between data driver/receiver circuit 108 and MM3 via system bus 2 and I/O bus 16.

The IOC 107 writes data stored in the HDD 20 to the local memory 104, or reads data stored in the local memory 104, and writes the data stored in the HDD 20 to the local memory 104.
This is a circuit that controls writing to.

The arbiter circuit 109 handles requests from the central control unit 101 and IO
This circuit accepts requests from the C107 and adjusts conflicts between requests for use of the data signal line 141. In addition, when the sub DMAC 101'' of the central control unit 101 makes a direct memory access request, the MM
Signals MEMRD101a and MEMWR1 specify whether to write to MM3 or read from MM3.
0lb is output. MEMRD101a is the AND gate 11 explained earlier.
0, DPI 113 and local memory 104
and a direction control terminal of the data driver/receiver circuit 108. Therefore, this M E
In addition to the read request to MM3, MRD l01a
It is also used to read data from the local memory 104 and to instruct the data driver/receiver circuit 108 in the direction of data transfer. The P P I 114 is connected to the host device 1 and the central control unit 101.
This is an interface circuit for exchanging commands with. The PPI 114 sends M-I, which is an interrupt request signal to the host device l of the central control unit 101.
NT is output to the I/O bus l6, and the central control unit 1
S-INT101d which is an interrupt request signal for 01
The system is configured to accept the information from the host device l and output it to the central control unit 101. The DPI 113 is an interface circuit for executing direct memory access transfer between the input/output control device 100 and the MM3, as previously explained using FIG. I/O bus 1 from this DPI 113
Toward 6, M-DR E Q 100a, M
EMR100c and MEMW100d are output, and M-DAC is output from the I/O bus 16 as a response.
K 100b inputs. On the other hand, the MEMRD 101a and MEMWR 10lb are input from the central control unit 101 to the DPI 113,
From address decoder circuit 103 to MM-MAPADR1
03a inputs. Then, from the D P I 113, the DMAREQ 101c described earlier is sent to the central control unit 1.
01's sub DMAC 101''. (ppr configuration and operation at startup) Figure 7 shows a specific block diagram of the PPI shown in Figure 6. I 114 includes an instruction decoder circuit 1 1
4a, a data driver/receiver circuit 114b, and a data driver/receiver circuit 114c. The instruction decoder circuit 1 14a is connected to input M-Address, M-1OR, and M-10W from the I/O path 16. The data driver/receiver circuit 114b also receives M-Data from the I/O bus 16.
is wired so that it can be input. The instruction decoder circuit 114a decodes the address signal etc. output from the host device l and sends the S-INT signal to the central control unit 101 and the data driver/receiver circuit 114b.
In addition to outputting the signal 101d, this circuit also outputs an operation enable signal 114e to the data driver/receiver circuit 114c. Data driver/receiver circuit 11
4b is an instruction decoder circuit. 114a, I
The data input from the /O bus 16 is transferred to the data signal line 14.
This is a circuit that outputs to the central control unit 101 via 1. The central control unit 101 receives a signal IOR for control of work/○.
120a, data driver/receiver circuit 1
14b and read the data. On the other hand, the data driver/receiver circuit 114c is a circuit that outputs data output from the central control unit 101 to the data signal line 141 toward the I/O bus 16. This data driver/receiver circuit 1 14c receives a signal IOWl for I/O output output from the central control unit 101.
20b and the data on the data signal line 141, and executes data output according to the operation enable signal 114e output from the instruction decoder circuit 114a. Furthermore, the central control unit 101 transmits the M-INT 120c, which is an interrupt signal to the host device l, via the PPI 114.
It is wired to output to /O path 16. The PPI 114 with the above configuration operates as follows. FIG. 8 is an explanatory diagram of the operation of the apparatus of the present invention at startup.

In the figure, first, the central control unit 101 of the input/output control device
outputs a power-on-ready interrupt to host device 1 at startup. This is the M-INT12 shown in Figure 7.
0c is executed by outputting it to the higher-level device l. The host device 1 learns that the input/output control device has been activated, and activates the central control unit 101 of the input/output control device.
Notify the initial request to. This is the seventh
This is done via the instruction decoder circuit 114a shown in the figure. The signal S-INT101d is sent to the central control unit 101.
, the central control unit 101 recognizes from the contents of the initial request that the host device 1 has notified the access cycle and the assigned address of the MM3 shown in FIG. Therefore, the central control unit 101
The M-INT120c for interrupt is issued to the host device 1 again as a command return. Thereafter, as shown in FIG. 8, the host device 1 sends notification of the access cycle and address. The memory size and memory length are notified. The access cycle is calculated in advance by the host device 1 in order to operate the system efficiently.
As shown in Figure 8, the address notification is
You will be notified in installments. Also, the memory length is, for example, ×
You will be notified with content such as x bytes. As a result, the central control unit 101 of the input/output control device recognizes that an area of xx bytes has been allocated from the top address in the address notification on the main storage device. Setting the access cycle> Returning to Figure 1 again, the operation of setting the cycle for outputting direct memory access requests will be explained. As explained using FIG. 8, when the host device notifies the central controller 101 of the access cycle, the central controller 101 sends the timer circuit 200 provided in the DPI 113 of FIG. On the other hand, it outputs a timer chip select signal TIMCS120d and a signal IOW120b for write operation to the timer circuit 200. Furthermore, the timer circuit 20 is connected via the data signal line 140, the data driver/receiver circuit 106, and the data signal line 141
0, input data corresponding to the access cycle previously notified from the host device.

This completes the access cycle setting. (Configuration of PPI) Here, the DPI 113 in FIG. The MEMRD 101a output from the central control unit 101,
MEMWR 10lb is AND gate 20
4 &:: is input and is connected to be input to the driver circuit 206. Furthermore, the output of the AND gate 204 and the MM- output from the address decoder circuit 103 are
M A P A D R 103a is Noah Gate 20
3 and generates a signal that is input to the J terminal of the flip-flop circuit 205. In addition, the MM output from the address decoder circuit 103
- The MAPADR 103a enters the OR gate 201 via the inverter 2o2. A signal 200a output from the timer circuit 200 at a previously set access cycle is also input to the OR gate 20l. or gate 20
The output of 1 is used as an input signal to the K terminal of the flip-flop circuit 205. The flip-flop circuit 205 has
Furthermore, a reset signal R E S E T205 that is active for a certain period of time when the power is turned on is connected to the reset terminal.
The wires are connected so that a is input. <Main operations of the device> The circuit shown in Figure 1 above operates as follows when executing a direct memory access transfer. FIG. 9 shows an operation time chart of the apparatus of the present invention. In the figure, row active signals are marked with *. First, at time t, as shown in FIG. 9(a),
The reset signal RESET205a when the power is turned on is at time t.
, ~ becomes active until time t2.

As a result, the flip-flop circuit 205a in FIG.
The q output of becomes active and DMAREQ101C is output, but in the central control unit 101, the sub D M
Since A C 101'' is masked, it is not activated yet.Next, when the operation shown in FIG. 8 is completed and the timer starts at time t3, the set access cycle TD
After a time, at time t4, the timer output 200a of the timer circuit 200 shown in FIG. 1 becomes active for l clocks [FIG. 9(b)].

As a result, the flip-flop circuit 20 shown in FIG.
5 becomes low level, DMAREQ 101c becomes active and is output from the flip-flop circuit 205 [FIG. 9 (8)]. This DMA R
E Q101c is the sub-DM of the central control device 101.
Enter A 0 101'. Here, the central control device 101 clears the mask of the sub-DMAC 101'', allows the operation of the sub-DMACIOI', and
An address for accessing MM3 is output to address decoder circuit 103 in FIG. Address decoder circuit 103 recognizes that the address signal is for accessing MM3, and
103a is output as active [FIG. 9(C)].

This MM-MAPADR 103a is output at time t6 in FIG. Immediately before this time t6, the timer circuit 200
A timer output 200a is output from the sub-DM A C 101'', and a timer output 200a is output from the sub-DM AC 101''.
01a or MEMWR 10lb is output [Fig. 9(d)]. As a result, the J terminal of the flip-flop circuit 205 shown in FIG. 1 becomes high level. On the other hand, as shown in FIGS. 1 and 9(f), the input signal of the J terminal of the flip-flop circuit 205 is directly transferred to M-D.
It is output to DMAC8 as REQl00a. When the DMAC 8 accepts the M-DREQ 100a, the M-DACK 100b sends the D P
Input to I113 [Figure 9(g)]. This M-
DACK 100b enables driver circuit 206 of FIG. Note that the driver 206 is composed of a tri-state buffer or the like.

On the other hand, M-DAC, Kl00b operates the data driver/receiver circuit 108 shown in FIG. 6, so that the data on the data signal line 141 is transferred to MM3, or the data from MM3 is , is input to the data signal line 141 via the data driver/receiver circuit 108 [FIG. 9(h)]. This data transfer direction is
As described above, it is controlled by the MEMRD 101a.

At time t7 in FIG. 9, when the timer output 2QOa becomes active for a predetermined time again, the DMAREQ 101c rises [FIG. 9(e)], and the central processing unit 101 receives this, and the MM-MAPADR 103a, M E
A signal such as MRD I01a or MEMWR101b is output. Subsequent time t a. to. t
,. ．． The operations at times t■, etc. are performed at times ti, ts. ty, the same operation is repeated at a preset period T. The present invention is not limited to the above embodiments.

The access cycle setting section does not necessarily need to be composed of a timer circuit. For example, known equivalent means such as an arithmetic circuit or a comparison circuit may be substituted. The settings may be made individually by an operator or may be made by a host device. Further, the access request output section may also be replaced with a known circuit having an equivalent function.

(Effects of the Invention) The input/output control device of the present invention described above is provided with an access cycle setting section that arbitrarily sets the cycle for outputting direct memory access requests. Direct memory access requests can be issued. Therefore, when adding input/output devices to the system or changing the design of the system, the cycle for outputting direct memory access requests for each input/output device should be selected and changed as appropriate to improve throughput. be able to. Therefore, an underrun error occurs due to an increase in the DMA load rate. It is possible to prevent overrun errors and the like from occurring.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main parts of the input/output control device of the present invention,
Figure 2 is a block diagram of a conventional general information processing device, Figure 3 is a specific block diagram of a conventional input/output device, and Figure 4 is a DM.
An explanatory diagram of A load factor, Fig. 5 is an explanatory diagram of the system bus occupation state due to DMA transfer, Fig. 6 is a block diagram showing the overall configuration of the input/output device of the present invention, and Fig. 7 is a concrete block of PPI. 8 is an explanatory diagram of the operation of the apparatus of the present invention at startup, and FIG. 9 is an operation time chart of the apparatus of the present invention.

Claims (1)

[Scope of Claims] 1. A device that is connected to a host device via a system bus and controls direct memory access transfer of an input/output device using the system bus, comprising: direct memory access of the direct memory access transfer; an access cycle setting unit that arbitrarily sets a cycle for outputting a request; and an access request output unit that outputs a direct memory access request to the host device at a set cycle according to the settings of the access cycle setting unit. An input/output control device featuring: 2. The access cycle setting unit, in accordance with the notification from the higher-level device,
2. The input/output device according to claim 1, wherein a cycle for outputting direct memory access requests is set.