JPH03192752A - Manufacture of substrate structure of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to obtain a high-integration degree integrated circuit by a method wherein an element isolation region and a field oxide region are formed almost flat to an element region. CONSTITUTION:A deep groove 11a for interelement isolation use is formed in a self-alignment manner by utilizing an anisotropic etching on a pattern region covering an element region and at the same time, a silicon oxide insulating film 21 and a silicon nitride insulating film 22 are formed in order on the inner wall of this groove 11a and after that, a remaining recessed part is filled with a filler 24. Moreover, before the surface, which faces the groove, on one side of a silicon substrate is oxidized and a field oxide film 25 is formed, an etching is performed on the substrate surface at a field oxide region, and the film 25 to be formed is ready-formed to the part of the thickness of about 1/2 of the film 25, whereby the surface of the substrate is formed flat as a whole. Thereby, an interelement isolation structure, which is superior in high integration, can be easily obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a substrate structure of a semiconductor device, particularly an integrated circuit semiconductor device in which a large number of elements are incorporated on the same substrate.

[Margin below]

[Prior Art] Conventionally, a selective oxidation method for selectively thermally oxidizing lines and the periphery of an element has been put to practical use as a method for isolating elements in a semiconductor device of this type. Furthermore, various methods have been devised to form a groove in the periphery of the element and fill it with dielectric material.

Among these, the selective drinking method requires, for example, the lifting platform of the bipolar process and the complete separation of the Evitamcial layer with an oxide film, and the long-term thermal oxidation causes the redistribution of unused MW to deteriorate the performance of the confectionery. deteriorate.

Furthermore, bird's beaks and bird's heads are formed during selective oxidation, which impedes high performance of integrated circuits.

On the other hand, with the method of forming trenches and filling them with dielectric material, generally only a narrow isolation region of a fixed width can be formed, and a thick field oxide region for interconnection is required. It wasn't.

Even if a thick field oxide region was formed in contact with the isolation trench as proposed in 1 Jul. 1, it would require a new photolithography process, which would complicate the process, as well as mask alignment problems. Taking into account the margin of field oxidation, when forming a field oxidation region, it is impossible to form a field oxidation region with no bird's beak or bird's head directly in contact with the groove, so a fault occurs between the trench and the field oxidation region. There is a drawback that a substrate with a flat surface cannot be realized. In addition, there is a point in improving the concentration as some crabs such as bird's beak remain. Furthermore, since adjacent patterns are formed using conventional groove-bun koji technology using exposure technology of There was a limit. Furthermore, when adjacent bags are made wider using conventional groove separation, there are also drawbacks such as the solution not being completely filled with dielectric material and the surface not being flat.

[Object and structure of the invention]

The present invention was made in view of the above circumstances, and its purpose is to provide a flat semiconductor 5rcf as a whole that can obtain an integrated circuit with a high degree of integration. An object of the present invention is to provide a substrate structure of L and a method of manufacturing a substrate structure of a semiconductor device in which such a substrate structure can be obtained through a simplified manufacturing process.

In order to achieve such an object, the substrate structure of the semiconductor device according to the present invention includes a field oxidation region between an element region selectively formed on a silicon substrate and a thick field condensation region in contact with the element region. A deep trench for isolation between elements is formed so as to be in direct contact with the semiconductor device, and this trench is filled with a silicon oxide insulating film, a silicon nitride insulating film, and a filler to form a flat surface as a whole.

In addition, in order to obtain such a tough structure, a self-aligned etching method is added to the uninvented manufacturing method for the substrate structure of a semiconductor device by using anisotropic etching for the butter/region covering the device region. After forming a deep adjacent trench for isolation between elements and sequentially forming a tJcm silicon insulating film and a silicon nitride insulating film within this trench, the remaining recess is filled with a filler material, and one of the trenches facing this trench is filled with a filling material. Prior to oxidizing the silicon substrate surface to form a field oxide film,
By etching the surface of the silicon substrate in the field oxidation region and removing the field oxide film up to the thickness of the field oxide film to be formed, the different surface is formed flat as a whole. Hereinafter, the present invention will be explained in detail using examples! 12 dawn.

〔Example〕

FIGS. 1(A) to 1(i) are process cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the present invention with a substrate present.

In the figure, first, for example, a layer with a thickness of 5 mm is placed on a silicon substrate 11.
0mf) forming a thermally oxidized silicon (sto,) test 12;
On this Sl02M12, a thickness of about 150a was applied using the method of G, etc.
m's silicone + 81aN4) Ilj! Then, on this Si3N4 film 13, silicon oxide 7 (810 m) with a thickness of about 600 m is formed by the G method or the like.

Here, a photoresist 15 having a thickness b is formed in a predetermined pattern on this 8101 film 14, and using this as a mask, reactive ion etching is performed using, for example, CHF5 gas to remove psio, film 14, and SlsN4M13.510.
The sNX 12 is sequentially removed to expose the silicon substrate 11. As a result, a desired isolation pattern between elements is formed (FIG. 1(a)).

Next, the resist 15 is removed under the conditions described above, and the entire surface is coated with silicon nitride: I
y (SisN+) film 16 is formed (IIEI Figure)
).

Next, 5iaN41416 is etched by reactive ion etching using C) iF8 gas until the silicon substrate 1 is exposed by an amount corresponding to the film thickness. Since reactive ion etching is used, the flat portion of the S'8N4 film 16 is removed, leaving a silicon nitride (S18N4) region 17 only at the step mlτ of the element isolation pattern. At this time, the width # remaining on the silicon substrate 11 of the 5isN4 region 1T
'': Almost equal to the film thickness of LS18N4/16, for example, in this case, it is about 500vn.Actually, it is 1diN
A 5lsN4 region 11 having a width of 100 to 500 (2) is formed by changing the thickness of the + dust 16. In this state, the exposed silicon substrate 11 is thermally oxidized to form a silicon oxide (8101) film 18 having a thickness of, for example, 300 days.

This SIO film 18 serves as a mask material layer when etching the silicon substrate 1 to form a groove later.
Figure 1 (C)).

Next, after removing the 5lsN4 region 11 by wrinkle etching with phosphoric acid or the like, for example, the silicon substrate 11 is etched by about 3cm by reactive ion etching using 51ct4 gas.
- Etching to form ridges 11& (Figure 1(d))
. The depth of this groove 111 is determined in relation to the inter-element withstand voltage required for isolation between elements in that portion. f! , 2 shows an example of this relationship. Unfortunately, the silico used to measure this property:/fi-JMB,,(111)P
- The red surface of a silicon substrate is doped with N+ ions and an N layer is epitaxially grown on it.

After the formation of the skin 11&, near the bottom of it, for example, the dose 1
x l Q"z+-', acceleration voltage 30 @V OhoH
Channel cut M*19 is formed by 74-on implantation, and 81
After removing the 0°Mlr by etching, the exposed silicon substrate 11 is removed by reactive ion etching using, for example, SIC gas by an amount equivalent to the thickness of the field enhancement film to be formed after the etching. .

After that, the exposed silicon substrate 11 and the groove 11 &
For example, by thermally oxidizing the inner surface of the silicon oxide (810 m) films 20 and 21 with a thickness of 50 mm and silicon nitride (:818 m) with a thickness of 150 mm, for example, by the method of reduced pressure G.
N4)! After forming 71122 on the entire surface, for example, by the method of reduced pressure G #)P! A filling material 23 made of a silicon oxide film, for example, is formed over the entire surface so as to fill the recess 11b' formed inside the 518N◆ film 22.
Figure 1-)).

Next, the filling material 23 is subjected to anisotropic reactive ion etching to remove the flat portion, and only the portion of the filling material 21/2 in which the recessed portion 11b is buried is removed. At this time, the filler 240 planting surface is one level higher on the left column, one level lower on the right side from the edge of the 5IBN4 membrane 22 in the electron separation area, and 811N in the field cultivation area.
4. A rounded slope is formed over the edge part K of the film 22. Then, the exposed Sl@N+ 111422 was removed by reactive ion etching, and the exposed 5i
The ns film 20 is etched until the silicon substrate 11 is exposed, and the film 14 is removed (810) (see FIG. 1(f)).
)).

Next, the exposed silicon substrate 11 is heated at 900° C., 8
Atmospheric pressure, 100 minutes of pyrogenic (pyregsn)
le) Thickness of about 1 mm to become wiring area by selective oxidation
A field oxide film 25 of .mu.m is formed. Field oxide film 25F thus formed! ,, is formed to approximately the same height as the upper surface of 5IOzl #12 covering the silicon substrate 11, and the substrate surface as a whole becomes approximately flat.

However, when forming this field oxide film 25, -
S on the part in contact with the groove 11a on the lower silicon substrate 11 side.
l, the N4 film 22 is exposed, and the original cross member 24
0 table rkI-tI: Field oxide film 25 forms a curved surface that descends toward the exposed portion, so field oxide film 25 is formed by filling material 21/
Cannot completely cross the top of 2, there is a slight dent fi + 11e
is 24 fillers and 1 ton of field oxidation! He often remains at the age of 25.

Therefore, in order to dig this recess ttdllc, a supplementary filling material made of a CVD silicon oxide film similar to the filling material 24 was formed on all songs, and then this filling material was field-etched using anisotropic reactive ion etching. The surface of the oxide film 250 is removed until it is exposed, leaving only the filling material 26 in the portion filling the recess 11. Finally, the 818N4 film 13 exposed on the element isolation region is removed by etching in a hot rinsing environment, so that the trench isolation portion is in direct contact with the thick field oxide film 25, and these trench isolation regions and the field oxide film 25 are removed. A substantially flat surface substrate structure is obtained in which the upper surfaces of the device region 25 and the element region are generally flat (FIG. 1-)). Thereafter, 5IOt*12 in the element region is removed and a desired element structure is formed there.

In such a substrate structure, the field oxide film 25 and the isolation region are directly molded, and the upper surface of the film is flat, so the width required for isolation is narrow, and it is easy to use for fixation. Another advantage is that wiring is easy. Furthermore, since the field oxide film 25 and the trench isolation region are separated in half by the short S1, 2N+M 22, which does not reach the surface of the substrate, the field oxide film 25 is short.
5 is excessively relaxed, and defects are less likely to occur in the element region. Therefore, characteristics such as hfa are less likely to deteriorate.

In the above-mentioned example, when forming the 5toi film 18, the film was heated at 900°C using the thick 51mN4 region IT as a mask.
If a 5tos film of 0.75 μm or more is formed by Couette oxidation, ζ crystal defects may occur in the silicon substrate 11. In order to avoid this, a method as shown in FIG. 3 may be used. That is, after obtaining the structures 1 to 1 shown in FIG. 1 6) in the same manner as described above, the resist 15
Remove the entire surface to a thickness of 5G+a using a reduced pressure method, for example.
After forming a silicon nitride (81xN4') pattern 21 with a thickness of less than m, a polysilicon pattern 28 with a thickness of about 500 mm is formed on it, for example by the same reduced pressure method (see Fig. 3(a)).
]). This polysilicon film 28 and 8111N4k
If 27 is used for a thick silicon nitride layer of 170s,
Since the silicon nitride film is only the M5iaN4 film 27, it is possible to prevent island defects from occurring within the silicon matrix 11.

In this case, 2g of polysilicon film! Similarly, a film made of other materials can be used as long as the film has excellent step coverage. For example, CvD cellulinated silicon film, sputtered At IA and other goldx8Q.

It is possible to use a polymeric material film such as Attie film, germanium oxide film, or photoresist.

Therefore, the polysilicon film 28 is removed by the thickness of the polysilicon film 28 by reactive ion etching to form a polysilicon region 29 (see Figure 3).

Next, using this polysilicon region 29 as a mask, 811
1N4 J[a Etch 27 and silicon substrate 1
Expose 1. Thereafter, the polysilicon region 2s is removed by etching, and the silicon base &11 is thermally oxidized using the remaining SL and N4 film 30 at the step portion as a mask to form a silicon oxide film 31 (see Fig. 3). C)) In this case, the stog is performed while leaving the polysilicon region 29.
[31 may be formed and then the polysilicon region 29 may be formed. Further, the Si8N4 conversion 30 may be used as long as it serves as a selective oxidation mask, for example, it can be used for mass oxidation, anodic oxidation, etc. When forming the film 31, 5lsN+
Instead of 1llk 3 G, an aluminum film or the like can be used. After this, 81. N.

The film 30 is removed and the same steps as shown in FIG. 1(d) and subsequent steps are performed.

In the embodiment described above, silicon oxide y (Si
It may also be a multi-Mlk structure with an Os) film interposed therebetween. This is shown in Figure 4. In other words, Fig. 4 shows a 5.
iaN*M! X2 T and thickness approximately 500! l! For example, the thickness is 70 nm between Q O Hori V 9 '37 g2B.
This is an example of adding 5105m32.

Furthermore, the step of etching the silicon substrate 11 in the field oxidation region shown in jfL1t9(·) is performed by etching the trench 11.
It can also be carried out directly before forming the structure shown in FIG. 1(a)K. An example is shown in FIG. That is, as shown in FIG. 1(a), the 8102B12.5hN4 film 13 and 5lo formed on the silicon substrate 11
T! A'J 14 is etched by reactive ion etching using CF4 gas using the photoresist 15 as a mask, and 5 IC is etched on the exposed silicon substrate 11.
Reactive ion etching using T4 gas is performed to remove the field oxide film to about the thickness of the field oxide film (Figure 5(a)).
).

Thereafter, after removing the photoresist 15, the photoresist 15 is removed using, for example, the reduced pressure method in the same manner as in the example shown in Figure 4.
A 33. The 3101 film 34 and the polysilicon film 35 are formed to have thicknesses of 30 nm, 100 mm, and 570 mm, respectively (Fig. 5).

In this state, the polysilicon film 35 is removed by reactive ion etching using S to remove only the stepped portion, and then the exposed 810sWX34 is removed using hexafluoric acid using the remaining polysilicon area as a mask. After that, the polysilicon region was removed, and the remaining 5IOsIA 34 was used as a mask to remove the Si 1IN4 film 33 with hot rinsing and sanding. Furthermore, the 5tosIa 34 was removed with hydrofluoric acid to form Sl 3N and film 36 only on the stepped portions. form. This 813
N, the width of the membrane 36 is Si3N, the film 33, SinsgG1
The total film thickness and fl of the polysilicon layer 34 and the polysilicon layer 35 are approximately 700 nm here. Then this 5lBN
4. When thermal oxidation is performed using AG436 as a mask, a silicon oxide (810 g) film 31 with a thickness of, for example, 300 days is formed (FIG. 5(C)).

After removing the 81xN4WA 36 by etching with phosphoric acid or the like, the silicon substrate 11 is etched by about 3 μm by reactive ion etching to form a groove 11m, and boron ions are implanted at the bottom to form a channel cut region 38. form (@Figure 5 (d)).

After removing the sand by etching the 5 lot film 3T, for example, a thermally oxidized silicon film (810,) with a thickness of about 50 nm @39
and 40 and K, for example, forming a vacuum silicon nitride l'518N4) with a thickness of 150 mm, and further forming a filler material 4 made of silicon oxide with a thickness of 400 u, for example.
2 (@Figure 5 (・)).

Next, fill the materials 42 and 8 by reactive ion etching.
111N4 Remove an amount equivalent to the thickness of the membrane 41 and fill it 43
Further, the StO film 38 is removed by 9-etch etching, and the Sly film 14 is removed.
7i7.5 (b) (f)).

Next, the exposed silicon substrate 11 is selectively immersed using the piezogenic method to carve field oxide G44, and the remaining recesses are filled with supplementary filler material 45 to form 1lkveK Sl.
8N4 MA 13 is removed with hot phosphoric acid (Figure 5-)
).

When it is possible to form even finer patterns, in addition to the formation of a thick field oxide film of approximately 2 or more fine lines and a deep skin as described above, a pattern of approximately IJt as shown in IIT61Sp, l can be formed.
It is possible to create an isolation structure within the element region using a trench as shallow as 100 m. This will be explained next.

First, thermal oxidation silicon (Sin) is deposited on the silicon substrate 46.
s ) film 41, silicon nitride (81sN4) film 48 and cvp dispersion silicon (810s) IJ 4 ! 1
A photoresist (not shown) having a predetermined pattern formed by KICt is used as a mask to perform etching, so that the surface of the silicon substrate 46 is exposed obliquely. As a result, a desired element isolation pattern is formed, but in this case, a shallow i[-Sin! Membrane 49.5 is N4 membrane 48 and si
o, a through hole 5G penetrating the membrane 41 is also formed at the same time.

Konoto'! , 5ins a47.5liN+ Ia 4
B's? and the thickness H of the 5tO1 film 49 is the same as that of the through hole 5.
It is also necessary to increase the 00 width, that is, the #IAW width of the shallow groove to be formed. Next, silicon nitride (8111N4) II 51 and polysilicon film 52 are deposited on the entire surface (@6 (a)).

Next, reactive ion etching is performed on the polysilicon 1152, leaving only the polysilicon region 53 at the stepped portion and the buried polysilicon region 51/2 in the through hole 50 (
Figure 5(b)).

Next, using the polysilicon regions 53 and 54 as masks, 81a
The N4 film 51 is removed by etching to expose the surface of the silicon substrate 460 (FIG. 6←)).

Next, a portion corresponding to the thickness of the polysilicon film 52 is etched by wet etching to remove the polysilicon oxide film 53, leaving the polysilicon region 55 in the through hole 50 (
@Figure 6 (d)).

Next, the exposed silicon substrate 46 is oxidized, and at the same time,
The polysilicon' (I-) in the R through hole 50 is oxidized to form a thermally oxidized silicon (SIOl) film 56 and a polysilicon oxide film 51. Thereafter, a deep #46a for isolation between elements is etched by reactive ion etching. form (Fig. 6(・)).

Then 5laN4@S1 on the surface forming shallow grooves
Then, the polysilicon oxide film 51 and 510mff 149 are removed by etching. S10! Since the film 49 is formed thicker than the other films, a portion thereof remains without being removed. Thereafter, after etching the shallow trench 58 and the silicon substrate 46 in the field oxidation region at the same time, a channel cut region 59 is formed by ion implantation (FIG. 6(f)
)).

Hereinafter, silicon oxide (810,) film 6G, silicon nitride 181
8N4)! After placing a filling material 62 made of A 61 and silicon oxide and forming a thick field oxide 8I 63, the recess is filled with a supplementary filling material 64, and finally the Sl, N, and film 48 on the device region are removed. By this, the first
1b(g), a PI3-like structure is formed (Fig. 6-)).

The seventh figure shows a structure in which a bipolar transistor is formed on the M base of the isolation region thus completed. Arsenic is diffused over the entire surface of the pubstrate 66 to a surface concentration of 1×10 19 ω-3 to form a single layer 6T that will serve as a collector salt layer, and on top of that a layer of 6T with a thickness of approximately Silicon layer 68t-
It is made by growing Evita medium-sized mushrooms. After each element is engaged, it is divided by the trench isolation region, so the n
+The buried layer does not need to be formed independently using a mask having separate patterns in advance, and may be formed over the entire surface in this way. Further, 69 is a p'' channel cut region, 7G is a field oxide film with a thickness of about 1gn, 71 is silicon oxide (Sins) formed on the inner wall of the deep groove and shallow trench for element isolation, and 72U is this 5IOtl!47.
1, 73 is a filling material, 74 is a supplementary filling material, 75 is an n+ diffusion layer, 76 is a + diffusion layer, TT to 79 are base, emitter, and collector layers, respectively. Tani' + t (else.

Additionally, this structure can also be used on SOI (silicon on insulator) substrates. The structure in that case is shown in Figure 8. In the figure, 80 is an insulating substrate. Instead of an insulating substrate, a buried insulating layer formed in a silicon substrate may be used.

7 and 8 show the case where a bipolar transistor is formed in the element region, but other than that, ~[)S)U7
Of course, an element such as a transistor (0MO8) transistor may also be formed.

In the substrate floating structure described above, the inter-element reverse breakdown voltage is approximately 18V, and for example, when a bipolar LSI is fabricated in the element region, the voltage is approximately three times or more than the operating voltage of 5V. It was confirmed that pressure resistance could be achieved. Note that this withstand voltage can be further increased by increasing the depth of the groove as shown in FIG.

Furthermore, when crystal defects in the device region were examined by dilt etching, it was confirmed that no crystal defects that would cause deterioration of the cable properties were generated during device filling.

In addition, in the example 5A# explained above, as a filler, for example, C
Although the case where an insulator such as a VD silicon oxide film is used has been described, the present invention is not limited to this.
In addition to insulators, polysilicon, semi-insulating materials, conductive materials, etc. can also be used as the filler. Here, as the semi-insulating material, for example, silicon oxynitride < s 1,0. , N, ), Omushigen-doped polysilicon, silicon nitride (81&N,
), etc., and the conductive material is a high melting point metal such as W*Pt. When using conductive fillers such as polysilicon, semi-insulating materials, or conductive materials, it is possible to reduce charges caused by radiation irradiation, etc., and improve environmental resistance. Strong elements can be manufactured. In this case, the filling material is approximately l
It is desirable that the material has a resistivity of less than 0 Ω·-, and the above-mentioned semi-insulating material is enshrined in a known manner to have such a resistivity value.

〔Effect of the invention〕

As explained above, according to the present invention, the deep tiles for element isolation filled with the dS piece electric body and the filler material and the thick field oxide film can be formed in a self-aligned manner. Because there are almost no bird's beaks or bird's heads in the area, the thick field oxide film is in direct contact with the deep layer, and the flat shape allows for a structure with a high level of integration to be easily obtained.

In addition, the width of the deep groove is not limited by the limits of exposure technology and can be controlled by the thickness of the film subjected to anisotropic etching, making it suitable for miniaturization. Shallow trenches and thick field oxide films in the device region can be formed in a self-aligned manner, eliminating the conventional problems of parasitic capacitance, parasitic cavities, and surface steps (bird's heads) caused by mismatching with the field. structure can be obtained. For this reason, Iku's metropolitanization, oxidation to high #, simple step I
Ivshi transformation! I can make maggots.

Furthermore, according to the present study, finely separated koji is used in which a fine-width tsuba, a thick field oxide film, and a shallow groove are formed in a single pattern around the device region, and the red face is flat and no pattern conversion difference occurs. structure can be formed. In addition, since no buried layer pattern is required, bipolar, 0MO8 and Bt-
The speed and power consumption of elements such as MOS can be increased and power consumption reduced.

[Brief explanation of drawings]

Fig. 1 (1k) to -) are process cross-sectional views showing one embodiment of the present invention, Fig. 2 is a diagram showing the relationship between the depth of the groove for isolation between elements and the withstand voltage between elements, and Fig. 3 -) -(e) are process sectional views showing other embodiments of the present invention, 1#X4 drawings are sectional views showing still other embodiments of the present invention, and Fig. 5(a) - ω 6(a) to (x
) is a process cross-sectional view showing still another embodiment of the present invention, and Figures 1, 7, and 8 are cross-sectional views showing an example of a semiconductor device formed using the substrate structure of one embodiment of the present invention, respectively. be. 11.46.65...Silicon substrate, l1m, 46
Hatake...Deep monument, 11b, 11e...Concavity, 12
,14°18.20,21.31.39.40.47,
49, 56.57° 60.71 ... Silicon oxide film, 13, 22, 27° 37.41.4g, 51.6
1.72...Silicon nitride film, 17, 30
, 36 , 53 , 54 ... silicon nitride region,
23 , 24 , 42 , 43 , 62 , 73
... Filler (@1 filler), 25, 44, 63.7
0...Field oxide film, 26.45, 64.74
... Filler (8g2 filler), 50 ... Through hole, 58 ... Shallow groove, 6T ... 1 layer (silicon substrate), 68 ... N-type silicon layer (Silene group [)
. Figure 1 Figure 4 Figure 2 Figure 6

Claims (4)

[Claims] (1) Using anisotropic etching and a step of forming a pattern region with a multilayer structure consisting of each layer having different etching characteristics on the silicon substrate in the element formation region,
a step of forming a thin film region of a predetermined width on the surface of the silicon substrate in a self-aligned manner adjacent to the pattern region; A step of forming an etching mask material layer with different etching characteristics, a step of etching the silicon substrate exposed by removing the thin film region to form a deep and narrow groove for isolation between elements, A step of etching the surface of one of the silicon substrates facing the trench to remove a portion approximately half the thickness of the field oxide film to be formed, and etching a silicon oxide insulating film and a silicon oxide insulating film along the inner wall of the deep trench. After sequentially arranging the silicon nitride insulating films, there is a step of filling the formed recesses with a filling material, and a step of filling approximately 1/2 of the field oxide film to be formed.
forming a field oxide film by oxidizing the surface of the silicon substrate that has been removed to a thickness of A method for manufacturing a substrate structure of a semiconductor device. (2) A step of forming a multilayered pattern area consisting of layers each having different etching characteristics on the silicon substrate in the element formation area, and a field to be formed by etching the surface of the silicon substrate using this pattern area as a master. A thin film region of a predetermined width was etched in a self-aligned manner adjacent to the pattern region using a step of removing the oxide film to a thickness of about 1/2 and anisotropic etching. A step of forming an etching mask material layer on the surface of a silicon substrate, a step of forming an etching mask material layer having etching characteristics different from that of the silicon substrate on the exposed surface of the silicon substrate other than this thin film region and the patterned region, and removing the thin film region. The process involves etching the exposed silicon substrate to form a deep and narrow groove for isolation between elements, and sequentially placing a silicon oxide insulating film and a silicon nitride insulating film along the inner wall of this deep trench. rear,
The method includes a step of filling the formed recess with a filling material, and a step of oxidizing the surface of the silicon substrate, which has been removed to a thickness of about 100 yen of the field oxide film to be formed, to form a field oxide film. 1. A method of manufacturing a substrate structure of a semiconductor device, comprising forming an element isolation region and a field oxidation region substantially flat with respect to a region. (3) A step of forming a pattern region with a multilayer structure consisting of layers each having different etching characteristics on the silicon substrate in the element formation region, and using anisotropic etching,
a step of forming a thin film region of a predetermined width on the surface of the silicon substrate in a self-aligned manner adjacent to the pattern region; A step of forming an etching mask material layer with different etching characteristics, a step of etching the silicon substrate exposed by removing the thin film region to form a deep and narrow groove for isolation between elements, A step of etching the surface of one of the silicon substrates facing the trench to remove a portion approximately half the thickness of the field oxide film to be formed, and etching a silicon oxide insulating film and a silicon oxide insulating film along the inner wall of the deep trench. After sequentially arranging the silicon nitride insulating films, a step of filling the recesses formed inside the silicon nitride substrate with a first filling material, and a step of filling the silicon nitride insulating films to a thickness of about 1/2 of the field oxide film to be formed as described above. A step of oxidizing the surface of the substrate to form a field oxide film, and a second filling of the recess formed between the field oxide film, the silicon nitride insulating film disposed in the deep trench, and the first filling material. 1. A method of manufacturing a substrate structure of a semiconductor device, comprising: filling the substrate structure with a material, and forming an element isolation region and a field oxidation region substantially flat with respect to an element region. (4) A step of forming a multilayer structure pattern region consisting of each layer having different etching characteristics, each having a through hole in a part, on the silicon substrate in the element formation region, and using anisotropic etching to remove the above pattern. A step of forming a thin film region of a predetermined width on the surface of the silicon substrate adjacent to the region in a self-aligned manner, and etching characteristics of the silicon substrate exposed outside the thin film region and the pattern region. a step of forming etching mask material layers with different thicknesses, a step of etching the exposed silicon substrate by removing the thin film region to form a deep and narrow groove for isolation between elements, and a step of forming a deep and narrow groove for isolation between the elements, and a step of etching the exposed silicon substrate by removing the thin film region; and a step of etching the surface of one silicon substrate facing the deep groove to remove approximately 1/2 the thickness of the field oxide film to be formed, and etching the silicon oxide along the inner wall of the deep groove. After sequentially arranging the insulating film and the silicon nitride insulating film, there is a process of filling the formed recesses with a filler, and oxidizing the surface of the silicon substrate, which has been removed to a thickness of about 100% of the field oxide film to be formed. 1. A method of manufacturing a semiconductor substrate structure, the method comprising: forming a field oxide film using a shallow groove, and forming an element isolation region and a field oxide region substantially flat with respect to an element region having a shallow trench.