JPH03171087A - Image processor - Google Patents

Abstract

PURPOSE:To allow the execution of the software of a personal computer without emulation by providing a control circuit which has two memories and executes the control of frequencies at the time of writing and reading out and the timing adjustment of input and output. CONSTITUTION:The control circuit 6 which has at least the two memories to store one line selects the memories 8, 9 to execute the reading out and writing and writes low-resolution data at the dot clock synchronized with the horizontal and vertical synchronizing frequencies outputted by the low-resolution data at the time of writing of the data. The circuit reads out the data synchronized with the horizontal synchronizing frequency with which a display 7 of a high resolution, i.e. the output destination of images at n-times (n is >=2 natural number) at the time of the writing and outputs the one line of the same image n-times, thereby adjusting the timing of the input and output at the time of the reading out. The software of the personal computer is executed in a native mode in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image processing device that displays an image signal for a low resolution display on a high resolution display.

Conventional technology Today, typical workstation CRT displays have a resolution of 1.280 dots horizontally and 10 dots vertically.
24-line displays are standard, and workstations with high-resolution displays like Anko are used for development purposes, but recently they have also started to be used in the business field.

On the other hand, the resolution of a typical CRT display of a personal computer for business use (640 dots horizontally, 400 lines vertically or 480 lines). The data is very useful.

Therefore, the desire to run existing personal computer application software on workstations becomes increasingly problematic due to differences in display resolution. Previously, the workstation side emulated the software for personal computers and displayed the personal computer screen software in one window on the workstation. The power of compatible auto-tracking type displays that have been put into practical use.The auto-tracking range is approximately 10 to 13 kHz in horizontal frequency.High-resolution CRT displays with a horizontal resolution of 1280 dots are used in workstations, etc. The standard horizontal frequency is 64 kHz, while the horizontal resolution used in personal computers is 640 kHz.
Even if the horizontal frequency is high on a dot low-resolution CRT display, the horizontal frequency is around 26 kHz, so even if a high-resolution auto-tracking display is used, the horizontal frequency will be around 26 kHz.
Problems to be Solved by the Invention As stated above, high-resolution CRTs for workstations cannot display
When displaying software for low-resolution personal computers on the display, the workstation emulates the low-resolution software.
A system that displays windows as a window has been put into practical use, and emulation processing takes a considerable amount of time.
In addition, when using interactive graphics software (response speed becomes slow and impractical), low-resolution application software directly accesses the personal computer's video RAM to speed up processing. cannot be displayed using this method (1) The present invention solves the above problems.
Means for Solving the Problems Although the object is to provide an image processing device that displays an image signal for a low resolution display on a high resolution display, in order to achieve the above object, the image processing device ζ of the present invention has at least two An image processing apparatus according to another invention includes a memory, a control circuit for controlling at least the frequency during writing and reading, and adjusting the timing of human output. It is equipped with a switching means for switching between.

Further, an image processing device according to another invention is equipped with a register for switching the above-mentioned switching means.According to the present invention, with the above structure, data for a low resolution display is displayed on a high resolution display. Tokisaka Data is written and read in synchronization with the horizontal synchronization frequency and dot clock frequency at which low-resolution image data is output, or with a frequency that is 1/n (n is a natural number of 2 or more) of the high-resolution display frequency. Time C-t Read with horizontal synchronization frequency n times the time of writing The frequency of the dot clock is a frequency that can synchronize a high-resolution display, and the number of horizontal pixel dots of the low-resolution data is one period of the horizontal synchronization frequency when output Convert to the frequency included in the data and read it.Use at least two memories.
Read n@ data from another memory that has already been written at n times the frequency in row 1. X. It is possible to display video data for a low resolution display on a high resolution display by controlling the input/output timing. Embodiment Figure 2 shows the horizontal display timing of a non-interlaced CRT display with 640 horizontal pixels and 400 vertical display lines used in a personal computer, and the horizontal synchronization frequency is 26.4kHz, 640 dots are displayed in one horizontal period.

Figure 3 shows the horizontal display timing of a non-interlaced CRT display with 1280 dots of horizontal display pixels, 1024 vertical display lines, and a horizontal synchronization frequency of 63.7kHz.
1280 dots are displayed in the horizontal period.

In order to display a low-resolution image with a horizontal synchronization frequency of 26.4kHz on a high-resolution display with a horizontal synchronization frequency of 63.7kHz, as shown in Figure 4, video data of 640 dots for one line of the low-resolution image is displayed at a horizontal frequency of 26.4kHz.
It is displayed at 52.8kHz, which is twice the frequency of z. At this time, since the readout frequency is doubled, the same data is displayed two dots at a time on the display. Therefore, when in low resolution native mode (friend horizontal frequency 5
1280 dots are displayed in one horizontal period at 2.8 kHz.

After displaying 1280 dots for 1 line with 640 data 2 dots at a time, the same line data is displayed again 2 dots at a time in the same way as before. When two lines of the same line are displayed, the next line's worth of 640 dot data is displayed two dots at a time on the line next to the line just displayed. Therefore, in low resolution native mode, 800 lines are displayed in one vertical period at a vertical frequency of 60 Hz.

In the case of a low resolution image with 480 vertical display lines (
960 lines are displayed in one vertical period.

The horizontal synchronization frequency in the high resolution mode of 1280 dots x 1024 lines is 63.7kHz, and the horizontal synchronization frequency in the low resolution native mode is 52.8kHz, so the difference in frequency is 10.9kHz, CRT displays capable of auto-tracking in this frequency range have already been put into practical use.

Regarding the vertical frequency, it is 60 Hz in both low resolution native modes, so there is no problem. Therefore, if you connect a display that can support these two types of horizontal synchronization frequencies, you will get a low resolution of 640 dots x 400 lines. Images can be displayed on a high-resolution display on a workstation.

In Figure 1, l is the original 1280 of the workstation.
In the high-resolution image control circuit section that controls the display of a high-resolution image of 1024 lines of dots, video signals of green and blue (hereinafter referred to as RED, GREEN, and BLUE video signals) are output at a horizontal synchronization frequency of 63.7 kHz. too
The output is a single operation of the video signal changeover switch 11, and a synchronizing signal is superimposed on the video signal of Namo GREEN.

3, 4, 5 are REDX GREEN, BL respectively
Circuit block compatible with UE, low resolution l line 6
It consists of first and second line memories 8, 9 consisting of FIF◯ that stores 40 dots, a D/A converter 10, and a video signal changeover switch 11. The video signal from the low-resolution block is a 4-bit, 16-gradation buffer.
For monochrome, it is 1 bit, and for 256 gradations, it is 8 bits.

2 is a low-resolution image control circuit unit that displays a low-resolution image of 640 dots x 400 lines; 4RED, GREEN;
, BLUE video signals before D/A conversion are input to each circuit block.

6 is a timing control section that selects the first and second line memories, writes the video data from the low-resolution image control circuit section 2 into the first and second line memories 8 and 9, and controls the read timing. be. 22. 8
The MHz dot clock is supplied from this timing control section 6, and 7 is supplied to the RED circuit block 3 and the GREEN circuit block 4.
, the horizontal synchronization frequency from each circuit block of the BLUE circuit block 5 is 63.7kHz, and the vertical synchronization frequency is 60Hz.
Non-inklace 1 280 dots x 1024 lines high resolution video data or ζ Horizontal synchronization frequency 5
It is a dual auto-tracking display that automatically responds to 1280 x 800 lines of non-interlaced video data with a vertical synchronization frequency of 60 Hz and a frequency of 2.8 kHz.

This dual auto-tracking display 7 can switch between two frequencies by manual setting. Next, the function of the timing control section 6 will be explained.

The start of the l-th line of the video signal can be known by the negation of the vertical synchronization signal VSVN from the timing control unit 6 (low-resolution image control circuit unit 2) and the negation of the BLNK signal indicating the blanking period.

When the lth line is written to the first FIF○ line memory 8, the timing control unit 6 resets the write address of the first FIF○ line memory 8 using the terminal RSW.
and enable the write enable terminal WE of the first FIF○ line memory 8.

The video data from the low resolution image control circuit section 2 is connected to the dot clock DTCL supplied from the timing control section 6.
K22. Since it is output in synchronization with 8 MHz, this clock is used as the write clock WCK of the first FIFO line memory 8.

When the BLNK signal from the low resolution image control circuit section 2 is asserted, the timing control section 6 disables the write enable terminal WE of the first FIF○ line memory 8.

In this way, from the first dot data of one line, 64
0 dots are stored in the first FIF○ line memory 8.

Similarly, for the second line, the horizontal synchronization signal HSY from the low-resolution image control circuit section 2 is
The start of the second line can be known by the negation of NC and the negation of the BLNK signal indicating the blanking period, and the second line is written into the second FIF◯ line memory 9. The timing control unit 6 enables the terminal RSW for resetting the write address of the second FIFO line memory 9, and enables the write enable terminal WE of the second FIFO line memory 9. The following is the same as writing to the first FIFO line memory 8, and the same applies to the third and subsequent lines.One line 64 of the low resolution image
0 dots are alternately stored in the first FIF○ line memory 8 and the second FIF○ line memory 9.

As shown in FIG.
Assert HSYNC to EEN circuit block 4. After a predetermined time, GREEN circuit block 4
After a predetermined back porch, enable the reset terminal RSR of the read address of the FIF○, enable the read enable terminal RE of the first FIF○ line memory 8, and read the Llth line.

The read clock RCK is 2 times the write clock WCK.
Read out at 45.6MHz, which is twice as high as 45.6MHz h D/A converter 10
The signal passes through the video signal changeover switch 1l and is displayed on the dual auto-tracking display 7. 640
After a predetermined front porch after dot display is completed, the read permission terminal RE of the first FIFO line memory 8 is disabled.

The time width of HSYNC to GREEN circuit block 4 and the total time of back porch and front porch (horizontal synchronization period is predetermined to be 52.8 kHz, and counted by the counter of timing control section 6, after that, the back porch is calculated in the same way. Pouch, horizontal synchronization period After the front porch, the same line is read out from the FIFO line memory 8 of 2- again using the same protocol.

The reading of the first line from the first FIFO line memory 8 and the storage of the second line from the second FIFO line memory 9 are performed simultaneously.

Since the read cycle from the first FIF○ line memory 8 is 52.8 kHz, which is twice the write cycle to the second FIF○ line memory 9, when two cycles are completed, the second FIFO line memory 9 The write cycle to has completed.

Next, the third line of video data from the low resolution image control circuit unit 2 is stored in the first FIF○ line memory 8. The following lines are stored in one line memory using the same protocol, while the other lines are stored in another line memory.
Read and display at twice the frequency.

As described above, by using the image processing apparatus according to the embodiment of the present invention, it is possible to use software for a personal computer without emulating it, and it can be executed on a workstation without reducing the execution speed. In addition, one dot of low-resolution video data is divided into two dots vertically and two dots horizontally. In other words, since it is displayed on a high-resolution display using 4 dots, a screen with the same aspect ratio can be reproduced. Furthermore, the screen is easier to see than the conventional method of displaying windows in fixed sections, and it also uses high-resolution C for workstations.
Eliminates the need to have two types of RT displays and low-resolution CRT displays for personal computers,
This also leads to space saving on the workbench.

In this example, the data is read at the frequency at which low-resolution image data is output, and the data is output to the high-resolution display at twice the frequency at which it is read. When outputting to a high-resolution display by reading the data at half the frequency when reading the data (it is also possible to output at twice the frequency at the time of reading. In this example, the high-resolution display that is the output destination) By doing this, the output destination high-resolution display does not need to have an auto-tracking function. The power of outputting two lines of the same data at the frequency t Furthermore, for high-resolution displays ('!, it is possible to cope with this by multiplying the frequency by n (n is a natural number) and outputting Ln lines (1 Invention) As is clear from the above embodiments, the present invention allows software of a personal computer to be executed in a native mode in a workstation whose horizontal display resolution is n times that of a personal computer (n is a natural number). becomes possible.

Furthermore, since the software of the personal computer can be executed without emulating it, the effort required for emulation can be reduced and time can be saved.

[Brief explanation of the drawing]

Figure 1 is a block diagram of an image processing device according to an embodiment of the present invention; Figure 2 is a low resolution C
A timing chart showing an example of the horizontal timing of an RT display. Fig. 3 is a timing chart showing an example of the horizontal timing of a high-resolution CRT display of a workstation. Fig. 4 shows a timing chart showing an example of the horizontal timing of a high-resolution CRT display of a workstation. Fig. 4 shows a low-resolution image of Fig. A timing chart showing the horizontal timing when displaying on the auto-tracking display. FIG. 5 is a timing chart showing the horizontal display timing in the low resolution native mode. 1... High resolution image control cycle 2... Low resolution image control cycle 3... RED circuit block 4... GREEN circuit block 5... BLUE circuit block 6... Timing system 'a Hunger 7...Dual auto tracking display, 8
...First FIF○ line memory, 9...Second F
IF○ line memory, 10...D/A conversion switch 1 1...Video signal changeover switch.

Claims (3)

[Claims] (1) at least two memories storing one line;
Select a memory for reading and writing, and when writing low-resolution data to the memory, write with a dot clock synchronized with the horizontal and vertical synchronization frequency at which the low-resolution data is output, and when reading, the dot clock is n times that of writing. (n is a natural number greater than or equal to 2) and is read out using a dot clock that is synchronized with the horizontal synchronization frequency that can be synchronized with the high-resolution display that is the image output destination, outputs one line of the same image n times, and adjusts the input/output timing. An image processing device equipped with a control circuit that performs (2) at least two memories storing one line;
When selecting a memory to read from and write to, and writing low-resolution data to the memory, set the horizontal sync frequency to 1/n (n is a natural number of 2 or more) of the horizontal sync frequency of the high-resolution display that is the image output destination. It is equipped with a control circuit that writes with a synchronized dot clock, reads out with a dot clock synchronized with the horizontal synchronization frequency of the high-resolution display, outputs one line of the same image n times, and adjusts the timing of input and output. image processing device (3) The image processing device according to claim 1 or 2, further comprising switching means for switching between a low resolution video signal and a high resolution video signal at the signal output end. (4) A low resolution image mode and a high resolution image mode. 4. The image processing apparatus according to claim 3, further comprising a register for setting the selection of and storing the set value.