JPH03179491A - Memory access system for display - Google Patents

Abstract

PURPOSE:To reduce the current consumption by assigning an access cycle of a KANJI(Chinese character) code for a memory when attribute data does not indicate a display of KANJI, and setting one access cycle of the KANJI code for every N cycles and assigning the remaining cycles as read/write cycles of a processor when the attribute data indicates the display of KANJI. CONSTITUTION:When the attribute data does not indicates the display of KANJI, in a display control circuit 2, the access cycle of the KANJI code for the memory 7 is assigned as the read/write cycle of the memory 7 according to the indication of an assignment means 5. When the display of KANJI is indicated, on the other hand, one access cycle of the KANJI code for the memory 7 is set for every N cycles, the currently read KANJI code is held in a holding means 4, and the KANJI code held by the holding means 4 is used in the remaining (N-1) cycles to read a KANJI pattern out of a character pattern generating means 3. Then the remaining (N-1) cycles of the memory 7 are assigned as read/write cycles of the memory 7 for the processor 1. Consequently, the current consumption is reducible.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Actions Examples Effects of the Invention [Summary] Displaying ANK characters, kanji, etc. Regarding a display memory access method that prevents unnecessary access to display memory in devices, reduces current consumption, and increases the margin of access time. A memory that stores ANK codes, attribute data, and kanji codes, and ANK codes and attribute data or kanji codes are read out alternately from the memory, and when the attribute data read from the memory does not indicate the display of kanji, the ANK character pattern is , and when the attribute data instructs the display of kanji, a kanji pattern with an area N times the area of the ANK character is
In a device that uses N times as many cycles to display NK characters, a holding means holds the kanji code read from the memory, and an allocation means allocates the access cycle of the kanji code to the memory to the read/write cycle of the processor. If the attribute data does not instruct the display of kanji, the access cycle of the kanji code to the memory is assigned to the read/write cycle of the processor, and if the attribute data instructs the display of kanji, the kanji code access cycle to the memory is assigned. The access cycle is set once every N cycles, and the remaining (N-1) cycles are used for 81 read/write cycles of the processor.

[Industrial application field]

The present invention relates to a device that displays ANK characters, kanji, etc. on a display panel, and in particular prevents unnecessary access to display memory that stores character codes and attribute data, thereby reducing power consumption and increasing the margin of access time. This invention relates to a display memory access method that enables display memory access.

In recent years, with the spread of personal computers, word processors, etc., small and easy-to-carry portable devices have been developed, but these devices use batteries as power sources and display ANK characters, kanji, etc. on the liquid crystal display panel. There is something to do.

These devices store ANK codes, attribute data, kanji codes, etc. in one VRAM (video RAM), and continuously access this VRAM for display, but the display time of one screen is The speed at which flickering does not occur is generally set at 1/60 to 1/70 seconds, and there are restrictions on the access time to this VRAM.

Therefore, it is necessary that the access time to VRAM to read data for one screen is short, and
Since current is consumed every time M is accessed, the battery is consumed, but in order to extend the life of the battery, it is desirable that this current consumption be small.

[Conventional technology]

FIG. 4 is a diagram illustrating an example of the prior art.

Portable computers, etc. that display data on a liquid crystal display panel have only one VRAM in order to reduce current consumption and the volume in which memory is mounted, as shown in Figure 4 (
As shown in a), for example, an area where ANK codes and attribute data are recorded and an area where Kanji codes are recorded are allocated on the same memory.

The ANK code is 8 bits, the attribute data is also 8 bits, and the Kanji data is 16 bits. and,
VRAM is accessed in word units (16 bits).

When displaying characters using VRAM, a character generation circuit is used to read character patterns corresponding to the ANK code or Kanji code read from the VRAM, but in the case of ANK codes, the attribute code read at the same time is Based on the specified display method, for example, ANK character patterns are read out in 8-bit increments from the character generation circuit in synchronization with the scan timing of the liquid crystal panel.In the case of Kanji codes, the character generation circuit reads out the ANK character pattern in synchronization with the scan timing of the liquid crystal panel. Then, the Kanji character pattern is read out 8 bits at a time.

Therefore, for example, if the ANK character displayed on the LCD panel is 8 x 16 dots (8 horizontal dots and 16 vertical dots), the Kanji character is 16 x 16 dots, and the maximum number of dots in the line direction of the LCD panel is 640 dots. Then,
Up to 80 ANK characters are displayed, and 40 Kanji characters are displayed. And the time to display one kanji character is AN
It takes time for 2 K characters.

Also, by scanning 16 lines, one line of characters is displayed, but for this reason, for ANK characters it is necessary to read the same character pattern of the character generation circuit 16 times, and for Kanji characters, it is necessary to read the same character pattern of the character generation circuit 16 times. needs to be read 32 times.

For this reason, the number of accesses to the same character code on VRAM corresponds to the above number of times: 16 times are required for the ANK code and attribute data recording area, and 32 times are required for the kanji code recording area. , as shown in FIG. 4(b), in the cycle (■), A is stored in the address area on the VRAM corresponding to the display position on the liquid crystal display panel.
The NK code and attribute data are read out, the kanji code is read out in the ■ cycle, the ANK code and attribute data are read out in the ■ cycle, the kanji code is issued in the ■ cycle, and the processor reads in the ■ cycle. /write is performed, and this repetition is executed continuously.

When the Kanji display bit in the attribute data read in the cycle ■ is, for example, logic "1", the 8 pins read out from the character generation circuit are displayed on the LCD according to the Kanji code read out in the cycle ■. The ANK code sent to the display panel and read in the cycle 2 is ignored.

Also, when the kanji display bit in the attribute data read in the cycle (■) is logic "O", the 8 bits read out from the character generation circuit are displayed on the liquid crystal display panel by the ANK code read out in the cycle (■). The kanji code sent in the cycle ■ and read in the cycle ■ is ignored.

Similarly, when the Kanji display bit in the attribute data read in the cycle ■ is logic "1", the 8 bits read out from the character generation circuit are displayed on the liquid crystal display according to the Kanji code read out in the cycle ■. The ANK code sent to the panel and read in the cycle 2 is ignored.

Also, when the kanji display bit in the attribute data read in the cycle (■) is logic "0", the 8 bits read out from the character generation circuit are displayed on the liquid crystal display panel by the ANK code read out in the cycle (■). The kanji code sent in the cycle ■ and read in the cycle ■ is ignored.

Then, in the cycle (3), the display data is rewritten by the processor.

[Problem to be solved by the invention]

As mentioned above, conventionally, in order to read data for two ANK characters or one character for Kanji from VRAM, a 4x3
2 cycles and 1×32 cycles are allocated for data rewriting, and if 400 kanji characters are to be displayed on the liquid crystal display panel, there is a margin for the above-mentioned access time constraints for VRAM to prevent flickering. The problem is that there are almost no

Also, all data is read from the VRAM, and unnecessary data is ignored. For example, even if it is not necessary to display a kanji character, the kanji code is read and ignored, but this causes unnecessary access to VRAM, and this access generates wasted current consumption. There is a problem with doing so.

Furthermore, when displaying kanji, the kanji code read in the cycle ■ and the kanji code read in the cycle In the ■ cycle, read the kanji code necessary to read out the 8 bits that represent the pattern on the right half of the kanji from the character generation circuit.Therefore, if the same kanji code is Therefore, the number of accesses in the cycle (2) is limited to the number of copies, and there is also the problem of wasteful current consumption.

In view of these problems, the present invention allocates the cycles of ■ and ■ for reading the kanji code to the read/write cycle of the processor, deletes the cycle of ■, and displays the kanji when it is not necessary to display the kanji. When displaying, by assigning the ■ cycle that reads the same kanji code to the read/write cycle of the Prosensor and deleting the ■ cycle,
The purpose is to reduce current consumption and increase the margin of access time to VRAM.

[Means to solve the problem] FIG. 1 is a diagram explaining the present invention in detail.

Based on the address and data sent by the processor 1, the display control circuit 2 stores the ANK code, attribute data, and Kanji code in the memory 7 as shown in FIG. 4(a). Then, the ANK code and the attribute data or the kanji code are alternately read out from the memory 7, and when the attribute data read out from the memory 7 does not instruct the display of kanji, the character pattern generating means 3 is generated based on the read out ANK code. The read ANK character pattern is sent to the display panel 6 for display, and when the attribute data indicates the display of kanji, the character pattern generating means 3 is sent based on the read kanji code.
A kanji pattern having an area N times larger than that of the ANK characters read from is displayed on the display panel 6 using N times the cycle of ANK character display.

At this time, if the attribute data read from the memory 7 does not instruct display of kanji, the display control circuit 2 controls the allocation means 5
According to the instruction, the access cycle of the kanji code to the memory 7 is changed to
When assigned to a write cycle and the attribute data instructs to display a kanji, the kanji code is accessed once every N cycles to the memory 7, and the kanji code that is successively displayed at this time is held in the holding means 4. , the remaining (N-
1) The cycle reads a kanji pattern from the character pattern generation means 3 using the kanji code held by the holding means 4. The remaining (N-1) cycles for the memory 7 are allocated to read/write cycles for the memory 7 by the processor l.

[Effect]

By configuring as described above, when displaying a kanji is not necessary, the access cycle to the memory 7 for reading the kanji code is allocated to the read/write cycle of the processor 1, and even when displaying a kanji, the same kanji It becomes possible to allocate the access cycle to memory 7 for reading the code to the read/write cycle of processor 1, so it is possible to delete the read/write cycle for memo 'J7, which was previously allocated to processor 1. I can do it. Therefore, it is possible to reduce current consumption and increase the margin of access time to the memorandum.

〔Example〕

FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention.
FIG. 3 is a time chart explaining the operation of FIG. 2.

The cycle switching circuit 17 controls the selector 21 based on the clock sent out by the clock generation circuit 10 and the timing created and sent out by the display access timing generation circuit 9, and controls the select and read command generation circuit 18. The memory 7 is caused to send a chip select signal and a read command to the memory 7 to be sent.

Then, it sends an address increment signal to the display address counter 19, controls the selector 20, and causes the display address counter 19 to sequentially increment and send out the display address based on the address increment signal to the memory 7. .

That is, first, in the cycle shown in FIG. 3 (3), the start address of the ANK code and attribute data recording area of the memory 7 as shown in FIG. 4 (a) is sent to the memory 7.

The ANK code and attribute data sent out from the memory 7 by the address sent by the display address counter 19 are latched by the latch circuits 15 and 16, and the kanji display bit in the attribute data latched by the latch circuit 16. is checked by the kanji display presence/absence determination circuit 12, and if it is logic “L”, the ANK latched in the launch circuit 15 is checked.
No code is sent to the character generation circuit 13.

However, if the kanji display bit checked by the kanji display presence/absence determination circuit 12 is logic "0", the latch circuit 1
The ANK code latched at 5 is sent to the character generation circuit 13, the ANK character pattern corresponding to this ANK code is indexed, and 8-bit data in the line direction of the display panel 6 is sent to the drive circuit 14.

At this time, based on the clock sent out by the clock generation circuit 10 and the timing created and sent out by the display access timing generation circuit 9, the drive circuit 14 sends out 8-bit data to the display panel 6, and the display panel 6 Displays 8 bits in the line direction.

The kanji display presence/absence determination circuit 12 has a kanji display bit of logic “0”.
”, processor accessible timing generation circuit 1
1 that access to the memory 7 of the processor 1 is possible, and the processor accessible timing generation circuit 11 notifies the display access timing generation circuit 9 that the processor 1 can access the memory 7.
Based on the timing of sending to the drive circuit 14, the data passes through the processor read/write timing adjustment circuit 8, and
The processor l is caused to send a signal permitting access to the memory 7.

At the same time, the processor accessible timing generation circuit 11 instructs the cycle switching circuit 17 to select the selector 2.
0 and 21, the address bus of the processor 1 is connected to the memory 7, and the signal line 22 for transmitting read/write commands sent by the processor 1 is connected to the memory 7. And display address counter 19
Stop sending the address increment signal sent to

When the processor 1 needs to change the display content on the display panel 6, it tries to access the memory 7, but it waits for this access until the processor read/write timing adjustment circuit 8 allows it. If permission is granted, a write command is sent to the signal line 22, an address is sent to the memory 7 via the address bus, and 1 word of data is sent via the data bus in the cycle shown in ■ in FIG. The data is sent and written into the memory 7.

Even if the processor read/write timing adjustment circuit 8 permits access to the memory 7, if there is no need to access the processor I, the access to the memory 7 in this access cycle shown in ■ in FIG. It is not executed, resulting in a reduction in current consumption.

When the cycle switching circuit 17 is notified of the end of the access cycle for the processor 1 by the processor accessible timing generation circuit 11, it switches the selectors 20 and 21 to output the output of the display address counter 19 and the select and read command generation circuit. 18 output to memory 7
The address increment signal is sent to the display address counter 19.

Therefore, the chip select signal and read command sent from the select and read command generation circuit 18 to the memory 7 are sent to the memory 7, and the address incremented by the display address counter 19 is calculated in the cycle shown in ■ in FIG. 3(a). Then, the code and attribute data of the next ANK character recorded in the ANK code and attribute data recording area shown in FIG. 4(a) are read out.

Then, the kanji display bit of the attribute data read out to the latch circuit 16 is checked by the kanji display presence/absence determination circuit 12. At this time, if the kanji display bit is logic "0", the latch circuit 15 The latched ANK code is sent to the character generation circuit 13.

The kanji display presence/absence determination circuit 12 has a kanji display bit of logic “0”.
”, the process shown in FIG.
In the cycle shown in a), access to the memory 7 by the processor 1 is executed.

In addition, when the processor 1 does not access the memory 7, the cycle shown in {circle around (2)} in FIG. 3(a) saves current consumption.

The cycles 1 to 2 in FIG. 3(a) constitute one frame, and the next frame operates in the same manner as described above. Therefore, by repeating the above steps, the ANK characters corresponding to the ANK codes recorded in the ANK code and attribute data recording area of the memory 7 are sequentially displayed on the display panel 6.

The kanji display presence/absence determination circuit 12 is latched by the launch circuit 15 when the kanji display bit read out to the latch circuit 16 in the same manner as described above is logic "1" in the cycle shown in ■ in FIG. 3(c). In addition to prohibiting the sending of the ANK code, the cycle switching circuit 17 is notified via the processor accessible timing generating circuit 11, and the address to be sent to the memory 7 of the display address counter 19 is set to the kanji code record shown in FIG. 4(a). The kanji code is switched to the first address of the area and sent to the memory 7, and in the next cycle shown in (■) in FIG. 3(b), the kanji code read from the memory 7 is latched by the latch circuit 15. Then, this kanji code is sent to the character generation circuit 13.

Therefore, 8 bits of the kanji pattern are sent from the character generation circuit 13 to the drive circuit 14 and displayed on the display panel 6 in the same manner as described above. In this case, if the Kanji pattern has an area twice as large as the ANK character pattern, the left half of the Kanji will be displayed.

Therefore, the kanji display presence/absence determination circuit 12 keeps the kanji code latched in the latch circuit 15, notifies it to the cycle switching circuit 17 via the processor accessible timing generation circuit 11, and outputs the kanji code to the display address counter 19.
The address to be sent to the memory 7 of FIG.
The area is switched to the K code and attribute data recording area, and the address is incremented and sent to the memory 7.

Therefore, the next ANK code and attribute data are read from the memory 7 in the next cycle shown in (■) in FIG. 3(b), but the latch circuit 15 continues to hold the Kanji code, so At 16, the Kanji display bit is launched. However, since the kanji display presence/absence determining circuit 12 is designated to display kanji characters in the cycle (■), the logic value of this kanji display bit latched by the latch circuit 16 is ignored.

The kanji display presence/absence determination circuit 12 causes the kanji code latched by the latch circuit 15 to be sent to the character generation circuit 13, and also allows the processor access timing generation circuit 11 to access the memory 7 of the processor 1. Notify.

The processor accessible timing generation circuit 11 generates a signal that allows the processor 1 to access the memory 7 via the processor read/write timing adjustment circuit 8 based on the timing to be sent to the drive circuit 14 of the display access timing generation circuit 9. send it out.

When the processor I needs to change the display content on the display panel 6, it tries to access the memory 7, but it waits for this access until the processor read/write timing adjustment circuit 8 allows it, and then does not perform the access. If permission is granted, the address is sent to the memory 7 via the address bus and the selector 20 switched in the same manner as described above, and one word of data is sent via the data bus in the cycle shown in ■ in Figure 3 (b). is sent and written into the memory 7.

If processor read/write timing adjustment circuit 8
Even if access to the memory 7 is permitted, if there is no need to access the processor 1, the access to the memory 7 will not be executed in this access cycle shown in (■) in FIG. 3(b), resulting in a reduction in current consumption. .

The cycles from ■ to ■ in FIG. 3(b) constitute one frame, and the next frame operates in the same manner as above. However, in the cycle of ■ in the next frame, the cycle switching circuit 17 uses the display address The address sent to the Kanji code recording area of the counter 19 shown in FIG. 4(a) is incremented, and the next Kanji code recorded in this Kanji code recording area is read out. Therefore, by repeating the above steps, the kanji characters will be sequentially displayed on the display panel 6 in accordance with the kanji code recorded in the kanji code recording area of the memory 7.

In this embodiment, one frame has four cycles, so compared to the conventional case where one frame has five cycles, the margin of access time to the memory 7 is improved, and the cycles allocated to read/write by processor I are also improved. , since not all accesses are made by processor l,
Current consumption is reduced.

〔Effect of the invention〕

As explained above, the present invention makes it possible to reduce current consumption by eliminating unnecessary access to memory, thereby extending the life of batteries, etc., and increasing the margin of access time to memory. I can do it.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining details of the present invention, FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention, FIG. 3 is a time chart explaining the operation of FIG. 2, and FIG.
The figure is a diagram illustrating an example of a conventional technique. In the figure, 1 is a processor, 2 is a display control circuit, 3 is a character pattern generation means, 4 is a holding means, 5 is an allocation means, 6 is a display panel, 7 is a memory, 8 is a processor read/write timing adjustment circuit, 9 1 is a display access timing generation circuit; 10 is a clock generation circuit; 11 is a processor-accessible timing generation circuit;
2 is a kanji display presence/absence determination circuit, 13 is a character generation circuit, 14 is a drive circuit, 15, 16
17 is a latch circuit, 17 is a cycle switching circuit, 18 is a select and read command generation circuit, 19 is a display address counter, and 20.21 is a selector. (b) Time chart explaining the visiting essay in Figure 2 Figure 3

Claims (1)

[Scope of Claims] A memory (7) for storing ANK codes, attribute data, and Kanji codes; and a memory (7) for alternately reading ANK codes and attribute data or Kanji codes from the memory (7). When the attribute data read from does not instruct the display of kanji, the ANK character pattern read from the character pattern generation means (3) is displayed based on the read ANK code, and the attribute data instructs the display of kanji. At the time, a kanji pattern having an area N times that of the ANK character read out from the character pattern generation means (3) based on the read kanji code is generated using N times the cycle of the ANK character display. In the display device, a holding means (4) for holding the Kanji code read from the memory (7), and an access cycle of the Kanji code to the memory (7) are assigned to a read/write cycle of the processor (1). Assignment means (5) is provided, and if the attribute data does not instruct display of kanji,
The access cycle of the kanji code to the memory (7) is assigned to the read/write cycle of the processor (1), and if the attribute data instructs the display of kanji characters, the access cycle of the kanji code to the memory (7) is assigned to the read/write cycle of the processor (1). The access cycle is once every N cycles, and in the remaining (N-1) cycles, the kanji code held by the holding means (4) is used to read out the kanji pattern from the character pattern generation means (3). Therefore, the (N-1) cycles for the memory (7) are the read/write cycles of the processor (1).
A display memory access method characterized by allocation to write cycles.