JPH03160668A - Inter-code interference removal device - Google Patents

Abstract

PURPOSE:To remove the non-linear distortion of magnetic recording data of high density and to remove inter-code interference by setting a state with a detection bit and a succeeding bit as objects, applying a Viterbi algorithm, reproducing and decoding data. CONSTITUTION:The state is set with the bit ak in the middle of detection and two succeeding bits ak+1 and ak+2 of data as the objects and the Viterbi algorithm is applied for the state. Namely, a metric is obtained by adders 8-15, square circuits 24-31 and adders 32-39 based on a signal Zk detected from the bit ak which is reproduced in the magnetic head 2 and prescribed predicted sample values Y1-Y8. Then, a survival pass is decided by the comparison 40 of the metric and the system of a decoding value whose tolerance is the highest is obtained in shift registers 53-56 and a discrimination circuit 57. Thus, non- linear distortion by two bits of succeding data can be removed in magnetic recording data of high density and inter-code interference can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an intersymbol interference cancellation device, and particularly to an intersymbol interference cancellation device that applies the Viterbi algorithm. [Summary of the Invention] The present invention provides an intersymbol interference removal device that sets a state from a bit being reproduced and a plurality of bits in the vicinity of the reproduced bit, and applies the Viterbi algorithm to the state to perform magnetic recording. By reproducing the data recorded on the medium, it is possible to decode the data by eliminating the effects of intersymbol interference such as nonlinear distortion and linear distortion in data that is recorded magnetically at high density. be. [Prior Art] When high-density magnetic recording is performed on magnetic recording media, intersymbol interference inevitably occurs. Intersymbol interference will be explained below. For example, when a digital signal is transmitted through a linear transmission line, the input data sequence is (at) (a+=0, l), the output signal is y(t), and the impulse response of the transmission line is g(
t), the digital signal e(t) (e(t)=1,
However, when 0≦t≦T) is transmitted, the output signal c(t) is expressed by the following equation.

c(t) = g(t) * e(t) When the bit interval is T and the above c(t) is used, the output signal y(t) is expressed by the following formula.

y(t) = Σa 1 * c(t-iT) Here, the human data series is (at) = (101100111
0010 ), then c(nT) = O (n ≠
0), the output value of the adjacent bit is not affected by c(t) as shown in Figure 9, so the output signal y (nT) at the time of detection becomes O or 1, making detection easy. .

Therefore, normally, an equalizer is used to
Pulse shaping is performed so that T) = 0. However, this equalization is not sufficient and an equalization error remains, c
When (nT)≠0, adjacent bits are affected as shown in Figure 10, and the output signal y(
nT) does not become O or 1. This is called intersymbol interference. [Problem to be solved by the invention] The above-mentioned intersymbol interference includes linear distortion and nonlinear distortion. Conventionally, inter-symbol interference has been removed by equalizing linear distortion with a linear equalizer (a combination of an integrator, low-pass filter, etc.). However, when this linear equalizer is used, noise is also emphasized, resulting in a problem that the S/N ratio deteriorates. Therefore, it has been proposed to remove intersymbol interference using bus feedback Viterbi decoding ["Bus feedback Viterbi decoding method for detection without opening an eye" Ikeya, Ide, Yamamitsu, IEICE Techniques M.
R87-38]. When intersymbol interference is removed using bus feedback Viterbi decoding, there is a problem in that it can only remove intersymbol interference from data that has already been decoded, and cannot remove intersymbol interference from data that has not yet been decoded. One example of nonlinear distortion is magnetic recording of digital signals, which has recently become possible at high density. Although this magnetic recording process is a nonlinear process, if we assume that the magnetization pattern in the medium is equal to the linear summation of isolated magnetization reversals, the isolated reproduction waveform shown in Figure 11 will be The reproduced waveform can be obtained by convolution. In the figure, ARI indicates a transition region, and 100 indicates a magnetic tape. When recording a digital signal, as shown in FIG. 12, if the recording wavelength T is relatively long, the above assumption holds, and therefore a reproduced waveform can be obtained by convolution of an isolated reproduced waveform. However, as shown in FIG. 13, as the recording wavelength T becomes shorter due to high-density recording, the distance between adjacent bits becomes shorter.
As indicated by the arrow Y, the transition regions ARI begin to overlap. Then, the residual magnetization of the already recorded recording signal magnetic field is disturbed by the new recording signal magnetic field. For this reason, the above-mentioned assumption of linear addition of isolated magnetization reversals becomes difficult to hold, and the actual reproduced waveform no longer matches the waveform obtained by convolution of the isolated reproduced waveform. As a result, there was a problem in that nonlinear distortion as shown by the arrow X in FIG. 13 occurred. Until now, almost no efforts have been made to eliminate the above-mentioned nonlinear distortion, and it has been desired to eliminate intersymbol interference due to nonlinear distortion.

By the way, it is possible to apply an equalizer to remove this nonlinear distortion, but there is a problem that conventional linear equalization is insufficient and cannot deal with nonlinear distortion. It is also possible to apply the above-mentioned bus feedback Viterbi decoding, but in this case, the influence of subsequent data is not removed, making accurate decoding difficult and having problems with nonlinear distortion. Ta. Furthermore, there is a problem that the error rate cannot be improved due to these intersymbol interferences.

Therefore, an object of the present invention is to provide an intersymbol interference removal device that can remove intersymbol interference such as nonlinear distortion and linear distortion in data that is magnetically recorded at high density. [Means for Solving the Problems] The present invention sets a state from a bit being reproduced and a plurality of bits in the vicinity of the reproduced bit, and records the state on a magnetic recording medium by applying the Viterbi algorithm to the state. tlrIi is the reproduced data. [Operation] In this invention, a state is set from the bit being reproduced and a plurality of bits in the vicinity of the reproduced bit, and the Viterbi algorithm is applied to this state. That is, a metric is determined based on the signal detected from the bit being reproduced and a predetermined expected sample value, and a survival path is determined based on a comparison of this metric, and the sequence of decoded values with the highest likelihood is determined. Desired. In this way, data recorded on the magnetic recording medium is reproduced. [Example] Hereinafter, an example of the present invention will be described with reference to FIGS. 1 to 8. In the embodiments of the present invention, first, the removal of nonlinear distortion will be explained in one embodiment, and then the removal of both linear distortion and nonlinear distortion will be explained in another embodiment.

An embodiment of the present invention is shown in FIGS. 1 to 5. FIG. 1 shows the state settings of one embodiment, and FIG. 2 shows a block diagram of an intersymbol interference canceling device.

First, in order to facilitate understanding of the embodiment, application of the Viterbi algorithm will be explained, and then an intersymbol interference cancellation device will be explained. As mentioned above, nonlinear distortion can be caused by the recording magnetic field of subsequent bits disturbing the already established recording magnetic field (residual magnetization) or by recording demagnetization. depends on the subsequent data (the data that is about to be played). Therefore, in the present invention, the detection bit {at} and the bit pattern of the subsequent data are set as states, and the Viterbi algorithm is used. ? The number of states described above is determined by how many bits after the detection bit am, the influence of subsequent data is assumed. For example, as shown in FIG. 1, detection bits a. and 2 bits aK*I, a(*■ total 3 as subsequent data)
Assuming bits, 3 bits ( at s all *
The number of possible states of 1, am+*) is 8 (=2'
), so there are 8 states, namely S1 (000) to S
8 (111) Viterbi decoding is possible. The state transition diagram at this time is shown in Figure 3, and the trellis diagram is shown in Figure 4. Consider the expected sample value Ys at the detection bit }ax.
In this expected sample value Ys, if there is no nonlinear distortion or equalization error, Yl-Y4 is 0 and Y5 to Y8 are 1. By adding nonlinear distortion according to (S-31-38), eight values of Ys=Y1 to Y8 are possible. Note that the expected sample value Ys is an experimentally determined value. This expected sample value Ys can be determined adaptively, for example, by digitizing the reproduced waveform and actually measuring it from the measured value, or by measuring the error rate. The actual reproduced signal is Zk (Zk=Ys+nkin
The Viterbi algorithm is applied with k assumed to be Gaussian noise) and the "length" of the transition leading to a certain state S as (-(Zk-Ys)8). That is, the metrics at time (k-1) are respectively Lm-+' + Lm-
+ ” + '-・-・-'. When Lk-1 is 8,
Maximum Lk-1' + maximum Lk-1 '' * '-・-'. Lk-1 '' while considering the length of each transition
Each transition is selected such that . For example, L
When calculating kl, since the state S1 is reached from S1 or S5 from the state transition diagram of FIG. 3, LkI is [
L O-+ ' (Zk Yl)" ). (L
This is determined by comparing the two values m-t'-(Zk-Y5)'') and selecting the larger value.This results in the most probable state transition, that is, the most probable decoding sequence. In this way, it is possible to select the most likely decoding sequence while predicting the bit pattern of the subsequent data that has not yet been decoded.
This will be explained with reference to the figure. In the configuration shown in FIG. 2, the signal Zk reproduced from the magnetic tape 1 by the magnetic head 2 at time t (k) is sent to the PLL 4 and the switch 5 via the equalizer amplifier 3.
is supplied to terminal 5a of. In the PLL 4, a clock signal CLK is extracted from the reproduced signal Zk. This clock signal CLK is taken out from the terminal 6 and is supplied to each circuit inside the device.

The switch 5 receives a clock signal CL supplied from a terminal 7.
Opening/closing is controlled by K. When switch 5 is closed, that is, terminals 5a and 5b are connected, signal Zk is supplied to adders 8 to 15, respectively. Adders 8-15 add predetermined sample values Y1-Y8 supplied from terminals l6-23 and signal Zk. The outputs from adders 8 to 15 are sent to square circuits 24 to 3.
It is supplied to l. In the squaring circuits 24 to 3l, the adders 8 to
Output (Zk-Yl) to (Zk-Y8) supplied from 15
) is squared and given a negative sign. This square circuit 24
Output from ~31 (-(Zk-Yl) wealth) ~(1(Zk
-Y8)") are supplied to adders 32 to 39. In the adder 32, the above-mentioned output (-(Zk-Yl)") and the time L(k- The metrics Lk-1' or Lk-1' of 1) are added, and the metrics l and IIl at time t (k) are obtained (Lk' = L, k-,' - (Zk-Yl)
Small, Lk=Lb-t' (Zk Y5)")
, this metric LA1 is supplied to the memory 44. The memory 44 takes in the metric Lm based on the clock signal section CLK supplied via the terminal 52 and supplies it to the comparator 40. The adder 33 adds the above-mentioned output (-(Zk-Y2)'') and the metric Lk-1' or Lk-1' at time t (k-1) supplied from the comparator 40, and calculates the time. The metric L.' at t (k) is determined (Lk'' = L.-1
' - (Zk-Y2)'', t.''=L,k-,
5- (Zk-Y2)"), this metric l-
kt is supplied to the memory 45. The memory 45 takes in the metric L,' based on the clock signal CLK supplied via the terminal 52, and supplies it to the comparator 41. The adder 34 outputs the above-mentioned output (-(Zk-Y3)
”) and the metric Lk-1 ``or Lk-1'' at time t(k-1) supplied from the comparator 41, the metric k3 at time t(k) is calculated, and this metric L,3 is supplied to the memory 46. The memory 46 takes in the metric Lk3 based on the clock signal CIJ and supplies it to the comparator 42.

The adder 35 calculates the time Lk-1 based on the above-mentioned output (1(Zk-Y4)t) and the metric Lk-1 ``or Lk-1'' of the time t(k-1) supplied from the comparator 4l. The metric L% in (k) is determined, and this metric L% is supplied to the memory 47. memory 47
Then, based on the clock signal CLK, the metrics l,
II4 is taken in and supplied to the comparator 43. The adder 36 uses the above-mentioned output (-(Zk-Y5) value) and the metric Lm-1' or L-ar,? of the time t(k-1) supplied from the comparator 42. Based on the time t
The metric Lk' in (k) is determined, and this metric LkS is supplied to the memory 48. memory 48
Then, based on the clock signal CLK, the metric Lk
S is taken in and supplied to the comparator 40. The adder 37 outputs the above-mentioned output (-(Z k-Y 6)"
) and the metric Lk-1' or Lk-1' at time t(k-1) supplied from the comparator 42,
The metric L at time t (k). h is calculated,
This metric L,' is supplied to the memory 49. The memory 49 takes in the metric L,' based on the clock signal CLK and supplies it to the comparator 4l. In the adder 38, based on the above-mentioned output (-(Zk-Y7)'') and the metric Lk-1' or Lll-1'' at time t(k-1) supplied from the comparator 43,
Metric [, lI? at time t (k)? is calculated, and this metric Lk7 is supplied to the memory 50.
The memory 50 takes in the metric L1' based on the clock signal CIJI and supplies it to the comparator 42. The adder 39 calculates the time U based on the above-mentioned output (1(Zk-Y8)'') and the metric L1, 4 or Lll-1- of the time t (k-1) supplied from the comparator 43.
The metric Lk1 in (k) is obtained, and this metric L. ' is supplied to the memory 5l. In the memory 5l, the metric L. “
is taken in and supplied to the comparator 43. The comparators 40 to 43 compare the metrics l, kl, L, and @ according to the trellis diagram in FIG. The transition is determined. Then, “1” or “゛゜0” is transferred to shift registers 53 to 56.
Supply to. At the same time, the comparators 40 to 43 output metrics I, . I=l,. @ is sent to adders 32-39. Eedback will be given.

In the horizontal command shown in Figure 2, states S1 and 32, S3 and S
4. For S5 and S6, S7 and S8, Metlink Lk-1
A common value is used for each value. This will be explained below. Looking at the state transition diagram in FIG. 3 and the trellis diagram in FIG. 4, only states S1 and 35 lead to state S1. 2
Similarly, only states S1 and 55 lead to state 71!32. Condition J! The path leading to 3iSl is determined by the following formula. L
m-1'-(Z k-Y 1)">L,-+'-(Z
k-Y l)" ・--{1) In the case of this equation (1), it is determined that the transition is from state S1 to state S1. Lm-1'-(Z k-Y 1)"< Lk -1'-(
Z k−Y 1)”・−・−・(2) In the case of this equation (2), it is determined that there is a transition from state S5 to state BSl.Here, the term (Zk−Yl)” is Because it is common (1)
, equation (2) can be rewritten as follows. Ll+-1'
＞Li＋−＋ '・・・−・−・−・・−・・・−・
(3) Lk-, '<t,k-+' -・---1-・・-・−・・−・(4) Moreover, the path leading to the state LQS2 is determined by the following formula. Lk-1'-(Z k-Y 2)">Lll-+'-
(Z k−Y 2)” In the case of this equation (5), the state S
It is determined that the transition is from state 1 to state S2.

Lm-1'-(Z k-Y 2)''<Lk-1'-(
Z k−Y 2)” In the case of this equation (6), the shape 11s
It is judged that the transition is from 5 to 2. Here, since the term (Zk-Y2)'' is common, (5)
, equation (6) can be rewritten as follows. L 1-+'
>Li+-+ '・One・−・−・−・・・−・(7)L
m-t'<Lm-+'・-・−・・・・・・・−
-(8) Equations (3) and (4) are exactly the same as equations (7) and (8). This leads to the following two conclusions. ■． Regardless of whether the transition destination is jlqsISS2, the most probable path is determined using the same discriminant. ■． The metric at that time is that the transition destination is state S.
The same metric for either 1 or S2...-{
5) ...-...(6) It can be found by adding [Lm-+', Lm-+'). The above two conclusions are based on other conditions JllS3 and S4,
The same applies to S5 and S6, and S7 and S8. Therefore, as shown in the structure of FIG.
The same value of metric can be used for each of 3 and S4, S5 and S6, and S7 and S8. The comparator 40 determines the transitions leading to states 31 and 32, the comparator 41 determines the transitions leading to states jlls3 and S4, and the comparator 42 determines the transitions leading to the states jlls3 and S4.
The transitions leading to ffis5 and S6 are determined, and the comparator 43 determines the transitions leading to states S7 and S8. As a result of this comparison, the decoding at each pass {
i (1 or 0) is determined. This decoded value is supplied to shift registers 53-56. Originally, the number of shift registers should be the same as the number of states, but in this example, as described above, the same discriminant is used and the same decoded value is obtained when reaching state S1 and when reaching state S2. The same applies to states S3 and 34, S5 and S6, and S7 and S8, so the number of shift registers is half of the number of eight states. The shift register 53 contains the decoded value of the path leading to state Sl-32, and the shift register 54 contains the decoded value of the path leading to state S1-32.
The decoded value of the path leading to 4, the shift register 55 has the state 11
The decoded values of the path leading to states s5 and S6 and the decoded values of the path leading to states S7 and S8 are sent to the shift register 56. The shift registers 53 to 56 are interconnected according to a trellis diagram, and serial or parallel loading of decoded values is performed according to the selection of the survival path described above. Serial or parallel loading of the decoded values in the shift registers 53 to 56 is performed in synchronization with the clock signal CLK supplied from the terminal 52 as shown in FIG. This corresponds to merging paths on a trellis diagram. From shift registers 53 to 56,
The decoded value is supplied to the discrimination circuit 57. The four decoded values supplied to the discriminator circuit 57 should originally have one loss, but in reality, it is quite conceivable that they do not match due to noise or other influences. Therefore, in the determination circuit 57, a decoded value is selected based on criteria such as majority vote and metric size, and is taken out from the terminal 58.

According to this embodiment, detection bit am and detection bit a
．． The state is set for the 2-bit a1+ and aK-th subsequent data, and the Viterbi algorithm is applied to reproduce and decode the data. 2 bits of data a1l
Nonlinear distortion caused by saKhR can be removed, and intersymbol interference can be removed. In addition, since a linear equalizer is not used to remove this intersymbol interference, it is possible to prevent S/N from deteriorating, and since path feedback Viterbi decoding is not used, data that has not yet been decoded can be removed. Intersymbol interference from can be removed. In this embodiment, in order to eliminate intersymbol interference, detection bits all+ and bits a. ．． 1.a. 8
Are you setting the state targeting the 3 bits of ? However, the number of target bits is not limited to this and can be set arbitrarily. Other embodiments of the invention are shown in FIGS. 6-8. This other embodiment differs from the above-mentioned embodiment in that it takes into consideration the bits aK-1 and all+1 before and after the detection bit a1. That is, in the above-mentioned embodiment, an example is explained in which nonlinear distortion, which is the influence of the subsequent bits a1 and a wet on the detected bit, is removed, but in other embodiments, the detected bits This also takes into account linear distortion, which is the effect of all-1. In this other embodiment, as shown in FIG. 6, the detection bits a. The values of l bits aK-1 and aK+1 before and after are set as the "state". Then, the most likely decoding sequence is found based on the Viterbi algorithm. First, we will explain the relationship between intersymbol interference and states. Assuming that there is no noise, the value of the signal at the detection time t=KT is uniquely determined. If the equivalent error CK is a. =0
Then y* -0 % a K -13+1=1.
If there is an error as shown in Figure 7, it is expressed by ν or the equation below due to intersymbol interference. If is O, then the equalization is νK3Σa! 'CI+-1 {In general, when equalization error C1 remains over n points, y takes 2s values. For example, as shown in FIG.
+ l, C. ,C, remain, there are 23=8 possible values for y. (ae+-+, a., a
ll )− (00 0)y* =0 (=yg+)
State Sl (ax-+, ax, all+1) ”” (00
1) νt −C−+ (=3′ sz) state S2(
am-+ , am , awL-+ ) − (0 1
0) 9 m = 1 ("l ss) shape 1133 (
am-+, awt, a*. t ) '= (O l
1))l*−1+C−+(=ys
a) Condition! ! S4 (ax-t, am, all
) = (1 0 0)yx =C+ (=y
ss)-like LQS5 (a1+ , awr , at-+
) = (1 0 1) νx=c−++C+
(=3'S6) State S6 (am-1, aK,
ax-+ ) = (1 1 0))' *
= 1 +C1 (=)' s,) state S7 (ax
−+ , ax , ax−+ ) = (1
1 1) yi=1+C-++C+ C=yss
) shape [38 Furthermore, if nonlinear distortion is to be considered, nonlinear distortion α▲ corresponding to each pattern may be determined and added by some method. Nonlinear distortion basically depends on the pattern, so in this way it can be expected to detect the effects of nonlinear characteristics sufficiently. (ax-+, aKs az*1) = (O O
O)y. =0+α+(””)'s+) state S1(aI
+-1, au, a*. + ) = (oo 1)”) *
=C-++αg (=)l sz)-like Llts2(a
m-+, ax, am. + ) = (0 1 0
)yyo=l+α3(””)lss) likejlls3(a
m-+, ax, aK-1) ” (0
1 1 ) 3'*-1+C-1+αa (=3'
! 4) LqS4 (a.K-1, al, aK
．． I) = (1 0 0)yw=C+ +
αs (=yss)-like 51q35 (aK-+,
aK, at-+ ) ” (l O l ))
) * = C−+ + C + +α6 (=3
'sa)-like JlqS6(ax-+, awt%
aK*1 ) − (1 1 0) νm=1+C
1 +αt (-3'st) state S7 (am-+
% ax, all41) − (1 1 1
)9 w ”=1+C-++C1 +αI (-3
'sw) State S8 At this time (all-1, all
, all+1) is considered as a state and the Viterbi algorithm is applied. The content of the application of the Viterbi algorithm, circuits, transition diagrams, trellis diagrams, etc. is the same as in the previous embodiment, and common parts are given the same reference numerals and redundant explanations will be omitted. According to this other embodiment, in addition to the effects of the above-mentioned embodiment, the detection bit }am and each l bit Fall-1 before and after it
, aκ1, and the data is decoded by applying the Viterbi algorithm.
Both linear distortion caused by K-1, a-, and non-linear distortion caused by bit a1 of the subsequent data following detection bit }ax can be removed, and inter-symbol interference can be removed. [Effects of the Invention] According to the intersymbol interference canceling device according to the present invention, the state is set for the detected bit and the bits before and after it, and the data is decoded by applying the Viterbi algorithm. It has the effect of removing non-glandular distortion in data that is magnetically recorded at a high density and intersymbol interference. It also has the effect of eliminating linear distortion in data that is magnetically recorded at high density and intersymbol interference. This has the effect of improving the error rate. In addition, when removing intersymbol interference, since a linear equalizer is not used, noise is not emphasized and S/N
This can prevent deterioration of the Furthermore, since it does not rely on path feedback Viterbi decoding, it has the effect of being able to remove intersymbol interference from data that has not yet been decoded.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram showing state settings in an embodiment of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, Fig. 3 is a state transition diagram, and Fig. 4 is a trellis line. 5 is a schematic diagram showing the operation of the shift register, FIG. 6 is an explanatory diagram showing state settings in another embodiment of the present invention, and FIG. 7 is a schematic diagram showing the operation of the shift register.
The figure is an explanatory diagram showing inter-symbol interference due to equalization error, Figure 8 is an explanatory diagram showing an example of equalization error, and Figures 9 and 10 respectively show the level of the output signal depending on the presence or absence of equalization error. FIG. 11 is a diagram showing the magnetization state of an isolated reproduction waveform, FIG. 12 is a diagram showing the magnetization state when the wavelength of the recording signal is long, and FIG.
The figure shows the magnetization state and nonlinear distortion when the wavelength of the recording signal is short. Explanation of main symbols in the drawings 1, 100: magnetic tape, a. : detection bit, aK-I
SaK◆I% alt+l% aK*2:
Bits %S, Sl to S8: Status.

Claims (1)

[Claims] A state is set from a bit being reproduced and a plurality of bits in the vicinity of the reproduced bit, and the Viterbi algorithm is applied to the above state to reproduce data recorded on a magnetic recording medium. An intersymbol interference removal device characterized by: